JP2007027460A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can prevent generation of a void in forming a Cu wiring and prevent deterioration in adhesiveness between a barrier metal layer and a Cu layer, and a semiconductor device manufactured by this method. <P>SOLUTION: In the method of manufacturing a semiconductor device in which a wiring is formed on a substrate 10, the barrier metal layer 16 consisting of a Ta-based barrier metal material and an alloy of Cu and/or Ag is firstly formed on the substrate 10. Then, a metal layer 17 containing Cu is formed on the upper layer of the barrier metal layer 16 by electrolytic plating using the barrier metal layer 16 as an electrode, and the barrier metal layer 16 and the metal layer 17 are processed into a wiring pattern. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a trench wiring by a damascene or a dial damascene process and a manufacturing method thereof.

  Conventionally, an aluminum-based alloy has been used as a material for fine wiring of a high-density integrated circuit formed on a semiconductor wafer. However, in order to further increase the speed of the semiconductor device, it is necessary to use a material having a lower specific resistance as a wiring material, and copper, silver, or the like is preferable as such a material. In particular, copper is expected to be a next-generation material because it has a low specific resistance of 1.8 μΩcm, which is advantageous for increasing the speed of semiconductor devices and has an electromigration resistance that is an order of magnitude higher than that of aluminum-based alloys.

In wiring formation using copper, since so-called dry etching of copper is generally not easy, a so-called damascene method is used.
For example, as described in Patent Documents 1 and 2, for example, a wiring groove having a predetermined pattern is formed in advance in an interlayer insulating film made of, for example, silicon oxide, and the inner wall of the wiring groove is covered with Ta by a sputtering method. A barrier metal layer to be a diffusion barrier is formed, a Cu seed layer to be a seed for electrolytic plating is formed on the barrier metal layer by a sputtering method, and a wiring material (Cu) is formed in the wiring groove using the seed layer. In this method, after the embedding, excess wiring material is removed by chemical mechanical polishing (hereinafter referred to as CMP) to form wiring.

  Further, there is also known a dual damascene method in which after connecting holes (contact holes) and wiring grooves (trench) are formed, wiring materials are filled in a lump in the same manner as described above, and excess wiring materials are removed by CMP.

  FIG. 10A is a schematic diagram for explaining a problem in the case where the laminated film of the barrier metal layer and the seed layer is formed as described above in the damascene or dual damascene process for forming the Cu wiring.

For example, a first insulating film 50 made of silicon oxide or the like is formed on a substrate (not shown), and a plug 51 is embedded through the first insulating film 50.
A second insulating film 52 is formed to cover the first insulating film 50 and the plug 51, and a wiring trench TR is formed so as to expose the upper surface of the plug 51.
A barrier metal layer 53 made of Ta is formed to cover the inner wall surface of the wiring trench TR, and a Cu seed layer 54 is further formed thereon.

By performing electrolytic plating using the above seed layer, as shown in FIG. 10B, the wiring trench TR is embedded, and a metal layer 55 containing copper is formed integrally with the seed layer.
Thereafter, the metal layer 55 and the barrier metal layer 53 outside the wiring trench TR can be removed by CMP treatment to obtain a desired trench wiring.

Here, if the miniaturization of the wiring advances in the manufacturing process with the above configuration, as shown in FIG. 10A, there is a problem that the overhang of the seed layer 54 at the edge of the wiring groove of the seed layer becomes large. When the overhang is increased and the electrolytic plating process is performed, as shown in FIG. 10B, a filling defect such as a void V occurs in the metal layer 55 to be formed.
The phenomenon in which the above-described overhang and void are generated becomes more prominent as the wiring becomes finer.

  Non-Patent Document 1 reports a technique in which a Ru film is formed as a barrier metal layer in the above-described damascene process or dual damascene process, and a metal layer containing Cu is directly formed on the Ru film by electrolytic plating. Has been.

When a metal layer containing Cu is directly formed on the Ru film, the surface of the barrier metal layer made of Ru is oxidized before the plating process, and the adhesion strength between the barrier metal layer and Cu is extremely weak. There is a possibility of becoming.
JP 2005-129746 A JP 2004-319616 A Zhi-wei Sun, Renren He and John O. Dukovic, Conference Proceedings AMC XX, p.531-537 (2005), Materials Research Society

  The problem to be solved is that when forming a wiring containing Cu, a defective filling such as a void occurs, and the adhesion between the barrier metal layer and the metal layer containing Cu is lowered.

  The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which wiring is formed on a substrate, and a barrier metal layer made of an alloy of a Ta-based barrier metal material and Cu and / or Ag is formed on the substrate. Forming a metal layer containing Cu by electrolytic plating using the barrier metal layer as an electrode above the barrier metal layer; and processing the barrier metal layer and the metal layer into a wiring pattern. .

The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which wiring is formed on a substrate. First, a barrier metal layer comprising a Ta-based barrier metal material and an alloy of Cu and / or Ag is formed on the substrate. Form.
Next, a metal layer containing Cu is formed on the upper layer of the barrier metal layer by electrolytic plating using the barrier metal layer as an electrode, and the barrier metal layer and the metal layer are processed into a wiring pattern.

  The semiconductor device of the present invention is a semiconductor device in which wiring is formed on a substrate, and the wiring includes a barrier metal layer made of an alloy of Ta-based barrier metal material and Cu and / or Ag formed on the substrate. And a metal layer containing Cu formed on the barrier metal layer, and the barrier metal layer and the metal layer are processed into a wiring pattern.

  The semiconductor device of the present invention is a semiconductor device in which wiring is formed on a substrate. Here, a barrier metal layer made of an alloy of a Ta-based barrier metal material and Cu and / or Ag is formed on the substrate, and a metal layer containing Cu is formed on the barrier metal layer. These barrier metal layer and metal The layer is processed into a wiring pattern to configure the wiring.

  In the semiconductor device manufacturing method of the present invention, a barrier metal layer is formed of a Ta-based barrier metal material and an alloy of Cu and / or Ag, and an electrolytic plating process for depositing Cu is performed using the barrier metal layer. The barrier metal layer also functions as a seed layer for the electrolytic plating process, and even when the wiring pattern is miniaturized by depositing the Cu layer directly on the barrier metal layer by the electrolytic plating process It is possible to reduce voids due to overhang, which is a risk. Further, when formed in this manner, formation of an oxide film on the surface of the barrier metal layer can be reduced, and furthermore, since the barrier metal layer has an anchor effect, sufficient adhesion between the Cu layer and the barrier metal layer can be secured.

  In the semiconductor device of the present invention, a barrier metal layer is formed of a Ta-based barrier metal material and an alloy of Cu and / or Ag, and Cu can be deposited by electrolytic plating using the barrier metal layer. Even if the wiring pattern is miniaturized, the occurrence of overhangs and voids is suppressed. Further, the formation of an oxide film on the surface of the barrier metal layer is reduced, and since the barrier metal layer has an anchor effect, sufficient adhesion between the Cu layer and the barrier metal layer is ensured.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the present embodiment.
For example, a first insulating film 11 made of silicon oxide is formed on a substrate 10 on which an electronic circuit (not shown) is formed, and a contact plug 12 made of tungsten or the like penetrates the first insulating film 11 and is not formed. It is formed so as to be connected to the illustrated electronic circuit.
A second insulating film 13 made of an organic insulating material such as polyarylene is formed on the first insulating film 11, and a third insulating film 14 made of silicon oxide or the like is formed on the second insulating film 13.
In the second insulating film 13 and the third insulating film 14, the first wiring trench TR1 in which the upper surface of the contact plug 12 is exposed is formed on the bottom surface.

  A barrier metal layer 16 made of an alloy of a Ta-based barrier metal material and Cu and / or Ag is formed so as to cover the inner wall of the first wiring trench TR1, and the first wiring trench TR1 is embedded in the upper layer to form the Cu A first wiring 17a made of is formed. The first wiring 17 a is connected to the contact plug 12 through the barrier metal layer 16.

A fourth insulating film 18 made of, for example, silicon carbide, for example, a fifth insulating film 19 made of, for example, silicon carbide oxide (SiOC), for example, polyarylene is coated on the third insulating film 14 so as to cover the first wiring 17a. A sixth insulating film 20 made of an organic interfacial material and a seventh insulating film 21 made of, for example, silicon oxide are formed.
In the fourth insulating film 18 and the fifth insulating film 19, a contact hole CH exposing the upper surface of the first wiring 17a is opened on the bottom surface, and communicates with the contact hole CH, so that the sixth insulating film is formed. A second wiring trench TR <b> 2 is formed in the 20 and the seventh insulating film 21.

A barrier metal layer 26 made of an alloy of Ta-based barrier metal material and Cu and / or Ag is formed so as to cover the second wiring trench TR2 provided in communication and the inner wall of the contact hole CH. , Cu is formed by filling the second wiring trench TR2 and the contact hole CH, the contact plug 27a is integrally formed in the contact hole CH, and the second wiring 27b is integrally formed in the second wiring trench TR2. . The contact plug 27 a formed integrally with the second wiring 27 b is connected to the first wiring 17 a through the barrier metal layer 26.
A barrier film such as CoWP may be formed on the surface of the first wiring 17a and the second wiring 27b.

  In the semiconductor device of the present embodiment, a barrier metal layer is formed of a Ta-based barrier metal material and an alloy of Cu and / or Ag, and Cu can be deposited by electrolytic plating using the barrier metal layer. Even if the wiring pattern is miniaturized, the occurrence of overhangs and voids is suppressed. Further, the formation of an oxide film on the surface of the barrier metal layer is reduced, and since the barrier metal layer has an anchor effect, sufficient adhesion between the Cu layer and the barrier metal layer is ensured.

Next, a method for manufacturing the semiconductor device according to the above-described embodiment will be described.
First, as shown in FIG. 2A, silicon oxide is deposited on a substrate 10 on which an electronic circuit (not shown) is formed by, for example, a CVD (Chemical Vapor Deposition) method to form a first insulating film 11. Then, a contact hole reaching an electronic circuit (not shown) is pattern-opened and filled with tungsten or the like so as to connect the contact plug 12 to the electronic circuit (not shown).
The second insulating film 13 is formed on the first insulating film 11 by applying an organic insulating material such as polyarylene to a thickness of 200 nm.
A third insulating film 14 is formed on the second insulating film 13 by depositing silicon oxide with a thickness of 200 nm by, for example, a plasma CVD method using silane as a raw material.

Next, as shown in FIG. 2B, a resist film 15 having an opening in the pattern of the first wiring is formed on the third insulating film 14 by a photolithography process.
Etching such as RIE (reactive ion etching) is performed using the obtained resist film 15 as a mask, and the first wiring trench TR1 is pattern-opened in the third insulating film. Silicon oxide can be etched with a high selectivity of, for example, 100 or more with respect to an organic insulating material such as polyarylene.

  Next, as shown in FIG. 2C, the patterned third insulating film 14 is used as a hard mask, and etching such as RIE is performed to transfer the opening pattern of the first wiring trench TR1 to the second insulating film 13. To do. An organic insulating material such as polyarylene can be etched with a high selectivity of, for example, 100 or more with respect to silicon oxide. By this etching process, the resist film 15 is removed.

  Next, as shown in FIG. 3A, the inner wall surface of the first wiring trench TR1 is coated by a physical vapor deposition method such as sputtering using a Ta-based barrier metal material and an alloy target of Cu and / or Ag. The barrier metal layer 16 is formed by depositing a Ta-based barrier metal material and an alloy of Cu and / or Ag with a thickness of 10 nm.

  Since Cu or Ag added to the Ta-based barrier metal material lowers the electrical resistance of the barrier metal layer 16, when a metal layer containing Cu is formed on the barrier metal layer by electrolytic plating in the next step. In addition, the barrier metal layer 16 can be used as an electrode, thereby making it unnecessary to form a seed layer that needs to be formed conventionally.

  If the amount of Cu and / or Ag added to the barrier metal material is too small, the adhesion force between the metal layer 17 containing Cu and the barrier metal layer 16 formed in the upper layer of the barrier metal layer 16 in the next step will be reduced. If it is too large, the properties of the diffusion barrier of the barrier metal layer 16 itself will be impaired. Therefore, Cu and / or Ag is preferably 5 to 15 atomic%, for example, about 10 atomic%.

The deposition conditions for the Ta-based barrier metal material and the Cu and / or Ag alloy film are, for example, as follows.
DC power: 6kW
Process gas: Ar = 8 sccm → 0 sccm → 12 sccm
Pressure: 0.4Pa
Deposition temperature: 100 ° C
Substrate bias: 300W

  Next, as shown in FIG. 3B, for example, a metal containing Cu is deposited to a thickness of 1000 nm by electrolytic plating using the barrier metal layer 16 as one electrode, and the first layer is formed on the barrier metal layer 16. The metal layer 17 is formed by filling the wiring trench TR1.

In the above-described electrolytic plating treatment, an electrode having a configuration that is concentrically divided into an inner side and an outer side may be used as a counter electrode used for the electrolytic plating, if necessary. It is possible to adjust the progress of plating in the region inside and outside the wafer.
For example, as shown below, the first step and the second step are combined to perform plating for 110 coulombs in the inner region, and then the third step is performed using the inner electrode and the outer electrode at an equal power ratio to obtain a total film thickness. Plating until 1000 nm.

Electrolytic plating method (copper sulfate plating)
First step: 10 A / 2 seconds / 90 rpm (inner electrode 100%)
Second step: 3A / 30 sec / 90 rpm (inner electrode 100%)
Third step: 18A / until the total reaches 1000 nm
(Inner electrode: outer electrode = 50%: 50%)

Next, heat treatment is performed to grow Cu grains. Next, as shown in FIG. 3C, the metal layer 17 outside the first wiring trench TR1 is removed by, for example, CMP processing, and then CMP processing is performed. To remove the barrier metal layer 16. At this time, the third insulating film 14 may be thinned by about 100 nm.
Thus, the first wiring 17a is embedded in the first wiring trench TR1.

  Subsequently, for the purpose of removing the oxide film on Cu and the anticorrosive agent of Cu formed on the Cu surface in the CMP process, the substrate is washed with an organic acid such as citric acid or an oxalic acid aqueous solution. By electrolytic plating, a barrier film such as CoWP is formed to cover the upper surface of the first wiring 17a.

Next, as shown in FIG. 4A, a film of 50 nm thick silicon nitride (SiCN), silicon carbide (SiC), or silicon nitride acting as an upper etching stopper film using trimethylsilane and NH ₃ as raw materials. A fourth insulating film 18 is formed by depositing with a thickness.
Next, silicon carbide oxide (SiOC) is deposited to a thickness of 200 nm on the fourth insulating film 18 by plasma CVD using trimethylsilane or the like as a raw material to form a fifth insulating film 19.

Next, an organic insulating material such as polyarylene is applied to the upper layer of the fifth insulating film 19 with a thickness of 200 nm to form the sixth insulating film 20.
Next, a seventh insulating film 21 is formed on the sixth insulating film 20 by depositing silicon oxide with a film thickness of 200 nm, for example, by plasma CVD using silane as a raw material.
Further, as a hard mask for processing the second wiring trench and the contact hole, silicon nitride and silicon oxide are stacked on the seventh insulating film 21 by, for example, plasma CVD, and the eighth insulating film 22 and the ninth insulating film 23 are formed. Form each one.

Next, as shown in FIG. 4B, a resist film 24 having an opening in the pattern of the second wiring is formed on the ninth insulating film 23 by a photolithography process.
Etching such as RIE is performed using the obtained resist film 24 as a mask, and a second wiring trench TR2 is pattern-opened in the ninth insulating film 23. Silicon oxide can be etched with a selectivity of, for example, 10 or more with respect to silicon nitride.

Next, after removing the resist film 24 by an ashing process or the like, as shown in FIG. 5A, a step of the ninth insulating film 23 of, for example, 25 to 50 nm is covered by a photolithography process. A resist film 25 is formed on the ninth insulating film 23 and the eighth insulating film 22 so as to have a contact hole pattern opened from the bottom of the second wiring trench.
Etching such as RIE is performed using the obtained resist film 25 as a mask, a contact hole CH pattern is opened in the eighth insulating film 22, and then a contact hole is formed in the seventh insulating film 21 using the eighth insulating film 22 as a mask. The opening pattern is transferred and then transferred to the sixth insulating film 20. The resist film 25 is removed by the etching process of the sixth insulating film 20.
In this manner, the contact hole CH is pattern-opened through the eighth insulating film 22, the seventh insulating film 21, and the sixth insulating film 20. An organic insulating material such as polyarylene can be etched with a high selectivity of, for example, 100 or more using silicon oxide as a mask.

  Next, as shown in FIG. 5B, the eighth insulating film 22 is patterned using the ninth insulating film 23 as a mask, and the pattern of the second wiring trench TR2 is transferred to the eighth insulating film 22. Silicon nitride can be etched with a selectivity of, for example, about 3 using silicon oxide as a mask. At this time, the contact hole pattern is etched to a depth in the middle of the fifth insulating film 19.

  Next, as shown in FIG. 6A, the seventh insulating film 21 is patterned using the eighth insulating film 22 as a mask, and the pattern of the second wiring trench TR <b> 2 is transferred to the seventh insulating film 21. At this point, the ninth insulating film 23 is completely removed, and the contact hole pattern is transferred to the fifth insulating film 19. Silicon carbide oxide can be etched with a selection ratio of 10 or more with respect to silicon nitride, silicon carbide, or silicon nitride carbide.

Next, as shown in FIG. 6B, the sixth insulating film 20 is patterned using the seventh insulating film 21 as a mask, and the pattern of the second wiring trench TR <b> 2 is transferred to the sixth insulating film 20.
Further, the fourth insulating film 18 is patterned using the fifth insulating film 19 as a mask, and the pattern of the contact hole CH is transferred to the fourth insulating film 18. In this etching, the eighth insulating film 22 is completely removed.
As described above, contact holes can be formed in the fourth insulating film 18 and the fifth insulating film 19, and the second wiring trench TR2 can be formed in communication with the sixth insulating film 20 and the seventh insulating film 21.

  Next, as shown in FIG. 7A, the inner wall surface of the contact hole CH and the second wiring trench TR2 is coated by a physical vapor deposition method such as sputtering, for example, and a Ta-based barrier metal material and Cu and / or Ag. The barrier metal layer 26 is formed by depositing the alloy with a thickness of 10 nm. The film forming conditions for the Ta-based barrier metal material and the alloy of Cu and / or Ag are the same as described above.

  Next, as shown in FIG. 7B, copper is deposited with a film thickness of 1000 nm by, for example, electrolytic plating using the barrier metal layer 26 as one electrode, and contact holes CH and A metal layer 27 containing Cu is formed to fill the second wiring trench TR2.

Next, heat treatment is performed to grow Cu grains, and further, for example, the metal layer 27 outside the second wiring trench TR2 is removed by a CMP process, and then a CMP process is performed to remove the barrier metal layer 26. At this time, the seventh insulating film 21 may be thinned.
Thereby, as shown in FIG. 1, the contact plug 27a made of a metal layer containing Cu and embedded in the contact hole CH and the second wiring 27b embedded in the second wiring trench TR2 are integrally formed. can do.

  Subsequently, for the purpose of removing the oxide film on Cu and the anticorrosive agent of Cu formed on the Cu surface in the CMP process, the substrate is washed with an organic acid such as citric acid or an oxalic acid aqueous solution. By electrolytic plating, a barrier film such as CoWP is formed to cover the upper surface of the second wiring 27b.

  According to the method of manufacturing a semiconductor device according to the present embodiment, the barrier metal layer is formed of the Ta-based barrier metal material and the alloy of Cu and / or Ag, and the electrolytic plating process for depositing Cu using the barrier metal layer. In other words, the barrier metal layer also functions as a seed layer for the electrolytic plating process. By depositing the Cu layer directly on the barrier metal layer by the electrolytic plating process, the wiring pattern can be made fine. Even when the process is advanced, voids due to overhang, which is a risk, can be reduced. Further, when formed in this manner, formation of an oxide film on the surface of the barrier metal layer can be reduced, and furthermore, since the barrier metal layer has an anchor effect, sufficient adhesion between the Cu layer and the barrier metal layer can be secured.

Second Embodiment In the present embodiment, the trench wiring and the contact plug are integrally formed by a dual damascene process similar to the first embodiment, but the insulating film structure has a simpler configuration.

For example, as shown in FIG. 8A, a first insulating film 41 is formed by depositing silicon oxide on a substrate 40 on which an electronic circuit (not shown) is formed by, for example, a CVD method. A contact hole reaching the electronic circuit is patterned and filled with tungsten or the like so as to connect the contact plug 42 to an electronic circuit (not shown).
A second insulating film 43 and a third insulating film 44 are laminated on the upper layer of the first insulating film 41 using an organic insulating material such as polyarylene, or an insulating material such as silicon oxide or silicon nitride.

  Next, as shown in FIG. 8B, pattern etching is performed on the second insulating film 43 and the third insulating film 44, contact holes CH are formed in the second insulating film 43, and wiring grooves are formed in the third insulating film 44. TR is formed in communication.

  Next, as shown in FIG. 8C, the inner wall surface of the contact hole CH and the wiring trench TR is coated by a physical vapor deposition method such as sputtering, for example, and a Ta-based barrier metal material and an alloy of Cu and / or Ag. Thus, the barrier metal layer 45 is formed.

  Next, as shown in FIG. 9A, for example, Cu is deposited by an electrolytic plating process using the barrier metal layer 45 as one electrode, and the contact hole CH and the wiring trench TR are embedded in the upper layer of the barrier metal layer 45. A metal layer 46 containing Cu is formed.

Next, as shown in FIG. 9B, the metal layer 46 outside the wiring trench TR is removed by, for example, a CMP process, and then the CMP process is performed to remove the barrier metal layer 45.
Thereby, the contact plug 46a made of a metal containing Cu and embedded in the contact hole CH and the wiring 46b embedded in the wiring trench TR can be integrally formed.
Subsequently, if necessary, a barrier film such as CoWP is formed by covering the upper surface of the wiring 46b by electroless plating.

  According to the manufacturing method of the semiconductor device according to the present embodiment, the barrier metal layer is formed of a Ta-based barrier metal material and an alloy of Cu and / or Ag, as in the first embodiment, and this is used. In other words, the electrolytic plating process for depositing Cu is performed, that is, the barrier metal layer also functions as a seed layer for the electrolytic plating process, and the Cu layer is directly deposited on the upper layer of the barrier metal layer by the electrolytic plating process. By doing so, even when the wiring pattern is miniaturized, it is possible to reduce voids due to overhang, which is a risk. Further, when formed in this manner, formation of an oxide film on the surface of the barrier metal layer can be reduced, and furthermore, since the barrier metal layer has an anchor effect, sufficient adhesion between the Cu layer and the barrier metal layer can be secured.

The present invention is not limited to the above description.
For example, as the barrier metal layer, an alloy of a Ta-based barrier metal material such as Ta or TaN and Cu or Ag can be used. In addition, an alloy of another barrier metal material such as Ti or W and Cu or Ag can be used.
The configuration of the interlayer insulating film is not particularly limited.
As the barrier film, a nickel alloy film as well as a cobalt alloy film such as CoWP can be used as necessary.
In addition, various modifications can be made without departing from the scope of the present invention.

The method for manufacturing a semiconductor device of the present invention can be applied to a method for manufacturing a semiconductor device in which trench wiring such as copper is formed by a damascene process or a dual damascene process.
The semiconductor device of the present invention can be applied to a semiconductor device having a trench wiring such as copper.

FIG. 1 is a sectional view showing a schematic configuration of a semiconductor device according to the first embodiment of the present invention. 2A to 2C are cross-sectional views illustrating the manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 3A to 3C are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 4A and FIG. 4B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 5A and FIG. 5B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6A and FIG. 6B are cross-sectional views showing manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 7A and FIG. 7B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 8A to 8C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 9A and FIG. 9B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 10A and FIG. 10B are schematic diagrams for explaining the problems of the conventional method.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... 1st insulating film, 12 ... Contact plug, 13 ... 2nd insulating film, 14 ... 3rd insulating film, 15 ... Resist film, 16 ... Barrier metal layer, 17 ... Metal layer, 17a ... 1st 1 wiring, 18 ... 4th insulating film, 19 ... 5th insulating film, 20 ... 6th insulating film, 21 ... 7th insulating film, 22 ... 8th insulating film, 23 ... 9th insulating film, 24 ... resist film, DESCRIPTION OF SYMBOLS 25 ... Resist film, 26 ... Barrier metal layer, 27 ... Metal layer, 27a ... Contact plug, 27b ... Second wiring, 40 ... Semiconductor substrate, 41 ... First insulating film, 42 ... Contact plug, 43 ... Second insulating film 44 ... 3rd insulating film, 45 ... Barrier metal layer, 46 ... Metal layer, 46a ... Contact plug, 46b ... Wiring, TR1 ... 1st wiring groove, TR2 ... 2nd wiring groove, TR ... Wiring groove, CH ... Contact hole

Claims (9)

A method of manufacturing a semiconductor device for forming wiring on a substrate,
Forming a barrier metal layer made of an alloy of Ta-based barrier metal material and Cu and / or Ag on the substrate;
Forming a metal layer containing Cu on the upper layer of the barrier metal layer by electrolytic plating using the barrier metal layer as an electrode;
And a step of processing the barrier metal layer and the metal layer into a wiring pattern. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the barrier metal layer, the Ta-based barrier metal material and an alloy of Cu and / or Ag are formed by sputtering using a target material. Before the step of forming the barrier metal layer, and further comprising the step of forming a wiring groove in the substrate,
In the step of forming the barrier metal layer, the inner wall surface of the wiring groove is covered and formed,
In the step of forming the metal layer, the wiring groove is embedded and formed,
The method of manufacturing a semiconductor device according to claim 1, wherein in the step of processing the barrier metal layer and the metal layer into a wiring pattern, the barrier metal layer and the metal layer outside the wiring groove are removed. The method for manufacturing a semiconductor device according to claim 3, wherein in the step of removing the barrier metal layer and the metal layer outside the wiring groove, polishing is performed from above the metal layer. Before the step of forming the barrier metal layer, further comprising a step of forming a wiring groove and a contact hole in communication with the substrate;
In the step of forming the barrier metal layer, the inner wall surface of the wiring groove and the contact hole is formed,
In the step of forming the metal layer, the wiring trench and the contact hole are buried and formed,
The method for manufacturing a semiconductor device according to claim 1, wherein in the step of processing the barrier metal layer and the metal layer into a wiring pattern, the barrier metal layer and the metal layer outside the wiring groove and the contact hole are removed. . The method for manufacturing a semiconductor device according to claim 5, wherein in the step of removing the barrier metal layer and the metal layer outside the wiring trench and the contact hole, polishing is performed from above the metal layer. A semiconductor device in which wiring is formed on a substrate,
The wiring is
A barrier metal layer made of an alloy of Ta-based barrier metal material and Cu and / or Ag formed on the substrate;
A metal layer containing Cu formed on the barrier metal layer, and
A semiconductor device in which the barrier metal layer and the metal layer are processed into a wiring pattern. A wiring groove is formed on the substrate,
The barrier metal layer is formed so as to cover the inner wall of the wiring groove,
The semiconductor device according to claim 7, wherein the metal layer is formed by embedding the wiring groove in an upper layer of the barrier metal layer. A wiring groove and a contact hole are formed in the substrate in communication,
The barrier metal layer is formed so as to cover the inner wall of the wiring groove and the contact hole,
The semiconductor device according to claim 7, wherein the metal layer is formed by filling the wiring groove and the contact hole in an upper layer of the barrier metal layer.

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