JP2007012654A - Method of manufacturing laminated ceramic electronic component - Google Patents

Method of manufacturing laminated ceramic electronic component Download PDF

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JP2007012654A
JP2007012654A JP2005187694A JP2005187694A JP2007012654A JP 2007012654 A JP2007012654 A JP 2007012654A JP 2005187694 A JP2005187694 A JP 2005187694A JP 2005187694 A JP2005187694 A JP 2005187694A JP 2007012654 A JP2007012654 A JP 2007012654A
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conductor pattern
conductor
electronic component
ceramic electronic
vertical line
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Yoshinobu Tanaka
芳宜 田中
Junji Hosokawa
淳史 細川
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a laminated ceramic electronic component capable of preventing the occurrence of a short-circuiting fail without increasing the size of the laminated ceramic electronic component. <P>SOLUTION: The method of manufacturing the laminated ceramic electronic component has a conductor pattern formation process. In the conductor pattern formation process: a vertical line 25b is formed in the cut-off region of a second green sheet 32 sandwiched between first and second conductor patterns 21, 22 that should be insulated mutually; a third conductor patten 23, which connects the vertical line 25b to the first conductor pattern 21 mutually, is formed on the surface of the second green sheet 32; and a fourth conductor pattern 24, where the vertical line 25b should be connected to the second conductor pattern 22 mutually, is formed on the surface of a third green sheet 33. In a cut-off process thereafter, third and fourth conductor patterns 23, 24 are cut, or the vertical line 25b is removed completely, thus insulating the first and second patterns 21, 22 each other. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、携帯電話機等の小型の電子機器に装備される各種電子回路を構成するための積層セラミック電子部品の製造方法に関するものである。   The present invention relates to a method for manufacturing a multilayer ceramic electronic component for constituting various electronic circuits equipped in a small electronic device such as a mobile phone.

近年、携帯電話機等の小型の電子機器においては、小型化に対する要求が益々厳しくなってきており、この様な状況において、機器を構成する複数の回路素子を1チップの積層セラミック電子部品に集積化して、該積層セラミック電子部品をメイン基板に実装することが行なわれている。   In recent years, in small electronic devices such as mobile phones, the demand for downsizing has become more and more severe. In such a situation, a plurality of circuit elements constituting the device are integrated into a single-chip multilayer ceramic electronic component. Thus, the multilayer ceramic electronic component is mounted on a main board.

図4に示す従来の積層セラミック電子部品(5)は、3層のセラミック層(51)(52)(53)の積層構造を有している。該積層セラミック電子部品(5)は、図5(a)〜(c)に示す如く、3層のセラミック層(51)(52)(53)となる3枚のグリーンシート(41)(42)(43)にそれぞれ、同一の導体パターンをマトリクス状に配列して形成する導体パターン形成工程と、該導体パターン形成工程を経て得られる3枚のグリーンシート(41)(42)(43)を図5(d)に示す如く積層して、図5(e)に示す積層体(4)を作製した後、該積層体(4)に焼成を施す焼成工程と、焼成後の積層体(4)を所定の切断線に沿って切断する切断工程を経て作製される。
尚、図5(a)〜(c)は、前記導体パターン形成工程を最上層の第1セラミック層(51)となる第1グリーンシート(41)について示したものである。
The conventional multilayer ceramic electronic component (5) shown in FIG. 4 has a multilayer structure of three ceramic layers (51), (52) and (53). The multilayer ceramic electronic component (5) is composed of three green sheets (41), (42) to be three ceramic layers (51), (52), (53) as shown in FIGS. (43) shows a conductor pattern forming step in which the same conductor pattern is arranged in a matrix, and three green sheets (41), (42), and (43) obtained through the conductor pattern forming step. 5 (d), the laminate (4) shown in FIG. 5 (e) is manufactured, and then the laminate (4) is fired, and the fired laminate (4). Is manufactured through a cutting process of cutting along a predetermined cutting line.
5A to 5C show the conductive pattern forming process for the first green sheet (41) which is the uppermost first ceramic layer (51).

図5(a)に示す如く、先ず、第1グリーンシート(41)を用意し、次に、図5(b)に示す如く、第1グリーンシート(41)の所定位置に貫通孔(49)〜(49)を開設した後、図5(c)に示す如く、貫通孔(49)〜(49)に導体材料を充填して垂直線路(58)〜(58)を形成すると共に、第1グリーンシート(41)の表面に導体材料を印刷して、所定の導体パターン(57)〜(57)を形成する。
同様にして、第2及び第3セラミック層(52)(53)となる第2及び第3グリーンシート(42)(43)にも、それぞれ所定の導体パターンと垂直線路を形成する。
As shown in FIG. 5 (a), first, a first green sheet (41) is prepared. Next, as shown in FIG. 5 (b), a through hole (49) is formed at a predetermined position of the first green sheet (41). After opening (49), as shown in FIG. 5 (c), the through holes (49) to (49) are filled with a conductor material to form vertical lines (58) to (58), and the first A conductor material is printed on the surface of the green sheet (41) to form predetermined conductor patterns (57) to (57).
Similarly, predetermined conductor patterns and vertical lines are formed on the second and third green sheets (42) and (43), which are the second and third ceramic layers (52) and (53), respectively.

次の焼成工程では、前記導体パターン形成工程を経て得られた第1乃至第3グリーンシート(41)(42)(43)を図5(d)に示す如く順に積み重ねて、図5(e)に示す積層体(4)を作製した後、該積層体(4)に熱圧着及び焼成を施して一体化する。
最後に切断工程にて、前記焼成工程を経て得られた積層体(4)を図5(e)中に破線で示す所定の切断線に沿って切断することにより、図4に示す積層セラミック電子部品(5)が作製されることになる。
In the next firing step, the first to third green sheets (41), (42), and (43) obtained through the conductor pattern forming step are sequentially stacked as shown in FIG. After the laminate (4) shown in FIG. 4 is produced, the laminate (4) is integrated by thermocompression bonding and firing.
Finally, in the cutting step, the multilayer body (4) obtained through the firing step is cut along a predetermined cutting line indicated by a broken line in FIG. A part (5) will be produced.

しかしながら、図5(e)に示す焼成工程において、第2グリーンシート(42)の表面に形成された第1の導体パターン(55)と第3グリーンシート(43)の表面に形成された第2の導体パターン(56)とが、図示の如く微細な短絡線路(45)により接続されて、短絡不良が発生することがあった。   However, in the firing step shown in FIG. 5 (e), the first conductor pattern (55) formed on the surface of the second green sheet (42) and the second conductor formed on the surface of the third green sheet (43). The conductor pattern (56) is connected by a fine short-circuit line (45) as shown in the figure, and a short-circuit failure may occur.

発明者が上述の短絡不良が発生する条件を分析したところ、図4に示す如く、両導体パターン(55)(56)が互いに電気的に絶縁されており、且つ、両導体パターン(55)(56)が上下方向に重なって、互いにオーバーラップする領域を有している場合に短絡不良が発生することを見出し、短絡不良の原因を焼成工程において発生する両導体パターン(55)(56)間の電位差によるものと推測した。
即ち、図5(e)に示す焼成工程において、温度上昇に伴う焦電効果及び圧着による圧電効果によって、誘電体である第2グリーンシート(42)に分極が生じ、該分極に伴って、第2グリーンシート(42)を挟んで互いに対向する第1及び第2の導体パターン(55)(56)が帯電して、両導体パターン(55)(56)間に電位差が生じることになる。該電位差に起因して微細な短絡線路(45)が形成され、短絡不良が発生すると推測されるのである。
The inventor analyzed the conditions for the occurrence of the short-circuit failure described above. As shown in FIG. 4, the two conductor patterns (55) and (56) are electrically insulated from each other, and the two conductor patterns (55) ( 56) is overlapped in the vertical direction and has a region where they overlap each other, it is found that a short-circuit failure occurs, and the cause of the short-circuit failure is between the two conductor patterns (55) (56) generated in the firing process. It was presumed to be due to the potential difference.
That is, in the firing step shown in FIG. 5 (e), polarization occurs in the second green sheet (42), which is a dielectric, due to the pyroelectric effect accompanying the temperature rise and the piezoelectric effect due to the pressure bonding. The first and second conductor patterns (55) and (56) facing each other across the two green sheets (42) are charged, and a potential difference is generated between the two conductor patterns (55) and (56). It is estimated that a fine short circuit line (45) is formed due to the potential difference and a short circuit failure occurs.

ところで、高温高湿条件下において、微小な間隔で形成された配線間を導体材料が移動して、該配線間が短絡してしまうマイグレーション現象が知られており、マイグレーション現象の発生を防止すべく種々の導体材料が提案されている(特許文献1参照)。
特開平6−20517号公報 [H01B 1/16]
By the way, a migration phenomenon is known in which a conductor material moves between wirings formed at minute intervals under high temperature and high humidity conditions, and the wirings are short-circuited. Various conductor materials have been proposed (see Patent Document 1).
JP-A-6-20517 [H01B 1/16]

しかしながら、マイグレーション現象が発生し難い導体材料を用いたとしても、上述の短絡不良の発生を充分に防止することが出来なかった。
そこで、従来の積層セラミック電子部品の製造においては、セラミック層を挟んで対向する2つの導体パターンがセラミック層の積層方向に重ならない様に配置し、或いはセラミック層の厚さを一定以上の厚さに形成する等の設計上の対策を施すことにより、短絡不良の発生を防止していた。
しかしながら、この様な設計上の対策のために集積度が低下して、積層セラミック電子部品が大型化してしまう問題があった。
そこで、本発明の目的は、積層セラミック電子部品の大型化を招くことなく、短絡不良の発生を防止することが出来る積層セラミック電子部品の製造方法を提供することである。
However, even when a conductive material that hardly causes the migration phenomenon is used, the occurrence of the short-circuit failure described above cannot be sufficiently prevented.
Therefore, in the manufacture of conventional multilayer ceramic electronic components, two conductor patterns facing each other across the ceramic layer are arranged so as not to overlap in the stacking direction of the ceramic layer, or the thickness of the ceramic layer is a certain thickness or more. The occurrence of a short circuit failure was prevented by taking measures on the design such as forming on the surface.
However, due to such design measures, there is a problem that the degree of integration decreases and the multilayer ceramic electronic component becomes large.
Accordingly, an object of the present invention is to provide a method for manufacturing a multilayer ceramic electronic component capable of preventing the occurrence of a short circuit failure without increasing the size of the multilayer ceramic electronic component.

本発明の対象とする積層セラミック電子部品は、複数のセラミック層の積層構造を有し、互いに接触する1或いは複数対のセラミック層の内、少なくとも一対のセラミック層には、第1の導体パターンが一方のセラミック層の表面に形成されると共に、他方のセラミック層の表面には、該第1の導体パターンと電気的に絶縁された第2の導体パターンが形成されている。
本発明に係る積層セラミック電子部品の製造方法は、前記複数のセラミック層となる複数枚のグリーンシートの表面に、同一の導体パターンをマトリクス状に配列して形成する導体パターン形成工程と、該導体パターン形成工程を経て得られた複数枚のグリーンシートを積層して積層体を作製した後、該積層体に焼成を施す焼成工程と、該焼成工程を経て得られた積層体を所定の切断線に沿って導体パターン毎に切断する切断工程とを有している。
The multilayer ceramic electronic component of the present invention has a multilayer structure of a plurality of ceramic layers, and at least one pair of ceramic layers in contact with each other has at least one pair of ceramic layers having a first conductor pattern. A second conductor pattern formed on the surface of one ceramic layer and electrically insulated from the first conductor pattern is formed on the surface of the other ceramic layer.
The method for manufacturing a multilayer ceramic electronic component according to the present invention includes a conductor pattern forming step in which the same conductor pattern is arranged in a matrix on the surface of a plurality of green sheets serving as the plurality of ceramic layers, and the conductor After a plurality of green sheets obtained through the pattern forming step are laminated to produce a laminate, a firing step for firing the laminate, and a laminate obtained through the firing step with a predetermined cutting line And a cutting step of cutting each conductor pattern along the line.

前記導体パターン形成工程では、前記一方のセラミック層となる第1グリーンシートの表面に、前記第1の導体パターンを含む同一の導体パターンを、少なくとも前記1方向に複数並べて形成し、互いに隣接する2つの同一の導体パターン間の各切断領域内に垂直線路を形成すると共に、該垂直線路と前記第1の導体パターンとを電気的に接続する第3の導体パターンを形成する。
又、前記他方のセラミック層となる第2グリーンシートの表面には、前記第2の導体パターンを含む同一の導体パターンを少なくとも1方向に複数並べて形成すると共に、前記積層体の状態において、前記垂直線路と互いに重なることとなる位置まで前記第2の導体パターンから伸びる第4の導体パターンを形成する。
そして、前記切断工程では、前記積層体を前記所定の切断線に沿って切断することにより、前記第3導体パターン、第4の導体パターン及び垂直線路からなる接続線路の少なくとも一部を除去して、前記第1の導体パターンと第2の導体パターンとを互いに電気的に絶縁する。
In the conductor pattern forming step, a plurality of the same conductor patterns including the first conductor pattern are formed side by side in the one direction on the surface of the first green sheet serving as the one ceramic layer, and adjacent to each other. A vertical line is formed in each cut region between two identical conductor patterns, and a third conductor pattern that electrically connects the vertical line and the first conductor pattern is formed.
In addition, a plurality of identical conductor patterns including the second conductor pattern are arranged in at least one direction on the surface of the second green sheet serving as the other ceramic layer, and the vertical conductor in the state of the multilayer body is formed. A fourth conductor pattern extending from the second conductor pattern to a position where it overlaps the line is formed.
In the cutting step, the laminate is cut along the predetermined cutting line to remove at least a part of the connection line including the third conductor pattern, the fourth conductor pattern, and the vertical line. The first conductor pattern and the second conductor pattern are electrically insulated from each other.

具体的には、前記垂直線路は、前記導体パターン形成工程にて、前記第1グリーンシートの切断領域に垂直の貫通孔を開設した後、該貫通孔に導体材料を充填して形成される。   Specifically, the vertical line is formed by opening a vertical through hole in the cut region of the first green sheet and filling the through hole with a conductive material in the conductor pattern forming step.

上記本発明の積層セラミック電子部品の製造方法によれば、焼成工程にて作製される積層体の状態において、導体パターン形成工程にて前記第1グリーンシートの切断領域に形成された垂直線路と第2グリーンシートの表面に形成された第4の導体パターンとが互いに接触し、これによって、前記第1の導体パターンと第2の導電パターンとが、前記垂直線路、第3の導体パターン及び第4の導体パターンからなる接続線路を経て互いに電気的に接続されることになる。
この結果、積層体の焼成中に、仮に前記第1の導体パターンと第2の導体パターンとに挟まれた第1グリーンシートに分極が生じ、前記第1の導体パターンと第2の導体パターンとが一時的に異なる電位に帯電したとしても、前記第1の導体パターンと第2の導体パターンとの間で電荷が移動して、前記第1の導体パターンと第2の導体パターンとは同電位に保たれる。従って、前記第1の導体パターンと第2の導体パターンの間に電位差が生じることはない。これによって、短絡不良の発生を防止することが出来る。
According to the method for manufacturing a multilayer ceramic electronic component of the present invention, the vertical line formed in the cut region of the first green sheet in the conductor pattern forming step and the The fourth conductor pattern formed on the surface of the two green sheets is in contact with each other, whereby the first conductor pattern and the second conductor pattern are connected to the vertical line, the third conductor pattern, and the fourth conductor pattern. They are electrically connected to each other through a connection line made of a conductive pattern.
As a result, polarization occurs in the first green sheet temporarily sandwiched between the first conductor pattern and the second conductor pattern during firing of the laminate, and the first conductor pattern and the second conductor pattern Are temporarily charged to different potentials, the charge moves between the first conductor pattern and the second conductor pattern, and the first conductor pattern and the second conductor pattern have the same potential. To be kept. Therefore, there is no potential difference between the first conductor pattern and the second conductor pattern. Thereby, the occurrence of short circuit failure can be prevented.

更に、次の切断工程にて前記積層体を所定の切断線に沿って切断することにより、前記第3の導体パターン、第4の導体パターン及び前記垂直線路の一部が除去される。これにより、前記第1の導体パターンと第2の導体パターンとが互いに電気的に絶縁されることとなり、この結果、所望の積層セラミック電子部品が完成することになる。   Furthermore, the third conductor pattern, the fourth conductor pattern, and a part of the vertical line are removed by cutting the laminated body along a predetermined cutting line in the next cutting step. As a result, the first conductor pattern and the second conductor pattern are electrically insulated from each other. As a result, a desired multilayer ceramic electronic component is completed.

上記本発明の積層セラミック電子部品の製造方法によれば、従来のような設計上の対策を施すことなく短絡不良の発生を防止することが出来る。又、従来は短絡不良が発生していた領域、即ち前記第1の導体パターンと少なくとも一部がオーバーラップすることとなる領域に、前記第2の導体パターンを形成することが可能となるので、これによって、積層セラミック電子部品の集積度が向上し、積層セラミック電子部品の小型化を図ることが出来る。   According to the method for manufacturing a multilayer ceramic electronic component of the present invention, it is possible to prevent the occurrence of a short circuit failure without taking a conventional design measure. In addition, since it is possible to form the second conductor pattern in a region where a short-circuit failure has conventionally occurred, that is, a region where at least part of the first conductor pattern overlaps, As a result, the degree of integration of the multilayer ceramic electronic component is improved, and the multilayer ceramic electronic component can be miniaturized.

本発明の積層セラミック電子部品の製造方法によれば、積層セラミック電子部品の大型化を招くことなく、短絡不良の発生を防止することが出来る。   According to the method for manufacturing a multilayer ceramic electronic component of the present invention, it is possible to prevent occurrence of a short circuit failure without increasing the size of the multilayer ceramic electronic component.

以下、本発明の実施の形態につき、図面に沿って具体的に説明する。
図1に示す如く、本発明に係る積層セラミック電子部品(1)は、3層のセラミック層(11)(12)(13)の積層構造を有している。
各セラミック(11)(12)(13)層には、その表面に所定の導体パターン(15)〜(15)が形成されると共に、各層間で複数の導体パターン(15)〜(15)を互いに電気的に接続するための垂直線路(16)〜(16)が形成されている。
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
As shown in FIG. 1, the multilayer ceramic electronic component (1) according to the present invention has a multilayer structure of three ceramic layers (11), (12) and (13).
Each ceramic (11) (12) (13) layer has a predetermined conductor pattern (15) to (15) formed on its surface, and a plurality of conductor patterns (15) to (15) between each layer. Vertical lines (16) to (16) for electrically connecting to each other are formed.

最上層の第1セラミック層(11)と最下層の第3セラミック層(13)の間に挟まれた第2セラミック層(12)の表面には、第1の導体パターン(21)が形成されており、該第1の導体パターン(21)は、垂直線路(16)を介して第1セラミック層(11)の表面に形成された導体パターン(15)に電気的に接続されている。
第3セラミック層(13)の表面には、前記第1導体パターン(21)とは電気的に絶縁された第2の導体パターン(22)が、前記第1導体パターン(21)と上下方向に重なって互いにオーバーラップする領域に形成されている。第2の導体パターン(22)は、垂直線路(16)を介して第3セラミック層(13)の裏面に形成された導体パターン(15)に電気的に接続されている。
尚、各セラミック層(11)(12)(13)は、例えば5mm角の平板形状を呈し、各セラミック層(11)(12)(13)の厚さは、例えば50μmに形成されている。又、各導体パターンの厚さは、例えば10〜20μmに形成されている。
A first conductor pattern (21) is formed on the surface of the second ceramic layer (12) sandwiched between the uppermost first ceramic layer (11) and the lowermost third ceramic layer (13). The first conductor pattern (21) is electrically connected to the conductor pattern (15) formed on the surface of the first ceramic layer (11) via the vertical line (16).
On the surface of the third ceramic layer (13), a second conductor pattern (22) that is electrically insulated from the first conductor pattern (21) extends vertically with respect to the first conductor pattern (21). Overlapping and overlapping regions are formed. The second conductor pattern (22) is electrically connected to the conductor pattern (15) formed on the back surface of the third ceramic layer (13) via the vertical line (16).
The ceramic layers (11), (12), and (13) have a flat plate shape of 5 mm square, for example, and the thickness of each ceramic layer (11), (12), and (13) is, for example, 50 μm. Moreover, the thickness of each conductor pattern is formed to 10-20 micrometers, for example.

該積層セラミック電子部品(1)は、図2(a)〜(c)に示す如く、3層のセラミック層(11)(12)(13)となる3枚のグリーンシート(31)(32)(33)にそれぞれ、同一の導体パターンをマトリクス状に配列して形成する導体パターン形成工程と、該導体パターン形成工程を経て得られる3枚のグリーンシート(31)(32)(33)を図2(d)に示す如く積層して、図2(e)に示す積層体(3)を作製した後、該積層体(3)に焼成を施す焼成工程と、焼成後の積層体(3)を所定の切断線に沿って切断する切断工程とを経て作製される。   The multilayer ceramic electronic component (1) is composed of three green sheets (31), (32) to be three ceramic layers (11), (12), (13) as shown in FIGS. (33) shows a conductor pattern forming step in which the same conductor pattern is arranged in a matrix, and three green sheets (31), (32) and (33) obtained through the conductor pattern forming step. 2 (d), the laminate (3) shown in FIG. 2 (e) is manufactured, and then the laminate (3) is fired, and the fired laminate (3). Is cut through a predetermined cutting line.

図3に示す如く、各グリーンシート(31)(32)(33)には、長手方向に沿って配列された3つの矩形状の導体パターン形成領域(35)(35)(35)内に、それぞれ同一の導体パターンが形成されており、隣接する2つの導体パターン形成領域(35)(35)の間には、前記切断工程にて切断されるべき切断領域(36)が設けられている。   As shown in FIG. 3, each green sheet (31) (32) (33) has three rectangular conductor pattern formation regions (35) (35) (35) arranged along the longitudinal direction. The same conductor pattern is formed, and a cutting region (36) to be cut in the cutting step is provided between two adjacent conductor pattern forming regions (35) and (35).

図2(a)〜(c)は、前記導体パターン形成工程を、第2セラミック層(12)となる第2グリーンシート(32)について示したものである。
図2(a)に示す如く、先ず、第2グリーンシート(32)を用意し、次に、図2(b)に示す如く、第2グリーンシート(32)の3つの導体パターン形成領域(35)内の所定位置にそれぞれ貫通孔(39a)を開設すると共に、2つの切断領域(36)内の所定位置にそれぞれ貫通孔(39b)を開設する。
その後、図2(c)に示す如く、貫通孔(39a)(39b)に導体材料を充填して垂直線路(16)(25b)を形成すると共に、第2グリーンシート(32)の表面に導体材料を印刷して、各導体パターン形成領域(35)内に第1導体パターン(21)を含む所定の導体パターンを形成すると共に、第1導体パターン(21)と前記切断領域(36)内に形成した垂直線路(25b)とを互いに電気的に接続する第3の導体パターン(23)を形成する。
2 (a) to 2 (c) show the conductor pattern forming step for the second green sheet (32) to be the second ceramic layer (12).
As shown in FIG. 2 (a), first, a second green sheet (32) is prepared, and then, as shown in FIG. 2 (b), three conductor pattern formation regions (35) of the second green sheet (32) are prepared. ) And through holes (39a) are respectively opened at predetermined positions within the two cutting regions (36).
Thereafter, as shown in FIG. 2 (c), the through holes (39a) and (39b) are filled with a conductor material to form vertical lines (16) and (25b), and the conductors are formed on the surface of the second green sheet (32). The material is printed to form a predetermined conductor pattern including the first conductor pattern (21) in each conductor pattern formation region (35), and in the first conductor pattern (21) and the cutting region (36). A third conductor pattern (23) is formed to electrically connect the formed vertical line (25b) to each other.

同様にして、図2(d)に示す如く、第3セラミック層(13)となる第3グリーンシート(33)には、各切断領域(36)内の所定位置に垂直線路(25c)を形成し、各導体パターン形成領域(35)内に第2導体パターン(22)を含む所定の導体パターンを形成すると共に、前記垂直線路(25c)と第2導体パターン(22)とを互いに電気的に接続する第4の導体パターン(24)を形成する。
又、第1セラミック層(11)となる第1グリーンシート(31)には、各切断領域(36)内の所定位置に垂直線路(25a)を形成し、各導体パターン形成領域(35)内に所定の導体パターン(15)〜(15)を形成すると共に、前記垂直線路(25a)と隣接する導体パターン(15)と該垂直線路(25a)とを互いに電気的に接続する第5の導体パターン(26)を形成する。
この様にして、所定の導体パターンと垂直線路を形成した第1乃至第3グリーンシート(31)(32)(33)が作製されることになる。
尚、第3乃至第5の導体パターン(24)〜(26)の線幅は80μm、各垂直線路(25a)〜(25c)の直径は130μmである。
Similarly, as shown in FIG. 2 (d), a vertical line (25c) is formed at a predetermined position in each cutting region (36) on the third green sheet (33) to be the third ceramic layer (13). In addition, a predetermined conductor pattern including the second conductor pattern (22) is formed in each conductor pattern forming region (35), and the vertical line (25c) and the second conductor pattern (22) are electrically connected to each other. A fourth conductor pattern (24) to be connected is formed.
Further, the first green sheet (31) to be the first ceramic layer (11) is formed with a vertical line (25a) at a predetermined position in each cutting region (36), and in each conductor pattern forming region (35). Are formed with predetermined conductor patterns (15) to (15), and the fifth conductor for electrically connecting the vertical line (25a) to the adjacent conductor pattern (15) and the vertical line (25a). A pattern (26) is formed.
In this way, the first to third green sheets (31), (32) and (33) in which the predetermined conductor pattern and the vertical line are formed are produced.
The line widths of the third to fifth conductor patterns (24) to (26) are 80 μm, and the diameters of the vertical lines (25a) to (25c) are 130 μm.

次の焼成工程にて、前記導体パターン形成工程を経て得られた第1乃至第3グリーンシート(31)(32)(33)を、図2(d)に示す如く順に積み重ねて、図2(e)に示す積層体(3)を作製する。このとき、各グリーンシート(31)(32)(33)の切断領域(36)内にそれぞれ形成された3つの垂直線路(25a)(25b)(25c)の端面どうしが互いに接触して貫通垂直線路(25)が形成され、第2グリーンシート(32)を挟んで互いに対向する第1導体パターン(21)と第2導体パターン(22)とは、貫通垂直線路(25)、第3の導体パターン(23)及び第4の導体パターン(24)を介して互いに電気的に接続されることになる。   In the next firing step, the first to third green sheets (31), (32), (33) obtained through the conductor pattern forming step are sequentially stacked as shown in FIG. A laminate (3) shown in e) is produced. At this time, the end surfaces of the three vertical lines (25a), (25b), and (25c) formed in the cut regions (36) of the green sheets (31), (32), and (33) are in contact with each other and penetrated vertically. The first conductor pattern (21) and the second conductor pattern (22), which are formed with the line (25) and face each other with the second green sheet (32) interposed therebetween, are a through vertical line (25) and a third conductor. They are electrically connected to each other through the pattern (23) and the fourth conductor pattern (24).

次に、積層体(3)に熱圧着及び焼成を施して一体化する。焼成過程において、仮に第2グリーンシート(32)に分極が生じ、第2グリーンシート(32)を挟んで互いに対向する第1の導体パターン(21)と第2の導体パターン(22)とが一時的に異なる電位に帯電したとしても、第1の導体パターン(21)と第2の導体パターン(22)とは電気的に接続されているので、第1の導体パターン(21)と第2の導体パターン(22)との間で電荷が移動して、両導体パターン(21)(22)は同電位に保たれる。従って、第1の導体パターン(21)と第2導体パターン(22)の間に電位差が生じることはない。これによって、短絡不良の発生を防止することが出来る。   Next, the laminate (3) is integrated by thermocompression bonding and baking. In the firing process, the second green sheet (32) is polarized, and the first conductor pattern (21) and the second conductor pattern (22) facing each other across the second green sheet (32) temporarily. The first conductor pattern (21) and the second conductor pattern (22) are electrically connected to each other even if they are charged to different potentials. The electric charge moves between the conductor patterns (22), and both the conductor patterns (21) and (22) are kept at the same potential. Therefore, there is no potential difference between the first conductor pattern (21) and the second conductor pattern (22). Thereby, the occurrence of short circuit failure can be prevented.

最後に切断工程では、厚さ500μmのダイシングブレードを用いて、図2(e)に破線で示す所定の切断線に沿って焼成後の積層体(3)を切断する。これにより直径130μmの貫通垂直線路(25)は、完全に除去されることになり、この結果、第1導体パターン(21)と第2導体パターン(22)とが互いに電気的に絶縁されて、目的とする積層セラミック電子部品(1)が完成する。
尚、図1に示す如く、積層セラミック電子部品(1)には、第3乃至第5の導体パターン(23)(24)(26)の一部が残存することになるが、該第3乃至第5の導体パターン(23)(24)(26)は、線幅80μmの極めて細い導体パターンであるため、積層セラミック電子部品(1)の性能に悪影響を及ぼすことはない。
Finally, in the cutting step, the fired laminate (3) is cut along a predetermined cutting line indicated by a broken line in FIG. 2 (e) using a dicing blade having a thickness of 500 μm. As a result, the through vertical line (25) having a diameter of 130 μm is completely removed. As a result, the first conductor pattern (21) and the second conductor pattern (22) are electrically insulated from each other, The target multilayer ceramic electronic component (1) is completed.
As shown in FIG. 1, a part of the third to fifth conductor patterns (23), (24), and (26) remain in the multilayer ceramic electronic component (1). Since the fifth conductor patterns (23), (24), and (26) are extremely thin conductor patterns having a line width of 80 μm, the performance of the multilayer ceramic electronic component (1) is not adversely affected.

本発明の積層セラミック電子部品(1)の製造方法によれば、従来のような設計上の対策を施すことなく短絡不良の発生を防止することが出来る。又、従来は短絡不良が発生していた領域、即ち、第1導体パターン(21)とオーバーラップすることとなる領域に、第2導体パターン(22)を形成することが可能となるので、積層セラミック電子部品の集積度が向上し、これによって積層セラミック電子部品の小型化を図ることが出来る。   According to the method of manufacturing the multilayer ceramic electronic component (1) of the present invention, it is possible to prevent the occurrence of a short circuit failure without taking a conventional design measure. In addition, since the second conductor pattern (22) can be formed in a region where a short-circuit failure has conventionally occurred, that is, a region where the first conductor pattern (21) overlaps, The degree of integration of the ceramic electronic components is improved, and this makes it possible to reduce the size of the multilayer ceramic electronic component.

尚、本発明の各部構成は上記実施の形態に限らず、特許請求の範囲に記載の技術的範囲内で種々の変形が可能である。例えば、本実施例において積層セラミック電子部品(1)を構成するセラミック層の数を3層としたが、2層以上であれば何層であっても可い。
又、本実施例において、積層セラミック電子部品(1)の複数のセラミック層を構成する全てのグリーンシートを貫通する貫通垂直線路(25)を前記切断領域(36)内に形成したが、短絡不良が発生しやすい前記第1の導体パターン(21)と第2の導体パターン(22)の間に挟まれた第2グリーンシート(32)の切断領域(36)にのみ垂直線路(25b)を形成し、第1及び第3グリーンシート(31)(33)の切断領域に形成した垂直線路(25a)(25c)及び第5の導体パターン(26)を省略することも可能である。
更に、各グリーンシートの表面に所定の導体パターンを形成する方法として導体材料を印刷する方法を用いたが、これに限らず、例えばスパッタ法、蒸着法、メッキ法等の種々の方法を採用することも可能である。
In addition, each part structure of this invention is not restricted to the said embodiment, A various deformation | transformation is possible within the technical scope as described in a claim. For example, in this embodiment, the number of ceramic layers constituting the multilayer ceramic electronic component (1) is three, but any number of layers may be used as long as it is two or more.
In this embodiment, the through vertical line (25) penetrating all the green sheets constituting the plurality of ceramic layers of the multilayer ceramic electronic component (1) is formed in the cutting region (36). A vertical line (25b) is formed only in the cut region (36) of the second green sheet (32) sandwiched between the first conductor pattern (21) and the second conductor pattern (22), which is likely to generate In addition, the vertical lines (25a) and (25c) and the fifth conductor pattern (26) formed in the cut regions of the first and third green sheets (31) and (33) can be omitted.
Furthermore, although the method of printing a conductor material was used as a method of forming a predetermined conductor pattern on the surface of each green sheet, the present invention is not limited to this, and various methods such as a sputtering method, a vapor deposition method, and a plating method are employed. It is also possible.

本発明に係る積層セラミック電子部品を示す断面図である。It is sectional drawing which shows the laminated ceramic electronic component which concerns on this invention. 該積層セラミック電子部品の製造工程を示す一連の断面図である。It is a series of sectional views showing the manufacturing process of the multilayer ceramic electronic component. 該積層セラミック電子部品の製造工程にて作製される積層体の分解斜視図である。It is a disassembled perspective view of the laminated body produced at the manufacturing process of this laminated ceramic electronic component. 従来の積層セラミック電子部品を示す断面図である。It is sectional drawing which shows the conventional multilayer ceramic electronic component. 従来の積層セラミック電子部品の製造工程を示す一連の断面図である。It is a series of sectional views showing a manufacturing process of a conventional multilayer ceramic electronic component.

符号の説明Explanation of symbols

(1) 積層セラミック電子部品
(11) 第1セラミック層
(12) 第2セラミック層
(13) 第3セラミック層
(15) 導体パターン
(16) 垂直線路
(21) 第1の導体パターン
(22) 第2の導体パターン
(23) 第3の導体パターン
(24) 第4の導体パターン
(25a)、(25b)、(25c) 垂直線路
(25) 貫通垂直線路
(3) 積層体
(31) 第1グリーンシート
(32) 第2グリーンシート
(33) 第3グリーンシート
(35) 導体パターン形成領域
(36) 切断領域
(1) Multilayer ceramic electronic parts
(11) First ceramic layer
(12) Second ceramic layer
(13) Third ceramic layer
(15) Conductor pattern
(16) Vertical track
(21) First conductor pattern
(22) Second conductor pattern
(23) Third conductor pattern
(24) Fourth conductor pattern
(25a), (25b), (25c) Vertical line
(25) Through vertical line
(3) Laminate
(31) First green sheet
(32) Second green sheet
(33) Third green sheet
(35) Conductor pattern formation area
(36) Cutting area

Claims (3)

複数のセラミック層の積層構造を有し、互いに接触する少なくとも一対のセラミック層には、第1の導体パターンが一方のセラミック層の表面に形成されると共に、他方のセラミック層の表面には、該第1の導体パターンと電気的に絶縁された第2の導体パターンが形成されている積層セラミック電子部品の製造方法において、
前記複数のセラミック層となる複数枚のグリーンシートの表面に、同一の導体パターンを少なくとも1方向に複数並べて形成する導体パターン形成工程と、該導体パターン形成工程を経て得られた複数枚のグリーンシートを積層して積層体を作製した後、該積層体に焼成を施す焼成工程と、該焼成工程を経て得られた積層体を所定の切断線に沿って導体パターン毎に切断する切断工程とを有し、
前記導体パターン形成工程では、前記一方のセラミック層となる第1グリーンシートの表面に、前記第1の導体パターンを含む同一の導体パターンを、少なくとも前記1方向に複数並べて形成し、互いに隣接する2つの同一の導体パターン間の各切断領域内に垂直線路を形成すると共に、該垂直線路と前記第1の導体パターンとを電気的に接続する第3の導体パターンを形成し、前記他方のセラミック層となる第2グリーンシートの表面には、前記第2の導体パターンを含む同一の導体パターンを少なくとも前記1方向に複数並べて形成すると共に、前記積層体の状態において、前記垂直線路と互いに重なることとなる位置まで前記第2の導体パターンから伸びる第4の導体パターンを形成し、
前記切断工程では、前記積層体を前記所定の切断線に沿って切断することにより、前記第3の導体パターン、第4の導体パターン及び垂直線路からなる接続線路の少なくとも一部を除去して、前記第1の導体パターンと第2の導体パターンとを互いに電気的に絶縁することを特徴とする積層セラミック電子部品の製造方法。
A first conductor pattern is formed on the surface of one ceramic layer in at least a pair of ceramic layers that have a laminated structure of a plurality of ceramic layers, and the surface of the other ceramic layer includes the first conductor pattern. In the manufacturing method of the multilayer ceramic electronic component in which the second conductor pattern electrically insulated from the first conductor pattern is formed,
A conductor pattern forming step of forming a plurality of identical conductor patterns in at least one direction on the surface of a plurality of green sheets to be a plurality of ceramic layers, and a plurality of green sheets obtained through the conductor pattern forming step After the laminate is manufactured to produce a laminate, a firing step of firing the laminate, and a cutting step of cutting the laminate obtained through the firing step for each conductor pattern along a predetermined cutting line Have
In the conductor pattern forming step, a plurality of the same conductor patterns including the first conductor pattern are formed side by side in the one direction on the surface of the first green sheet serving as the one ceramic layer, and adjacent to each other. Forming a vertical line in each cut region between two identical conductor patterns, and forming a third conductor pattern for electrically connecting the vertical line and the first conductor pattern, the other ceramic layer A plurality of the same conductor patterns including the second conductor pattern are formed side by side in the one direction on the surface of the second green sheet to be overlapped with the vertical line in the state of the laminate. Forming a fourth conductor pattern extending from the second conductor pattern to a position,
In the cutting step, by cutting the laminated body along the predetermined cutting line, to remove at least a part of the connection line consisting of the third conductor pattern, the fourth conductor pattern and the vertical line, A method for manufacturing a multilayer ceramic electronic component, wherein the first conductor pattern and the second conductor pattern are electrically insulated from each other.
前記導体パターン形成工程では、前記第2グリーンシートの表面であって、前記第1の導体パターンと少なくとも一部がオーバーラップすることとなる領域に、前記第2の導体パターンを形成する請求項1に記載の積層セラミック電子部品の製造方法。   The said conductor pattern formation process WHEREIN: The said 2nd conductor pattern is formed in the area | region which is a surface of the said 2nd green sheet and at least one part overlaps with the said 1st conductor pattern. The manufacturing method of the multilayer ceramic electronic component of description. 前記垂直線路は、前記導体パターン形成工程にて、前記第1グリーンシートの前記切断領域内に垂直の貫通孔を開設した後、該貫通孔に導体材料を充填して形成される請求項1又は請求項2に記載の積層セラミック電子部品の製造方法。   The vertical line is formed by opening a vertical through hole in the cut region of the first green sheet and then filling the through hole with a conductive material in the conductor pattern forming step. The manufacturing method of the multilayer ceramic electronic component of Claim 2.
JP2005187694A 2005-06-28 2005-06-28 Method of manufacturing laminated ceramic electronic component Pending JP2007012654A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012124421A1 (en) * 2011-03-14 2012-09-20 株式会社村田製作所 Flexible multilayer substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012124421A1 (en) * 2011-03-14 2012-09-20 株式会社村田製作所 Flexible multilayer substrate
JP5715237B2 (en) * 2011-03-14 2015-05-07 株式会社村田製作所 Flexible multilayer board

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