JP2007005501A - Capacitor element and non-reciprocal circuit element - Google Patents

Capacitor element and non-reciprocal circuit element Download PDF

Info

Publication number
JP2007005501A
JP2007005501A JP2005182685A JP2005182685A JP2007005501A JP 2007005501 A JP2007005501 A JP 2007005501A JP 2005182685 A JP2005182685 A JP 2005182685A JP 2005182685 A JP2005182685 A JP 2005182685A JP 2007005501 A JP2007005501 A JP 2007005501A
Authority
JP
Japan
Prior art keywords
electrode
capacitor
electrodes
layer
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005182685A
Other languages
Japanese (ja)
Inventor
Wataru Ohashi
渉 大橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP2005182685A priority Critical patent/JP2007005501A/en
Publication of JP2007005501A publication Critical patent/JP2007005501A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Non-Reversible Transmitting Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To decrease a capacity tolerance (variations) caused by misregistration of inter-electrodes formed on a dielectric board. <P>SOLUTION: A capacitor element comprises a first electrode and a second electrode, and the first electrode contains two or more capacity electrodes which are disposed at a distance in the thickness direction of a lamination board and are electrically connected to each other. The second electrode is disposed between adjoining two capacity electrodes in the thickness direction of the lamination board among the two or more capacity electrodes to form an electrostatic capacity between the first electrode and the second electrode. The second electrode contains at least the two capacity electrodes, which are disposed at a distance in the thickness direction of the lamination board and are electrically connected to each other. Preferably, the distance between the two capacity electrodes, included in the second electrode, is greater than the distance between the capacity electrode of the first electrode and the capacity electrode of the second electrode which form the electrostatic capacity so as to face each other. This is suitable for use as a matching capacitor of a non-reciprocal circuit element (isolator). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、コンデンサ素子および非可逆回路素子に係り、特にアイソレータ等の非可逆回路素子を構成するため積層基板内に形成するコンデンサの構造に関する。   The present invention relates to a capacitor element and a non-reciprocal circuit element, and more particularly to a structure of a capacitor formed in a multilayer substrate to constitute a non-reciprocal circuit element such as an isolator.

受動回路素子の一つとしてコンデンサは電子回路を構成し、各種の電子部品や回路モジュールに組み込まれることがある。例えば携帯電話機のような移動体通信機器のフロントエンド部には、アンテナからの反射電力を遮断するため、非可逆回路素子(アイソレータ)が設けられる。このアイソレータは、軟磁性体とこの軟磁性体に所定の角度を持って互いに交差するよう配置される3本の中心導体とからなる磁気回転子と、磁気回転子に直流磁界を印加する磁石と、終端抵抗と、複数の整合用コンデンサとを樹脂ケース内に収容してなる(下記特許文献1および2参照)。整合用コンデンサは、中心導体と各端子(入力端子、出力端子または終端抵抗を接続する終端端子)との間に一端が接続され、他端がグランドに接続される。   As one of the passive circuit elements, a capacitor constitutes an electronic circuit and may be incorporated into various electronic components and circuit modules. For example, a nonreciprocal circuit element (isolator) is provided at a front end portion of a mobile communication device such as a mobile phone in order to cut off reflected power from an antenna. This isolator includes a magnetic rotor composed of a soft magnetic body and three central conductors arranged so as to intersect with each other at a predetermined angle, a magnet for applying a DC magnetic field to the magnetic rotor, A terminal resistor and a plurality of matching capacitors are accommodated in a resin case (see Patent Documents 1 and 2 below). The matching capacitor has one end connected between the central conductor and each terminal (an input terminal, an output terminal, or a termination terminal connecting the termination resistor), and the other end connected to the ground.

かかるアイソレータは、携帯電話機においてはアンテナと送信用パワーアンプとの間に挿入され、パワーアンプからアンテナへ伝送される送信信号を通過させる一方、アンテナ側から反射されてきた不要電力を遮断する。アンテナ側からの不要電力は上記終端抵抗で熱エネルギとして消費されることとなるが、この熱を効率よく外部に逃がすことが当該アイソレータの特性を向上させる点で好ましい。このため特許文献1(特開2004−241944)の発明では、終端抵抗とグランド端子電極を特定の配置とすることによって終端抵抗からの放熱性を高めている。   Such an isolator is inserted between an antenna and a transmission power amplifier in a mobile phone, and allows transmission signals transmitted from the power amplifier to the antenna to pass therethrough, while blocking unnecessary power reflected from the antenna side. Unnecessary power from the antenna side is consumed as thermal energy by the termination resistor, but it is preferable to efficiently release this heat to the outside in terms of improving the characteristics of the isolator. For this reason, in the invention of Patent Document 1 (Japanese Patent Application Laid-Open No. 2004-241944), the heat radiation from the termination resistor is enhanced by arranging the termination resistor and the ground terminal electrode in a specific arrangement.

一方、整合用コンデンサは、高いQ値を得る点から、誘電体基板の両外面に平板状の電極を形成した単板型コンデンサによって構成することが有利である。しかしながら、単板型コンデンサは、誘電体基板が一層だけであるため十分な容量値を確保するには、誘電体基板(誘電体層)の厚さを薄くするか、誘電体基板の面積を大きくする必要がある。ところが、誘電体基板を薄くすればコンデンサ素子の機械的強度が低下する。他方、誘電体基板の面積を大きくすることは、素子の大型化を招く。単板型コンデンサでなく積層チップコンデンサを用いることも考えられるが、積層チップコンデンサは一般にQ値が低く、挿入損失が増大するため、非可逆回路素子に用いることが出来ない。   On the other hand, the matching capacitor is advantageously composed of a single plate capacitor in which flat electrodes are formed on both outer surfaces of the dielectric substrate from the viewpoint of obtaining a high Q value. However, since a single-plate capacitor has only one dielectric substrate, in order to secure a sufficient capacitance value, the thickness of the dielectric substrate (dielectric layer) is reduced or the area of the dielectric substrate is increased. There is a need to. However, if the dielectric substrate is made thinner, the mechanical strength of the capacitor element decreases. On the other hand, increasing the area of the dielectric substrate leads to an increase in the size of the element. Although it is conceivable to use a multilayer chip capacitor instead of a single plate type capacitor, the multilayer chip capacitor generally has a low Q value and increases insertion loss, and therefore cannot be used for a nonreciprocal circuit device.

そこで、特許文献2(特開2003−179408)の発明では、コンデンサ層(キャパシタ層)とこれを補強する非コンデンサ層(非キャパシタ層)とにより整合用コンデンサを形成している。非コンデンサ層を補強層として機能させることによって、コンデンサ層を薄く形成して大きな容量値を得るとともに機械的な強度を同時に確保するのである。   Therefore, in the invention of Patent Document 2 (Japanese Patent Laid-Open No. 2003-179408), a matching capacitor is formed by a capacitor layer (capacitor layer) and a non-capacitor layer (non-capacitor layer) that reinforces the capacitor layer. By making the non-capacitor layer function as a reinforcing layer, the capacitor layer is thinly formed to obtain a large capacitance value and simultaneously ensure mechanical strength.

特開2004−241944号公報JP 2004-241944 A 特開2003−179408号公報JP 2003-179408 A

ところで、上記文献記載の発明は、ともにアイソレータの特性向上を図るものではあるものの、これら文献記載の素子構造では、製造過程に起因するコンデンサの容量値の誤差を解消することは出来ない。   By the way, although the inventions described in the above documents both improve the characteristics of the isolator, the element structure described in these documents cannot eliminate the error in the capacitance value of the capacitor caused by the manufacturing process.

すなわち、誘電体基板を用いてコンデンサを形成する場合、基板表面に電極パターンを印刷し或いは積層基板を構成する各誘電体シートを積層するときに、パターンの印刷ずれやシート間の積層ずれによって対向する電極同士が正確に重なり合うことなく位置ずれを起すことがあり、このため、両電極によって形成されるコンデンサの容量値が本来得られるべき設計値から外れて容量値にばらつきが生じることがある。   That is, when a capacitor is formed using a dielectric substrate, when an electrode pattern is printed on the substrate surface or each dielectric sheet constituting the laminated substrate is laminated, it is opposed by pattern printing deviation or lamination deviation between sheets. In some cases, the electrodes do not accurately overlap with each other, causing a positional shift. For this reason, the capacitance value of the capacitor formed by both electrodes may deviate from the design value that should be originally obtained, and the capacitance value may vary.

このような容量値の誤差は、特に上記のようなアイソレータでは、整合用コンデンサが当該アイソレータの電気的特性に大きな影響を及ぼすことから、これを出来るだけ小さくすることが望ましい。さらにアイソレータに限らずコンデンサを含む他の様々な電子部品においても、容量誤差が生じることは当該電子部品の特性上好ましくない。   Such an error in the capacitance value is particularly desirable in the isolator as described above, since the matching capacitor greatly affects the electrical characteristics of the isolator. Furthermore, it is not preferable in terms of characteristics of the electronic component that a capacitance error occurs not only in the isolator but also in other various electronic components including a capacitor.

したがって、本発明の目的は、積層基板に設けられる電極間の位置ずれに起因したコンデンサ容量の誤差を低減する点にある。   Therefore, an object of the present invention is to reduce an error in the capacitance of the capacitor due to the positional deviation between the electrodes provided on the multilayer substrate.

前記課題を解決し目的を達成するため、本発明に係るコンデンサ素子は、積層基板の厚さ方向に間隔を隔てて配置されかつ互いに電気的に接続された2以上の容量電極を含む第一電極と、前記2以上の容量電極のうち前記積層基板の厚さ方向に隣り合う2つの容量電極の間に配置されて前記第一電極との間に静電容量を形成する第二電極とを備えたコンデンサ素子であって、前記第二電極は、前記積層基板の厚さ方向に間隔を隔てて配置されかつ互いに電気的に接続された2つの容量電極を少なくとも含む。   In order to solve the above-described problems and achieve the object, a capacitor element according to the present invention includes a first electrode including two or more capacitive electrodes that are arranged at intervals in the thickness direction of the multilayer substrate and are electrically connected to each other. And a second electrode that is disposed between two of the two or more capacitive electrodes adjacent to each other in the thickness direction of the multilayer substrate and forms a capacitance between the first electrode and the second electrode. In the capacitor element, the second electrode includes at least two capacitor electrodes that are spaced apart from each other in the thickness direction of the multilayer substrate and are electrically connected to each other.

静電容量(コンデンサ)を形成する一方の側の電極を電気的に(例えばビアホールで)接続した複数(例えば2枚)の電極で構成しこれら複数の電極の間に、静電容量を形成する他方の側の電極を差し挟んだ構造として基板内にコンデンサを形成することがある(以下、このような構造を差込型という)。一方、積層基板を用いてコンデンサを形成する場合には、電極パターンの印刷ずれや誘電体シートの積層ずれ等によって電極が位置ずれを起し、コンデンサの容量値に誤差(ばらつき)が生じることがある。   An electrode on one side forming a capacitance (capacitor) is composed of a plurality of (for example, two) electrodes electrically connected (for example, via holes), and a capacitance is formed between the plurality of electrodes. A capacitor may be formed in the substrate as a structure sandwiching the electrode on the other side (hereinafter such a structure is referred to as a plug-in type). On the other hand, when a capacitor is formed using a multilayer substrate, the electrodes may be misaligned due to electrode pattern printing misalignment or dielectric sheet stacking misalignment, resulting in an error (variation) in the capacitance value of the capacitor. is there.

本発明者は、かかる容量値のばらつきを減らす方法を種々検討する中で積層基板内に備えられる電極の電界強度を解析し、これに基づいて積層基板内のコンデンサ、特に上記差込型コンデンサにおける容量のばらつきを低減する電極構造を案出するに至った。   The present inventor analyzed the electric field strength of the electrodes provided in the multilayer substrate in various ways to reduce the variation in the capacitance value, and based on this, the capacitor in the multilayer substrate, in particular, the plug-in capacitor It came to devise the electrode structure which reduces the dispersion | variation in a capacity | capacitance.

すなわち本発明では、上記差込型コンデンサにおいて第一電極に含まれる2つの容量電極間に差し挟まれた第二電極の容量電極を互いに電気的に接続された複数の電極により構成する。   That is, according to the present invention, the second electrode capacitive electrode sandwiched between two capacitive electrodes included in the first electrode in the plug-in capacitor is constituted by a plurality of electrodes electrically connected to each other.

既存の差込型コンデンサでは、コンデンサを形成する一方の電極(第一電極)に含まれる1組の電極間に、コンデンサを形成する他方の電極(第二電極)に含まれる1枚の電極が差し挟まれる形態となっており、このような構造では、当該差し挟まれる電極に電界が集中する(他の電極と比較して強い電界が生じる)ことを上記解析によって本発明者は確認した。   In an existing plug-in capacitor, one electrode included in the other electrode (second electrode) forming the capacitor is between one set of electrodes included in one electrode (first electrode) forming the capacitor. The present inventor confirmed from the above analysis that the electric field concentrates on the electrode sandwiched (in this structure, a stronger electric field is generated compared to the other electrodes).

これに対し、当該差し挟まれる電極を複数とした上記本発明の構造によれば、当該差し挟まれる電極への電界の集中が緩和されて積層ずれや印刷ずれ等によって電極が位置ずれを起した場合にもその影響が少なくなり、当該コンデンサの容量変動を小さく抑えることが可能となる。尚、この点については図面に基づいて後に更に述べる。   On the other hand, according to the structure of the present invention in which a plurality of the sandwiched electrodes are provided, the concentration of the electric field on the sandwiched electrodes is alleviated, and the electrodes are displaced due to stacking displacement or printing displacement. Even in this case, the influence is reduced, and the capacitance fluctuation of the capacitor can be suppressed to a small value. This point will be further described later with reference to the drawings.

また、上記本発明のコンデンサ素子では、第二電極に含まれる2つの容量電極同士の間隔が、互いに対向して前記静電容量が形成される第一電極の容量電極と第二電極の容量電極との間の間隔より大きくなるように各電極を配置することが好ましい。   In the capacitor element of the present invention, the capacitance between the first electrode and the second electrode in which the capacitance is formed so that the interval between the two capacitance electrodes included in the second electrode is opposed to each other. It is preferable to arrange each electrode so as to be larger than the distance between them.

上記差し挟まれる電極(第二電極に含まれる容量電極)のうちの1つが位置ずれを起した場合に、容量形成を行う電極(第一電極に含まれる前記2つの容量電極のうちの一方の電極)ではない、本来容量形成を意図しない他の電極(第一電極に含まれる前記2つの容量電極のうちの他方の電極)との間に容量が形成され、これによって当該コンデンサの容量値の変動が生じることを防ぐためである。   When one of the electrodes sandwiched (capacitance electrode included in the second electrode) is displaced, an electrode for forming a capacitor (one of the two capacitance electrodes included in the first electrode) A capacitor is formed between the other electrode (the other electrode of the two capacitor electrodes included in the first electrode) that is not originally intended to form a capacitor, and the capacitance value of the capacitor is thereby reduced. This is to prevent fluctuations from occurring.

また本発明に係る非可逆回路素子は、信号が入力される入力端子と、信号が出力される出力端子と、これら入力端子および出力端子間に設けられた磁気回転子と、当該磁気回転子に直流磁界を印加する磁石と、一端が前記磁気回転子に電気的に接続され、他端がグランドに電気的に接続された1以上の整合用コンデンサとを備えた非可逆回路素子であって、前記整合用コンデンサのうち少なくとも1つを上記本発明に係るコンデンサ素子とした。   The nonreciprocal circuit device according to the present invention includes an input terminal for inputting a signal, an output terminal for outputting a signal, a magnetic rotor provided between the input terminal and the output terminal, and the magnetic rotor. A nonreciprocal circuit device comprising a magnet for applying a DC magnetic field, and one or more matching capacitors, one end of which is electrically connected to the magnetic rotor and the other end of which is electrically connected to the ground, At least one of the matching capacitors is a capacitor element according to the present invention.

非可逆回路素子(例えばアイソレータ)において整合用コンデンサは、当該素子の電気的特性を決定するのに重要な役割を果たすが、上記のように整合用コンデンサとして上記本発明のコンデンサ素子を使用すれば、整合用コンデンサの容量誤差の少ない良好な電気的特性を有する非可逆回路素子を構成することが出来る。   In a non-reciprocal circuit element (for example, an isolator), a matching capacitor plays an important role in determining the electrical characteristics of the element. However, as described above, if the capacitor element of the present invention is used as a matching capacitor, Thus, a non-reciprocal circuit device having good electrical characteristics with less capacitance error of the matching capacitor can be configured.

尚、当該非可逆回路素子には、アイソレータのほか、例えばサーキュレータ等が含まれる。また上記本発明に係るコンデンサ素子は、コンデンサの単体素子として構成されていても良いし、非可逆回路素子以外の様々な電子部品・回路モジュールに含まれた形態であっても構わない。   The nonreciprocal circuit element includes, for example, a circulator in addition to an isolator. The capacitor element according to the present invention may be configured as a single element of a capacitor or may be included in various electronic components / circuit modules other than the non-reciprocal circuit element.

本発明によれば、積層基板に設けられる電極間の位置ずれに起因したコンデンサ容量の誤差を低減することが出来る。   According to the present invention, it is possible to reduce an error in the capacitance of the capacitor due to the positional deviation between the electrodes provided on the multilayer substrate.

本発明の他の目的、特徴および利点は、図面を参照しつつ述べる以下の本発明の実施の形態の説明により明らかにするが、実施形態の説明に先立ちその前提となる従来の差込型電極構造を有するコンデンサ素子についてまず説明し、その後、この素子との対比において本発明の実施形態について述べる。尚、各図中、同一の符号は同一又は相当部分を示す。   Other objects, features, and advantages of the present invention will be clarified by the following description of the embodiments of the present invention described with reference to the drawings. Prior to the description of the embodiments, conventional plug-in electrodes First, a capacitor element having a structure will be described, and then an embodiment of the present invention will be described in comparison with the element. In each figure, the same numerals indicate the same or corresponding parts.

図1は差込型電極構造を有する従来のコンデンサ素子の一例を示すものである。同図に示すようにこのコンデンサ素子は、基板の表裏面を含めて8層の配線層を有する積層基板の内部にコンデンサを内蔵させたもので、これら配線層を基板表面から基板裏面に向け順に第1層(基板表面)L1、第2層L2、第3層L3、…、第8層(基板裏面)L8とした場合に当該コンデンサは、第3層L3に設けた容量電極14と、この容量電極14とビアホールV(以下、単にビアという)を通じて電気的に接続し略同電位とした第5層L5に設けた容量電極11によってコンデンサの一方の電極(第一電極)を構成する一方、第4層L4に設けた容量電極21と、この容量電極21とビアVを通じて電気的に接続された第6層L6に設けた容量電極24によってコンデンサの他方の電極(第二電極)を構成したものである。   FIG. 1 shows an example of a conventional capacitor element having a plug-in electrode structure. As shown in the figure, this capacitor element has a built-in capacitor in a multilayer substrate having eight wiring layers including the front and back surfaces of the substrate, and these wiring layers are arranged in order from the substrate surface to the substrate back surface. When the first layer (substrate surface) L1, the second layer L2, the third layer L3,..., The eighth layer (back surface of the substrate) L8, the capacitor includes the capacitive electrode 14 provided on the third layer L3, One electrode of the capacitor (first electrode) is constituted by the capacitor electrode 11 provided in the fifth layer L5 that is electrically connected to the capacitor electrode 14 through the via hole V (hereinafter simply referred to as via) and has substantially the same potential. The capacitor electrode 21 provided on the fourth layer L4 and the capacitor electrode 24 provided on the sixth layer L6 electrically connected to the capacitor electrode 21 through the via V constitute the other electrode (second electrode) of the capacitor. Is.

またこのコンデンサ素子は、第3層L3の容量電極14と第5層L5の容量電極11との間に第4層L4の容量電極21が差し挟まれるように、さらに第4層L4の容量電極21と第6層L6の容量電極24との間に第5層L5の容量電極11が差し挟まれるように配置する。より具体的には、第3層L3の容量電極14と第5層L5の容量電極11は、これら電極の一端部側においてビアVによって電気的に接続され、ビアVを設けていない電極他端部側から第4層L4の容量電極21が差し込まれるように配置されている。また、第4層L4の容量電極21と第6層L6の容量電極24についても同様に、これらの電極は一端部側においてビアVによって電気的に接続され、ビアVを設けていない電極他端部側から第5層L5の容量電極11が差し込まれる形となっている。   The capacitor element further includes a capacitor electrode of the fourth layer L4 such that a capacitor electrode 21 of the fourth layer L4 is interposed between the capacitor electrode 14 of the third layer L3 and the capacitor electrode 11 of the fifth layer L5. 21 and the capacitive electrode 24 of the sixth layer L6 are arranged so that the capacitive electrode 11 of the fifth layer L5 is sandwiched between them. More specifically, the capacitive electrode 14 of the third layer L3 and the capacitive electrode 11 of the fifth layer L5 are electrically connected by a via V on one end side of these electrodes, and the other end of the electrode not provided with the via V It arrange | positions so that the capacity | capacitance electrode 21 of the 4th layer L4 may be inserted from the part side. Similarly, for the capacitive electrode 21 of the fourth layer L4 and the capacitive electrode 24 of the sixth layer L6, these electrodes are electrically connected by a via V on one end side, and the other end of the electrode not provided with the via V is provided. The capacitor electrode 11 of the fifth layer L5 is inserted from the part side.

そしてこれら電極間に差し挟まれた容量電極11,21(以下、差込電極という)が、誘電体層(絶縁層)を介して上下に隣り合う相手方(第一電極又は第二電極)の電極と対向し、これにより第3層L3の容量電極14と第4層L4の容量電極21との間、第4層L4の容量電極21と第5層L5の容量電極11との間、並びに第5層L5の容量電極11と第6層L6の容量電極24との間にそれぞれ静電容量が形成される。尚、基板表面(第1層)L1および基板裏面(第8層)L8にはそれぞれ外部電極25,15を設け、これら外部電極25,15の各々にビアVを介して上記第一電極と第二電極をそれぞれ接続してある。   Capacitance electrodes 11 and 21 (hereinafter referred to as insertion electrodes) sandwiched between these electrodes are opposite electrodes (first electrode or second electrode) that are adjacent to each other via a dielectric layer (insulating layer). Thus, between the capacitive electrode 14 of the third layer L3 and the capacitive electrode 21 of the fourth layer L4, between the capacitive electrode 21 of the fourth layer L4 and the capacitive electrode 11 of the fifth layer L5, and Capacitances are respectively formed between the capacitive electrode 11 of the fifth layer L5 and the capacitive electrode 24 of the sixth layer L6. External electrodes 25 and 15 are provided on the substrate surface (first layer) L1 and the substrate back surface (eighth layer) L8, respectively. The external electrodes 25 and 15 are connected to the first electrode and the first electrode via vias V, respectively. Two electrodes are connected to each other.

一方、図2は本発明の一実施形態に係るコンデンサ素子を示す断面図である。この実施形態の素子では、前記従来のコンデンサ素子と同様に8層の配線層L1〜L8を有する積層基板にコンデンサを内蔵させたものであるが、当該コンデンサの一方の電極である第一電極を、互いにビアVによって電気的に接続された第2層L2、第5層L5および第6層L6にそれぞれ設けた容量電極14,12,13により構成する一方、当該第一電極の相手方の電極となってコンデンサを形成する第二電極を、互いにビアVによって電気的に接続された第3層L3、第4層L4および第7層L7にそれぞれ設けた容量電極22,23,24により構成したものである。   On the other hand, FIG. 2 is a sectional view showing a capacitor element according to an embodiment of the present invention. In the element of this embodiment, a capacitor is built in a laminated substrate having eight wiring layers L1 to L8 as in the conventional capacitor element, but the first electrode which is one electrode of the capacitor is provided. The capacitor electrodes 14, 12, and 13 are provided on the second layer L2, the fifth layer L5, and the sixth layer L6 that are electrically connected to each other by the vias V, respectively, The second electrode forming the capacitor is composed of capacitive electrodes 22, 23, 24 provided on the third layer L3, the fourth layer L4, and the seventh layer L7, which are electrically connected to each other by the via V, respectively. It is.

そして、これら容量電極のうち第二電極に属する第3層L3と第4層L4の電極22,23を、第一電極に属する第2層L2と第5層L5の電極14,12の間に差し挟まれるように、かつ、電極の端部位置が揃うように(どちらかの電極が突出しないように)配置するとともに、第一電極に属する第5層L5と第6層L6の電極12,13を、第二電極に属する第4層L4と第7層L7の電極23,24の間に差し挟まれるようにかつ同様に端部位置が揃うように配置してあり、これにより第2層L2の電極14と第3層L3の電極22との間、第4層L4の電極23と第5層L5の電極12との間、並びに第6層L6の電極13と第7層L7の電極24との間にそれぞれ静電容量を形成した。   Of these capacitive electrodes, the electrodes 22 and 23 of the third layer L3 and the fourth layer L4 belonging to the second electrode are placed between the electrodes 14 and 12 of the second layer L2 and the fifth layer L5 belonging to the first electrode. The electrodes are arranged so as to be sandwiched and the end positions of the electrodes are aligned (so that one of the electrodes does not protrude), and the electrodes 12 of the fifth layer L5 and the sixth layer L6 belonging to the first electrode, 13 is arranged so as to be sandwiched between the electrodes 23 and 24 of the fourth layer L4 and the seventh layer L7 belonging to the second electrode and so that the end positions thereof are also aligned, whereby the second layer Between the electrode 14 of the L2 and the electrode 22 of the third layer L3, between the electrode 23 of the fourth layer L4 and the electrode 12 of the fifth layer L5, and between the electrode 13 of the sixth layer L6 and the electrode of the seventh layer L7 A capacitance was formed between each of them.

つまり、本実施形態では、第一電極および第二電極の容量電極について上記図1に示したコンデンサ素子と同様の差込構造を有するが、コンデンサを形成する相手方の電極間に差し挟まれる差込電極11a,21aを、基板の厚さ方向に隣り合いかつ互いにビアVで接続された2枚の電極12,13;22,23によって構成したのである。尚、上記差込電極11a(12,13)および差込電極21a(22,23)は、本実施形態のように端部位置が揃うようにそれぞれ構成することが望ましいが、本発明では必ずしもこの実施形態のように差込電極の端部を完全に揃える必要はなく、いずれかの電極が突出している構造も本発明の範囲内である。   That is, in the present embodiment, the first electrode and the second electrode capacitive electrode have the same insertion structure as the capacitor element shown in FIG. 1, but are inserted between the counterpart electrodes forming the capacitor. The electrodes 11a and 21a are constituted by two electrodes 12, 13; 22, 23 which are adjacent to each other in the thickness direction of the substrate and are connected to each other by vias V. The insertion electrodes 11a (12, 13) and the insertion electrodes 21a (22, 23) are preferably configured so that their end positions are aligned as in the present embodiment. It is not necessary to completely align the end portions of the insertion electrodes as in the embodiment, and a structure in which any one of the electrodes protrudes is within the scope of the present invention.

さらに本実施形態では、上記差込電極11a,21aを構成する2つの電極12,13;22,23の間の間隔t0を、容量を形成する電極間の間隔t1より大きくしてある。これは、当該差込電極内の電極同士が相対的に位置ずれを起し、電極先端位置がずれた(どちらかの電極が左右方向に突出した)場合に、本来容量形成を意図しない電極との間に容量が形成され、これによって当該コンデンサの容量値の変動が生じることを防ぐためである。より具体的には、例えば第3層L3の電極22が図の左方に位置ずれした場合にはこの電極22と、容量形成を本来予定してない第5層L5の電極12との間に容量結合が生じる可能性があるが、差込電極の間隔t0を広くしておくことで、この不必要に形成される容量を減らすことが出来る。   Furthermore, in this embodiment, the interval t0 between the two electrodes 12, 13; 22, 23 constituting the insertion electrodes 11a, 21a is made larger than the interval t1 between the electrodes forming the capacitance. This is because when the electrodes in the insertion electrode are relatively displaced and the tip position of the electrode is shifted (one of the electrodes protrudes in the left-right direction), This is to prevent a capacitance from being formed between the capacitor and the capacitance value of the capacitor. More specifically, for example, when the electrode 22 of the third layer L3 is displaced to the left in the figure, between this electrode 22 and the electrode 12 of the fifth layer L5 that is not originally scheduled for capacitance formation. Although capacitive coupling may occur, the capacitance formed unnecessarily can be reduced by widening the interval t0 between the insertion electrodes.

本発明者は、上記のような差込型構造を有するコンデンサ素子の電界強度の解析を行った。図3および図4はその解析結果を示すものであり、図3は差込電極11が1枚の場合(従来構造)、図4は差込電極21aを2枚の電極22,23に分けた場合(本願構造)である。またこれらの図においてハッチングを施した領域は電界強度が5×106〔V/m〕未満の部分を、網掛けハッチングを施した領域は電界強度が5×106〔V/m〕以上7×106〔V/m〕未満の部分を、黒く塗りつぶした領域は電界強度が7×106〔V/m〕以上の部分をそれぞれ示している。 The inventor has analyzed the electric field strength of the capacitor element having the plug-in structure as described above. FIG. 3 and FIG. 4 show the analysis results. FIG. 3 shows the case where there is one insertion electrode 11 (conventional structure), and FIG. 4 shows that the insertion electrode 21a is divided into two electrodes 22 and 23. This is the case (structure of the present application). In these drawings, the hatched region has a field intensity of less than 5 × 10 6 [V / m], and the shaded region has a field strength of 5 × 10 6 [V / m] or more. The regions where the portions less than × 10 6 [V / m] are blacked out indicate portions where the electric field strength is 7 × 10 6 [V / m] or more.

これらの図から明らかなように、差込電極11が1枚である従来の構造(図3)では、当該差込電極11に電界が集中し、他の電極に較べ強い電界が生じていることが分かる。これに対し差込電極21aを2枚の電極22,23により構成した本発明に基づく構造(図4)では、差込電極21aへの電界の集中が緩和され、当該差込電極21aの電界は他の電極と同程度の強度に抑えられていることが分かる。   As is clear from these figures, in the conventional structure (FIG. 3) with one insertion electrode 11, the electric field concentrates on the insertion electrode 11 and a stronger electric field is generated than the other electrodes. I understand. On the other hand, in the structure (FIG. 4) based on this invention which comprised the insertion electrode 21a by the two electrodes 22 and 23, concentration of the electric field to the insertion electrode 21a is relieve | moderated, and the electric field of the said insertion electrode 21a is It can be seen that the strength is suppressed to the same level as the other electrodes.

したがって、上記図1に示す従来の素子構造では、容量を形成する差込電極11,21に電界が集中するため、この電極11,21あるいはこの電極11,21と容量を形成する相手方の電極14,24が位置ずれを起すと、容量の変動が大きくなる。一方、上記図2に示す本実施形態の素子構造によれば、差込電極11a,21aを含め、容量を形成するすべての電極が同程度の低い電界強度となるため、位置ずれによる容量変動を小さく抑えることが出来る。   Therefore, in the conventional element structure shown in FIG. 1, since the electric field concentrates on the insertion electrodes 11 and 21 forming the capacitance, the electrodes 11 and 21 or the electrodes 14 and the counterpart electrode 14 forming the capacitance are formed. , 24 cause a displacement, the capacity variation increases. On the other hand, according to the element structure of this embodiment shown in FIG. 2 above, since all the electrodes forming the capacitance, including the insertion electrodes 11a and 21a, have the same low electric field strength, the capacitance variation due to the displacement is caused. It can be kept small.

電極の配置構造は、図2に示した例に限られず、様々な態様をとることが可能である。例えば図5は本発明における電極の配置例を示す模式図であり、各図中、水平方向のラインはコンデンサを形成する電極を、垂直方向のラインは各電極を接続するビアを示している。この図に示すように本発明では、第一電極と第二電極の一方のみが差込電極を備えていても良いし(例えば同図(a),(b),(d))、第一電極と第二電極の両方が差込電極を備えていても構わない(例えば同図(c),(e))。また第一電極と第二電極のいずれか一方または双方に2以上の差込電極を備えることも出来る(例えば同図(d),(e))。さらに前記実施形態では、第一電極用の外部電極と、第二電極用の外部電極とをそれぞれ基板の表裏反対側の面に設けたが、これら外部電極を同一側の面(基板表面又は裏面)に設けても良い。この場合、第一・第二各電極から外部電極に接続されるビアは図5(b)に示すように同一方向に延びることとなる。   The arrangement structure of the electrodes is not limited to the example shown in FIG. 2 and can take various forms. For example, FIG. 5 is a schematic diagram showing an arrangement example of electrodes in the present invention. In each figure, horizontal lines indicate electrodes forming capacitors, and vertical lines indicate vias connecting the electrodes. As shown in this figure, in the present invention, only one of the first electrode and the second electrode may be provided with an insertion electrode (for example, (a), (b), (d) in the figure), Both the electrode and the second electrode may be provided with insertion electrodes (for example, (c) and (e) in the figure). Further, two or more insertion electrodes can be provided on one or both of the first electrode and the second electrode (for example, (d) and (e) in the figure). Furthermore, in the above-described embodiment, the external electrode for the first electrode and the external electrode for the second electrode are provided on the opposite surfaces of the substrate, respectively, but these external electrodes are provided on the same surface (substrate surface or back surface). ) May be provided. In this case, the vias connected from the first and second electrodes to the external electrode extend in the same direction as shown in FIG.

図6は、本発明の他の実施形態に係る非可逆回路素子(アイソレータ)を示す回路図である。このアイソレータは、従来から知られたアイソレータと同様に、信号が入力される入力端子31と、信号が出力される出力端子32と、これら入力端子31および出力端子32間に設けられた磁気回転子34と、磁気回転子34に直流磁界を印加する磁石(図示せず)と、終端端子33に接続された終端抵抗38と、一端が前記磁気回転子34に電気的に接続されとともに他端がグランドに電気的に接続された3個の整合用コンデンサ35,36,37とを備えるが、従来のアイソレータと異なり、整合用コンデンサ35〜37を前記実施形態に係るコンデンサ素子により構成したものである。   FIG. 6 is a circuit diagram showing a non-reciprocal circuit device (isolator) according to another embodiment of the present invention. This isolator is similar to conventionally known isolators in that an input terminal 31 to which a signal is input, an output terminal 32 from which a signal is output, and a magnetic rotor provided between the input terminal 31 and the output terminal 32. 34, a magnet (not shown) for applying a DC magnetic field to the magnetic rotor 34, a termination resistor 38 connected to the termination terminal 33, one end electrically connected to the magnetic rotor 34 and the other end Unlike the conventional isolator, the matching capacitors 35 to 37 are configured by the capacitor element according to the above embodiment, which includes three matching capacitors 35, 36, and 37 that are electrically connected to the ground. .

アイソレータにおいて整合用コンデンサ35〜37は、当該アイソレータの周波数特性を決定するのに重要な役割を果たすが、上記のように整合用コンデンサ35〜37として本実施形態のコンデンサ素子を使用すれば、整合用コンデンサ35〜37の容量誤差の少ない良好な電気的特性を有するアイソレータを構成することが出来る。   In the isolator, the matching capacitors 35 to 37 play an important role in determining the frequency characteristics of the isolator. As described above, if the capacitor element of the present embodiment is used as the matching capacitors 35 to 37, the matching capacitors 35 to 37 are matched. It is possible to construct an isolator having good electrical characteristics with little capacitance error of the capacitors 35 to 37 for use.

以上、本発明の実施の形態について説明したが、本発明はこれらに限定されるものではなく、特許請求の範囲に記載の範囲内で種々の変更を行うことができることは当業者に明らかである。例えば、基板の種類(有機系積層基板、LTCCほか無機セラミック系積層基板等)や基板の積層数、絶縁層および電極の構成材料、基板・電極の形成方法(サブトラクティブ法、セミアディティブ法、フルアディティブ法等)は特に限定されない。また本発明は、コンデンサの単体素子、アイソレータやサーキュレータのような非可逆回路素子のほか、コンデンサを基板に含んだ各種の電子部品・機能モジュールに広く適用することが可能である。   As mentioned above, although embodiment of this invention was described, this invention is not limited to these, It is clear to those skilled in the art that a various change can be made within the range as described in a claim. . For example, the type of substrate (organic multilayer substrate, LTCC or other inorganic ceramic multilayer substrate), the number of laminated layers, insulating layers and electrode constituent materials, substrate / electrode formation methods (subtractive method, semi-additive method, full The additive method is not particularly limited. Further, the present invention can be widely applied to various electronic components / functional modules including a capacitor on a substrate, in addition to a single element of a capacitor, a nonreciprocal circuit device such as an isolator or a circulator.

従来の差込型電極構造を有するコンデンサ素子の一例を示す断面図である。It is sectional drawing which shows an example of the capacitor | condenser element which has the conventional insertion type electrode structure. 本発明の一実施形態に係るコンデンサ素子を示す断面図である。It is sectional drawing which shows the capacitor | condenser element which concerns on one Embodiment of this invention. 従来の差込型電極構造を有するコンデンサ素子における電界強度分布を示す図である。It is a figure which shows the electric field strength distribution in the capacitor | condenser element which has the conventional insertion-type electrode structure. 本発明を適用した差込型電極構造を有するコンデンサ素子における電界強度分布を示す図である。It is a figure which shows the electric field strength distribution in the capacitor | condenser element which has a plug-in type electrode structure to which this invention is applied. 本発明のコンデンサ素子における電極の配置例を示す模式図である。It is a schematic diagram which shows the example of arrangement | positioning of the electrode in the capacitor | condenser element of this invention. 本発明の一実施形態に係る非可逆回路素子(アイソレータ)を示す回路図である。It is a circuit diagram showing a nonreciprocal circuit device (isolator) according to an embodiment of the present invention.

符号の説明Explanation of symbols

11,21,11a,21a 差込電極
12,13,14,22,23,24 容量電極
15,25 外部電極
31 入力端子
32 出力端子
33 終端端子
34 磁気回転子
35,36,37 整合用コンデンサ
L1〜L8 配線層
V ビアホール
11, 21, 11a, 21a Insertion electrode 12, 13, 14, 22, 23, 24 Capacitance electrode 15, 25 External electrode 31 Input terminal 32 Output terminal 33 Termination terminal 34 Magnetic rotor 35, 36, 37 Matching capacitor L1 ~ L8 Wiring layer V Via hole

Claims (3)

積層基板の厚さ方向に間隔を隔てて配置されかつ互いに電気的に接続された2以上の容量電極を含む第一電極と、
前記2以上の容量電極のうち前記積層基板の厚さ方向に隣り合う2つの容量電極の間に配置されて前記第一電極との間に静電容量を形成する第二電極とを備えたコンデンサ素子であって、
前記第二電極は、前記積層基板の厚さ方向に間隔を隔てて配置されかつ互いに電気的に接続された2つの容量電極を少なくとも含む
ことを特徴とするコンデンサ素子。
A first electrode including two or more capacitive electrodes arranged at intervals in the thickness direction of the multilayer substrate and electrically connected to each other;
A capacitor comprising a second electrode that is arranged between two capacitive electrodes adjacent to each other in the thickness direction of the multilayer substrate among the two or more capacitive electrodes and forms a capacitance between the first electrode and the first electrode. An element,
The capacitor element is characterized in that the second electrode includes at least two capacitor electrodes arranged at an interval in the thickness direction of the multilayer substrate and electrically connected to each other.
前記第二電極に含まれる2つの容量電極同士の間隔が、互いに対向して前記静電容量が形成される第一電極の容量電極と第二電極の容量電極との間の間隔より大きい
ことを特徴とする請求項1に記載のコンデンサ素子。
The interval between the two capacitance electrodes included in the second electrode is larger than the interval between the capacitance electrode of the first electrode and the capacitance electrode of the second electrode, which are formed so as to face each other. The capacitor element according to claim 1.
信号が入力される入力端子と、
信号が出力される出力端子と、
これら入力端子および出力端子間に設けられた磁気回転子と、
当該磁気回転子に直流磁界を印加する磁石と、
一端が前記磁気回転子に電気的に接続され、他端がグランドに電気的に接続された1以上の整合用コンデンサと、
を備えた非可逆回路素子であって、
前記整合用コンデンサのうち少なくとも1つが前記請求項1または2のコンデンサ素子である
ことを特徴とする非可逆回路素子。
An input terminal to which a signal is input;
An output terminal for outputting a signal;
A magnetic rotor provided between the input terminal and the output terminal;
A magnet for applying a DC magnetic field to the magnetic rotor;
One or more matching capacitors having one end electrically connected to the magnetic rotor and the other end electrically connected to ground;
A non-reciprocal circuit device comprising:
3. A nonreciprocal circuit device, wherein at least one of the matching capacitors is the capacitor device according to claim 1 or 2.
JP2005182685A 2005-06-22 2005-06-22 Capacitor element and non-reciprocal circuit element Pending JP2007005501A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005182685A JP2007005501A (en) 2005-06-22 2005-06-22 Capacitor element and non-reciprocal circuit element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005182685A JP2007005501A (en) 2005-06-22 2005-06-22 Capacitor element and non-reciprocal circuit element

Publications (1)

Publication Number Publication Date
JP2007005501A true JP2007005501A (en) 2007-01-11

Family

ID=37690832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005182685A Pending JP2007005501A (en) 2005-06-22 2005-06-22 Capacitor element and non-reciprocal circuit element

Country Status (1)

Country Link
JP (1) JP2007005501A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160008278A (en) * 2014-07-14 2016-01-22 조인셋 주식회사 Flat typed capacitor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06349666A (en) * 1993-06-02 1994-12-22 Taiyo Yuden Co Ltd Multilayered ceramic capacitor
JPH1097947A (en) * 1996-09-24 1998-04-14 Taiyo Yuden Co Ltd Laminated capacitor
JP2003179408A (en) * 2001-12-11 2003-06-27 Tdk Corp Non-reciprocal circuit element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06349666A (en) * 1993-06-02 1994-12-22 Taiyo Yuden Co Ltd Multilayered ceramic capacitor
JPH1097947A (en) * 1996-09-24 1998-04-14 Taiyo Yuden Co Ltd Laminated capacitor
JP2003179408A (en) * 2001-12-11 2003-06-27 Tdk Corp Non-reciprocal circuit element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160008278A (en) * 2014-07-14 2016-01-22 조인셋 주식회사 Flat typed capacitor
KR101600504B1 (en) * 2014-07-14 2016-03-07 조인셋 주식회사 Flat typed capacitor

Similar Documents

Publication Publication Date Title
US9252489B2 (en) Circuit board and circuit module
JP5482901B2 (en) Directional coupler
EP2785155B1 (en) Circuit board and electronic device
US9119318B2 (en) Multilayer substrate module
JP2016092561A (en) Transmission line and flat cable
EP2862228B1 (en) Balun
JP5153771B2 (en) Terminator
US7667980B2 (en) Printed circuit boards for countering signal distortion
JP2007096159A (en) Multilayer printed wiring board
JP6344476B2 (en) Multilayer circuit board
JP2003258510A (en) Wired transmission line
JP2007005501A (en) Capacitor element and non-reciprocal circuit element
US9318786B2 (en) High-frequency signal line and electronic device
WO2017199824A1 (en) Multilayer substrate and electronic appliance
WO2021005966A1 (en) Transmission line and transmission line manufacturing method
JP2007012711A (en) Capacitive element and non reciprocal circuit element
JP2006140933A (en) Interlayer connector of transmission line
JP5005915B2 (en) Multilayer dielectric resonator and multilayer dielectric filter
JP2007005631A (en) Capacitor element and non-reciprocal circuit element
JP5306551B1 (en) Multilayer circuit board
JP4417235B2 (en) Oscillator
JP4457335B2 (en) Non-reciprocal circuit element
JP4588679B2 (en) Filter device
JP2005353889A (en) High frequency multilayer integrated circuit
JP2009283797A (en) Substrate with built-in distributed constant circuit

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080512

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100318

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100401

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100721