JPH06349666A - Multilayered ceramic capacitor - Google Patents

Multilayered ceramic capacitor

Info

Publication number
JPH06349666A
JPH06349666A JP5157874A JP15787493A JPH06349666A JP H06349666 A JPH06349666 A JP H06349666A JP 5157874 A JP5157874 A JP 5157874A JP 15787493 A JP15787493 A JP 15787493A JP H06349666 A JPH06349666 A JP H06349666A
Authority
JP
Japan
Prior art keywords
conductor layers
dielectric
multilayer capacitor
electrodes
internal electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5157874A
Other languages
Japanese (ja)
Inventor
Koichiro Tsujiku
浩一郎 都竹
Naoto Narita
直人 成田
Yoichi Mizuno
洋一 水野
Atsushi Masuda
淳 増田
Riichi Toba
利一 鳥羽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP5157874A priority Critical patent/JPH06349666A/en
Publication of JPH06349666A publication Critical patent/JPH06349666A/en
Withdrawn legal-status Critical Current

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  • Ceramic Capacitors (AREA)

Abstract

PURPOSE:To prevent influence of an external circuit which is to be exerted upon a multilayered capacitor. CONSTITUTION:A first inner electrode 2 and a second inner electrode 3 are buried in ceramic dielectric material 1, and connected with an outer electrode 4 and an outer electrode 5, respectively. The first and the second inner electrodes 2, 3 consist of a plurality of conductor layers, which are connected with the same outer electrode every two adjacent conductor layers.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高周波領域で使用する
ことが可能な積層セラミックコンデンサに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic ceramic capacitor which can be used in a high frequency range.

【0002】[0002]

【従来の技術】従来の典型的な積層セラミックコンデン
サは、図5に示すようにセラミック誘電体1と、この中
に交互に埋設された第1及び第2の内部電極2、3と、
第1及び第2の内部電極2、3に接続された第1及び第
2の外部電極4、5とから成る。この積層コンデンサで
は、第1及び第2の内部電極2、3の対向によって容量
が得られる。別の従来の積層コンデンサとして図6に示
す構造のものが知られている。図6の積層コンデンサで
は、第1の内部電極2の相互間に2つの第2の内部電極
3が配置され、また第2の内部電極3の相互間に2つの
第1の内部電極2が配置されている。この様に構成する
と、最も下側及び最も上側を除いた内部電極2、3に流
れる電流が図5の場合の1/2になるので、品質係数Q
を高めることができる。
2. Description of the Related Art As shown in FIG. 5, a typical conventional monolithic ceramic capacitor has a ceramic dielectric 1 and first and second internal electrodes 2 and 3 alternately embedded therein.
It is composed of first and second outer electrodes 4, 5 connected to the first and second inner electrodes 2, 3. In this multilayer capacitor, capacitance is obtained by the facing of the first and second internal electrodes 2, 3. As another conventional multilayer capacitor, one having a structure shown in FIG. 6 is known. In the multilayer capacitor of FIG. 6, two second inner electrodes 3 are arranged between the first inner electrodes 2 and two first inner electrodes 2 are arranged between the second inner electrodes 3. Has been done. With this configuration, the current flowing through the internal electrodes 2 and 3 excluding the lowermost and uppermost portions is half that in the case of FIG.
Can be increased.

【0003】[0003]

【発明が解決しようとする課題】ところで、最近の電子
回路装置では電子部品が回路基板上に高密度実装されて
いる。このため回路基板上の配線導体を積層コンデンサ
の下を通さなければならないことがある。この様な場合
には積層コンデンサの内部電極と回路基板上の配線導体
との間の浮遊容量(ストレーキャパシタンス)に基づく
電流が内部電極に流れ、Qを低下させる。また、回路基
板上の配線導体からノイズ成分が積層コンデンサを含む
回路に入り込む恐れがある。
By the way, in recent electronic circuit devices, electronic components are mounted on a circuit board at a high density. Therefore, the wiring conductor on the circuit board may have to pass under the multilayer capacitor. In such a case, a current based on stray capacitance (stray capacitance) between the internal electrode of the multilayer capacitor and the wiring conductor on the circuit board flows through the internal electrode, which lowers Q. Further, noise components may enter the circuit including the multilayer capacitor from the wiring conductor on the circuit board.

【0004】そこで、本発明の目的は、内部電極の電流
密度を低くしてQを高めることができると共に、外部回
路の影響を低減することができる積層セラミックコンデ
ンサを提供することにある。
Therefore, an object of the present invention is to provide a monolithic ceramic capacitor capable of lowering the current density of the internal electrodes to increase the Q and reducing the influence of the external circuit.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
の本発明は、第1及び第2の主面と側面とを有する誘電
体と、前記誘電体に埋設された複数の導体層からなる第
1及び第2の内部電極と、前記誘電体の外周面に設けら
れ且つ前記第1及び第2の内部電極に接続された第1及
び第2の外部電極とを有する積層セラミックコンデンサ
において、前記第1の内部電極が複数の導体層毎に複数
のグループに分割され、前記第2の内部電極も複数の導
体層毎に複数のグループに分割され、前記第1の内部電
極の前記複数のグループが交互に配置されていることを
特徴とする積層セラミックコンデンサに係わるものであ
る。
The present invention for achieving the above object comprises a dielectric having first and second main surfaces and side surfaces, and a plurality of conductor layers embedded in the dielectric. A multilayer ceramic capacitor having first and second internal electrodes and first and second external electrodes provided on an outer peripheral surface of the dielectric and connected to the first and second internal electrodes, The first internal electrode is divided into a plurality of groups for each of a plurality of conductor layers, the second internal electrode is also divided into a plurality of groups of each of a plurality of conductor layers, and the plurality of groups of the first internal electrode are divided. The present invention relates to a monolithic ceramic capacitor characterized in that are alternately arranged.

【0006】[0006]

【発明の作用及び効果】本発明では第1及び第2の内部
電極の複数の導体層がグループ化され、グループ毎に交
互に配置されている。第1及び第2の内部電極の導体層
の最も上の導体層と最も下の導体層は、所望の静電容量
を得るために直接に寄与しないが、静電容量を得るため
に使用される中間の導電層に浮遊容量に基づく電流が流
れることを阻止するために寄与し、更に電磁的シールド
効果を発揮する。また、内部電極の導体層は中央領域に
おいてもグループ化され、複数(好ましくは2枚)の導
体層が同一方向に導出されているので、静電容量に基づ
いて1つの導電層に流れる電流を1/2に低減すること
ができ、Qを高めること即ち信号ロスを低減することが
できる。
According to the present invention, a plurality of conductor layers of the first and second internal electrodes are grouped and arranged alternately for each group. The uppermost conductor layer and the lowermost conductor layer of the conductor layers of the first and second internal electrodes do not directly contribute to obtain the desired capacitance, but are used to obtain the capacitance. It contributes to prevent the current based on the stray capacitance from flowing in the intermediate conductive layer, and further exerts an electromagnetic shield effect. In addition, the conductor layers of the internal electrodes are grouped in the central region as well, and a plurality (preferably two) of conductor layers are led out in the same direction, so that the current flowing in one conductor layer is determined based on the capacitance. It can be reduced to 1/2 and Q can be increased, that is, signal loss can be reduced.

【0007】[0007]

【実施例】次に、図1〜図3を参照して本発明の実施例
の積層コンデンサ10を説明する。この積層コンデンサ
10は、1MHzにおいて容量値Cが5.0pF、Qが
2000の材料から成るセラミック(磁器)誘電体1
と、第1及び第2の内部電極2、3と、第1及び第2の
外部電極4、5とを有する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a multilayer capacitor 10 according to an embodiment of the present invention will be described with reference to FIGS. This multilayer capacitor 10 is a ceramic (porcelain) dielectric 1 made of a material having a capacitance value C of 5.0 pF and a Q value of 2000 at 1 MHz.
And the first and second inner electrodes 2 and 3 and the first and second outer electrodes 4 and 5.

【0008】外部電極4、5の厚みが省略されて示され
ている図1から明らかなように、誘電体1は第1の主面
(上面)8aとこれに対向する第2の主面(下面)8b
と第1〜第4の側面9a、9b、9c、9dを有して全
体として直方体に形成されている。
As is apparent from FIG. 1 in which the thicknesses of the external electrodes 4 and 5 are omitted, the dielectric 1 has a first main surface (upper surface) 8a and a second main surface (the upper surface) 8a opposed thereto. Bottom) 8b
And it has the 1st-4th side surface 9a, 9b, 9c, 9d, and is formed in a rectangular parallelepiped as a whole.

【0009】第1及び第2の内部電極2、3が埋設され
た誘電体1は温度補償用誘電体磁器組成物から成るグリ
ーンシート(セラミック生シート)に導電性ペースト
(パラジウムペースト)を塗布したものを積層し、圧着
し、焼成することによって形成されている。図3に示す
ように幅広の帯状導体層から成る第1及び第2の内部電
極2、3は誘電体1の第1及び第2の第2の主面8a、
8bに対して平行に配置されている。
For the dielectric 1 in which the first and second internal electrodes 2 and 3 are buried, a conductive paste (palladium paste) is applied to a green sheet (ceramic green sheet) made of a temperature-compensating dielectric ceramic composition. It is formed by stacking things, pressing them, and baking them. As shown in FIG. 3, the first and second internal electrodes 2 and 3 made of wide strip-shaped conductor layers are the first and second main surfaces 8a of the dielectric body 1,
It is arranged parallel to 8b.

【0010】第1及び第2の内部電極2、3はそれぞれ
複数の導体層から成り、これ等は隣り合う2層が同一側
面に導出されるようにグループ化されている。即ち第1
及び第2の内部電極2、3が2層ずつ交互に第1の側面
9cと第2の側面9dとに導出されている。第1の外部
電極4は第1の側面9aにて第1の内部電極2に接続さ
れ、誘電体1の左端部において第1、第3及び第4の側
面9a、9c、9dと第1及び第2の主面8a、8bと
を覆うように導体膜で形成されている。第2の外部電極
5は誘電体1の右端部において第2、第3及び第4の側
面9b、9c、9dと第1及び第2の主面8a、8bと
を覆うように導体膜で形成されている。
The first and second internal electrodes 2, 3 are each composed of a plurality of conductor layers, which are grouped so that two adjacent layers are led out to the same side surface. That is, the first
The second internal electrodes 2 and 3 are alternately led out to the first side face 9c and the second side face 9d by two layers. The first outer electrode 4 is connected to the first inner electrode 2 at the first side surface 9a, and the first, third and fourth side surfaces 9a, 9c, 9d and the first and second side surfaces 9a, 9c and 9d are provided at the left end of the dielectric 1. It is formed of a conductor film so as to cover the second main surfaces 8a and 8b. The second external electrode 5 is formed of a conductor film so as to cover the second, third and fourth side surfaces 9b, 9c and 9d and the first and second main surfaces 8a and 8b at the right end portion of the dielectric 1. Has been done.

【0011】第1及び第2の内部電極2、3を2つの導
体層毎にグループ化した効果を調べるために、積層コン
デンサ10の第1及び第2の外部電極4、5を図4に示
すように測定用基板20の配線導体21、22に半田付
けし、更に積層コンデンサ10の下にグランド配線導体
23を通し、ネットワークアナライザから成る測定器2
4を接続し、積層コンデンサ10の外部電極4,5間に
1GHz の交流信号を流して積層コンデンサ10のインピ
−ダンスZ=R+jXc (但し、Rは実数部、Xc は虚数
部)を測定し、Q即ち−Xc /Rを求めたところ、Qは
58であった。
The first and second outer electrodes 4, 5 of the multilayer capacitor 10 are shown in FIG. 4 in order to investigate the effect of grouping the first and second inner electrodes 2, 3 for every two conductor layers. As described above, the wiring conductors 21 and 22 of the measurement substrate 20 are soldered, and the ground wiring conductor 23 is further passed under the multilayer capacitor 10 to form a measuring device 2 including a network analyzer.
4 is connected, an AC signal of 1 GHz is passed between the external electrodes 4 and 5 of the multilayer capacitor 10, and the impedance Z = R + jXc (where R is a real part and Xc is an imaginary part) of the multilayer capacitor 10 is measured, When Q, i.e., -Xc / R, was determined, Q was 58.

【0012】比較のために図5の従来の積層コンデンサ
においても、実施例の積層コンデンサ10と同様な測定
を行ったところ、Qは40であった。また、図6の従来
の積層コンデンサにおいても実施例と同様な測定を行っ
たところ、Qは55であった。以上の測定結果から明ら
かなように、本実施例の構造とすることによって、図6
の構造と同様に内部電極2、3の電流密度を低減させる
効果を得ることができるのみでなく、グランド配線導体
23等の外部回路の影響を最も上及び最も下の内部電極
によって防ぎ、Qを高めることができる。
For comparison, in the conventional multilayer capacitor shown in FIG. 5, when the same measurement as that of the multilayer capacitor 10 of the example was carried out, Q was 40. Also, when the same measurement as in the example was performed on the conventional multilayer capacitor of FIG. 6, Q was 55. As is clear from the above measurement results, by adopting the structure of this embodiment, the structure shown in FIG.
Not only can the effect of reducing the current density of the internal electrodes 2 and 3 be obtained as in the structure of No. 1, but the influence of external circuits such as the ground wiring conductor 23 can be prevented by the uppermost and lowermost internal electrodes, and Q can be reduced. Can be increased.

【0013】また、内部電極2、3の最も上及び最も下
の導体層は、Qの低下(信号ロスの増大)を防ぐのみで
なく、ノイズ成分のコンデンサへの入り込みを防ぐこと
ができる。
Further, the uppermost and lowermost conductor layers of the internal electrodes 2 and 3 can prevent not only a decrease in Q (increase in signal loss) but also a noise component from entering the capacitor.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の積層コンデンサを概略的に示
す斜視図である。
FIG. 1 is a perspective view schematically showing a multilayer capacitor according to an embodiment of the present invention.

【図2】図1のA−A線に相当する部分を示す積層コン
デンサの断面図である。
FIG. 2 is a sectional view of the multilayer capacitor showing a portion corresponding to line AA in FIG.

【図3】図2のB−B線の断面図である。FIG. 3 is a sectional view taken along line BB of FIG.

【図4】積層コンデンサの特性測定装置を示す平面図で
ある。
FIG. 4 is a plan view showing a characteristic measuring device for a multilayer capacitor.

【図5】従来の積層コンデンサを示す断面図である。FIG. 5 is a sectional view showing a conventional multilayer capacitor.

【図6】別の従来の積層コンデンサを示す断面図であ
る。
FIG. 6 is a sectional view showing another conventional multilayer capacitor.

【符号の説明】[Explanation of symbols]

1 誘電体 2、3 内部電極 4、5 外部電極 1 Dielectric 2, 3 Internal electrode 4, 5 External electrode

フロントページの続き (72)発明者 増田 淳 東京都台東区上野6丁目16番20号 太陽誘 電株式会社内 (72)発明者 鳥羽 利一 東京都台東区上野6丁目16番20号 太陽誘 電株式会社内Front page continuation (72) Inventor Atsushi Masuda 6-16-20 Ueno, Taito-ku, Tokyo Within Taiyo Denki Co., Ltd. (72) Inventor Riichi Toba 6-16-20 Ueno, Taito-ku, Tokyo Solar induction Within the corporation

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1及び第2の主面と側面とを有する誘
電体と、前記誘電体に埋設された複数の導体層からなる
第1及び第2の内部電極と、前記誘電体の外周面に設け
られ且つ前記第1及び第2の内部電極に接続された第1
及び第2の外部電極とを有する積層セラミックコンデン
サにおいて、 前記第1の内部電極が複数の導体層毎に複数のグループ
に分割され、前記第2の内部電極も複数の導体層毎に複
数のグループに分割され、前記第1の内部電極の前記複
数のグループが交互に配置されていることを特徴とする
積層セラミックコンデンサ。
1. A dielectric having first and second main surfaces and side surfaces, first and second internal electrodes composed of a plurality of conductor layers embedded in the dielectric, and an outer periphery of the dielectric. A first surface provided on the surface and connected to the first and second internal electrodes
And a second external electrode, wherein the first inner electrode is divided into a plurality of groups for each of a plurality of conductor layers, and the second inner electrode is also a plurality of groups for each of a plurality of conductor layers. And a plurality of groups of the first internal electrodes are alternately arranged.
JP5157874A 1993-06-02 1993-06-02 Multilayered ceramic capacitor Withdrawn JPH06349666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5157874A JPH06349666A (en) 1993-06-02 1993-06-02 Multilayered ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5157874A JPH06349666A (en) 1993-06-02 1993-06-02 Multilayered ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH06349666A true JPH06349666A (en) 1994-12-22

Family

ID=15659301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5157874A Withdrawn JPH06349666A (en) 1993-06-02 1993-06-02 Multilayered ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH06349666A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004509451A (en) * 2000-04-28 2004-03-25 エクストゥーワイ、アテニュエイタズ、エル、エル、シー A predetermined symmetrically balanced mixture having a complementary pair of parts with a shielding electrode and a shielded electrode and a symmetrically balanced complementary energy part other predetermined element parts for conditioning;
JP2007005501A (en) * 2005-06-22 2007-01-11 Tdk Corp Capacitor element and non-reciprocal circuit element
JP2007043001A (en) * 2005-08-05 2007-02-15 Tdk Corp Method of manufacturing laminated capacitor
US7239500B2 (en) 2005-09-30 2007-07-03 Tdk Corporation Multilayer capacitor
US7688567B2 (en) 2005-08-05 2010-03-30 Tdk Corporation Method of manufacturing multilayer capacitor and multilayer capacitor
JP2011040581A (en) * 2009-08-11 2011-02-24 Sony Corp Capacitance element and resonance circuit
US20110149466A1 (en) * 2009-12-22 2011-06-23 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor
US8116064B2 (en) 2008-07-29 2012-02-14 Tdk Corporation Multilayer capacitor
JP2016111248A (en) * 2014-12-09 2016-06-20 Tdk株式会社 Multilayer ceramic capacitor
CN114078634A (en) * 2020-08-20 2022-02-22 株式会社村田制作所 Multilayer ceramic capacitor
JP2022191693A (en) * 2021-06-16 2022-12-28 株式会社村田製作所 Multilayer ceramic capacitor

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004509451A (en) * 2000-04-28 2004-03-25 エクストゥーワイ、アテニュエイタズ、エル、エル、シー A predetermined symmetrically balanced mixture having a complementary pair of parts with a shielding electrode and a shielded electrode and a symmetrically balanced complementary energy part other predetermined element parts for conditioning;
JP2007005501A (en) * 2005-06-22 2007-01-11 Tdk Corp Capacitor element and non-reciprocal circuit element
JP2007043001A (en) * 2005-08-05 2007-02-15 Tdk Corp Method of manufacturing laminated capacitor
US7688567B2 (en) 2005-08-05 2010-03-30 Tdk Corporation Method of manufacturing multilayer capacitor and multilayer capacitor
JP4539489B2 (en) * 2005-08-05 2010-09-08 Tdk株式会社 Manufacturing method of multilayer capacitor
US7828033B2 (en) 2005-08-05 2010-11-09 Tdk Corporation Method of manufacturing multilayer capacitor and multilayer capacitor
US7239500B2 (en) 2005-09-30 2007-07-03 Tdk Corporation Multilayer capacitor
US8116064B2 (en) 2008-07-29 2012-02-14 Tdk Corporation Multilayer capacitor
JP2011040581A (en) * 2009-08-11 2011-02-24 Sony Corp Capacitance element and resonance circuit
US20110149466A1 (en) * 2009-12-22 2011-06-23 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor
JP2016111248A (en) * 2014-12-09 2016-06-20 Tdk株式会社 Multilayer ceramic capacitor
CN114078634A (en) * 2020-08-20 2022-02-22 株式会社村田制作所 Multilayer ceramic capacitor
KR20220023291A (en) * 2020-08-20 2022-03-02 가부시키가이샤 무라타 세이사쿠쇼 Multilayer ceramic capacitor
JP2022035385A (en) * 2020-08-20 2022-03-04 株式会社村田製作所 Multilayer ceramic capacitor
US11972903B2 (en) 2020-08-20 2024-04-30 Murata Manufacturing Co., Ltd. Multilayer ceramic capacitor
CN114078634B (en) * 2020-08-20 2024-05-07 株式会社村田制作所 Laminated ceramic capacitor
JP2022191693A (en) * 2021-06-16 2022-12-28 株式会社村田製作所 Multilayer ceramic capacitor
US12073997B2 (en) 2021-06-16 2024-08-27 Murata Manufacturing Co., Ltd. Multilayer ceramic capacitor

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