JP2006527429A - 自動回路設計のための方法および装置 - Google Patents

自動回路設計のための方法および装置 Download PDF

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JP2006527429A
JP2006527429A JP2006515054A JP2006515054A JP2006527429A JP 2006527429 A JP2006527429 A JP 2006527429A JP 2006515054 A JP2006515054 A JP 2006515054A JP 2006515054 A JP2006515054 A JP 2006515054A JP 2006527429 A JP2006527429 A JP 2006527429A
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design
circuit design
circuit
path
implementation
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JP2006527429A5 (enExample
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ラマチャンドラン，シャンパカ
クルーズ，アンドリュー
マックエルバイン，ケネス・エス
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シンプリシティ・インコーポレーテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/08—Probabilistic or stochastic CAD
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2006515054A 2003-05-30 2004-05-28 自動回路設計のための方法および装置 Pending JP2006527429A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US47505903P 2003-05-30 2003-05-30
US10/850,808 US7178118B2 (en) 2003-05-30 2004-05-21 Method and apparatus for automated circuit design
PCT/US2004/017207 WO2004109562A1 (en) 2003-05-30 2004-05-28 Method and apparatus for automated circuit design

Related Child Applications (1)

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JP2011002374A Division JP5197770B2 (ja) 2003-05-30 2011-01-07 回路設計ツール

Publications (2)

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JP2006527429A true JP2006527429A (ja) 2006-11-30
JP2006527429A5 JP2006527429A5 (enExample) 2007-07-19

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JP2006515054A Pending JP2006527429A (ja) 2003-05-30 2004-05-28 自動回路設計のための方法および装置
JP2011002374A Expired - Lifetime JP5197770B2 (ja) 2003-05-30 2011-01-07 回路設計ツール

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JP2011002374A Expired - Lifetime JP5197770B2 (ja) 2003-05-30 2011-01-07 回路設計ツール

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US (3) US7178118B2 (enExample)
EP (2) EP2275958A3 (enExample)
JP (2) JP2006527429A (enExample)
WO (1) WO2004109562A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012053703A (ja) * 2010-09-01 2012-03-15 Fujitsu Ltd 最適化ネットリスト作成プログラム、最適化ネットリスト作成装置および最適化ネットリスト作成方法

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6876940B2 (en) * 2003-07-17 2005-04-05 Texas Instruments Incorporated Measuring constraint parameters at different combinations of circuit parameters
EP1683189A4 (en) * 2003-11-06 2008-08-06 Clear Shape Technologies Inc DELTA GEOMETRY TIMING PREDICTION IN THE MANUFACTURE OF INTEGRATED CIRCUITS
US7356784B1 (en) * 2003-12-05 2008-04-08 Cadence Design Systems, Inc. Integrated synthesis placement and routing for integrated circuits
WO2005119441A2 (en) * 2004-06-01 2005-12-15 Tera Systems, Inc. Methods and systems for structured asic eletronic design automation
US7487486B2 (en) * 2004-06-17 2009-02-03 Mustafa Celik Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations
US7401307B2 (en) * 2004-11-03 2008-07-15 International Business Machines Corporation Slack sensitivity to parameter variation based timing analysis
JP2006268479A (ja) * 2005-03-24 2006-10-05 Fujitsu Ltd 設計支援装置、設計支援方法、設計支援プログラム、および記録媒体
US7752588B2 (en) * 2005-06-29 2010-07-06 Subhasis Bose Timing driven force directed placement flow
EP1907957A4 (en) * 2005-06-29 2013-03-20 Otrsotech Ltd Liability Company INVESTMENT METHODS AND SYSTEMS
US7325215B2 (en) * 2005-08-31 2008-01-29 Lsi Logic Corporation Timing violation debugging inside place and route tool
JP4275659B2 (ja) * 2005-09-26 2009-06-10 富士通株式会社 遅延解析プログラム、遅延解析装置、および遅延解析方法
US7657859B2 (en) * 2005-12-08 2010-02-02 International Business Machines Corporation Method for IC wiring yield optimization, including wire widening during and after routing
US8332793B2 (en) * 2006-05-18 2012-12-11 Otrsotech, Llc Methods and systems for placement and routing
US7996797B1 (en) 2006-08-16 2011-08-09 Altera Corporation Method and apparatus for performing multiple stage physical synthesis
US8127260B1 (en) * 2006-11-22 2012-02-28 Cadence Design Systems, Inc. Physical layout estimator
KR20090068569A (ko) * 2007-12-24 2009-06-29 주식회사 동부하이텍 반도체 소자의 테스트 패턴 및 테스트 패턴 형성 방법
US7996812B2 (en) * 2008-08-14 2011-08-09 International Business Machines Corporation Method of minimizing early-mode violations causing minimum impact to a chip design
US8024693B2 (en) * 2008-11-04 2011-09-20 Synopsys, Inc. Congestion optimization during synthesis
US20100257499A1 (en) * 2009-04-02 2010-10-07 International Business Machines Corporation Techniques for fast area-efficient incremental physical synthesis
JP5397083B2 (ja) * 2009-08-17 2014-01-22 富士通株式会社 回路設計支援方法、回路設計支援装置および回路設計支援プログラム
US8429589B2 (en) * 2009-09-08 2013-04-23 Synopsys, Inc. Generating net routing constraints for place and route
US8336015B2 (en) * 2009-09-08 2012-12-18 Synopsys, Inc. Pre-route and post-route net correlation with defined patterns
US8108821B2 (en) * 2010-01-12 2012-01-31 International Business Machines Corporation Reduction of logic and delay through latch polarity inversion
US8782577B2 (en) 2010-07-24 2014-07-15 Cadence Design Systems, Inc. Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness
US8694950B2 (en) 2010-07-24 2014-04-08 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness
US8386985B2 (en) 2011-05-06 2013-02-26 International Business Machines Corporation Timing driven routing in integrated circuit design
US8584070B2 (en) * 2011-10-04 2013-11-12 International Business Machines Corporation Evaluating routing congestion based on average global edge congestion histograms
US8694943B1 (en) 2011-12-30 2014-04-08 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness
US8645902B1 (en) 2011-12-30 2014-02-04 Cadence Design Systems, Inc. Methods, systems, and computer program products for implementing interactive coloring of physical design components in a physical electronic design with multiple-patterning techniques awareness
US9064063B1 (en) * 2011-12-30 2015-06-23 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints
US8595662B1 (en) 2011-12-30 2013-11-26 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing a physical design of an electronic circuit with automatic snapping
US9053289B1 (en) 2012-04-12 2015-06-09 Cadence Design Systems, Inc. Method and system for implementing an improved interface for designing electronic layouts
US8640075B2 (en) 2012-06-01 2014-01-28 International Business Machines Corporation Early design cycle optimzation
WO2014064650A2 (en) * 2012-10-25 2014-05-01 Tiwari Satish Chandra Method and system for automated design of an integrated circuit using configurable cells
US8959467B2 (en) * 2012-11-07 2015-02-17 Lsi Corporation Structural rule analysis with TCL scripts in synthesis or STA tools and integrated circuit design tools
US9087172B2 (en) 2013-10-07 2015-07-21 International Business Machines Corporation Implementing enhanced net routing congestion resolution of non-rectangular or rectangular hierarchical macros
US9483597B1 (en) * 2015-03-24 2016-11-01 Xilinx, Inc. Opportunistic candidate path selection during physical optimization of a circuit design for an IC
US10169517B2 (en) 2016-03-29 2019-01-01 Wipro Limited Methods and systems for reducing congestion in very large scale integrated (VLSI) chip design
US10970445B2 (en) * 2017-06-28 2021-04-06 Intel Corporation Methods and apparatus for performing timing driven hardware emulation
SG11202004147RA (en) * 2017-11-09 2020-06-29 Nchain Holdings Ltd System for securing verification key from alteration and verifying validity of a proof of correctness
US10586005B1 (en) 2018-03-21 2020-03-10 Xilinx, Inc. Incremental synthesis for changes to a circuit design
US10831971B1 (en) * 2019-06-05 2020-11-10 International Business Machines Corporation Net layer promotion with swap capability in electronic design
US12175176B2 (en) * 2021-03-17 2024-12-24 Synopsys, Inc. Fast synthesis of logical circuit design with predictive timing
CN114118358B (zh) * 2021-10-15 2025-10-21 阿里巴巴（中国）有限公司 图像处理方法、装置、电子设备、介质及程序产品

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04104374A (ja) * 1990-08-24 1992-04-06 Hitachi Ltd 実装設計チェック方法
JPH06180733A (ja) * 1992-12-11 1994-06-28 Toshiba Corp 論理合成システム
JPH09232436A (ja) * 1996-02-22 1997-09-05 Fujitsu Ltd 論理合成方法及び装置並びに半導体集積回路設計方法
JPH10125790A (ja) * 1996-10-17 1998-05-15 Matsushita Electric Ind Co Ltd ブロック間配線推定方法
JP2000076321A (ja) * 1998-09-03 2000-03-14 Nec Ic Microcomput Syst Ltd 機能ブロックのモデル作成によるｌｓｉ設計システム及びそのｌｓｉ設計方法
JP2000223578A (ja) * 1999-02-03 2000-08-11 Nec Corp 半導体集積回路の配線方法

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US655338A (en) * 1898-04-11 1900-08-07 Denis Gale Apparatus for separating solid bodies from liquids.
US5257201A (en) * 1987-03-20 1993-10-26 International Business Machines Corporation Method to efficiently reduce the number of connections in a circuit
JP2679500B2 (ja) * 1990-12-17 1997-11-19 モトローラ・インコーポレイテッド 総合的なシステム歩留りを計算するための方法
US5381524B2 (en) * 1991-11-12 1997-07-08 Chronology Corp Automated development of timing diagrams for electrical circuits
US5301118A (en) * 1991-11-18 1994-04-05 International Business Machines Corporation Monte carlo simulation design methodology
JP3219500B2 (ja) * 1991-12-27 2001-10-15 株式会社東芝 自動配線方法
US5418974A (en) * 1992-10-08 1995-05-23 International Business Machines Corporation Circuit design method and system therefor
US5666290A (en) * 1995-12-27 1997-09-09 Vlsi Technology, Inc. Interactive time-driven method of component placement that more directly constrains critical paths using net-based constraints
JPH09198419A (ja) * 1996-01-22 1997-07-31 Toshiba Corp 半導体装置の設計方法及び設計装置
JP2874628B2 (ja) * 1996-01-30 1999-03-24 日本電気株式会社 論理回路の最適化装置及びその方法
US5663891A (en) * 1996-04-03 1997-09-02 Cadence Design Systems, Inc. Optimization of multiple performance criteria of integrated circuits by expanding a constraint graph with subgraphs derived from multiple PWL convex cost functions
US5787008A (en) * 1996-04-10 1998-07-28 Motorola, Inc. Simulation corrected sensitivity
US5696771A (en) * 1996-05-17 1997-12-09 Synopsys, Inc. Method and apparatus for performing partial unscan and near full scan within design for test applications
US5978572A (en) * 1996-08-21 1999-11-02 Matsushita Electric Industrial Co., Ltd. LSI wire length estimation and area estimation
JPH10163330A (ja) * 1996-12-03 1998-06-19 Nec Corp レイアウト考慮遅延最適化装置および方法
JPH10223763A (ja) * 1997-02-12 1998-08-21 Fujitsu Ltd セル配置最適化処理方法および装置
US5999714A (en) * 1997-03-27 1999-12-07 International Business Machines Corporation Method for incorporating noise considerations in automatic circuit optimization
US6145117A (en) * 1998-01-30 2000-11-07 Tera Systems Incorporated Creating optimized physical implementations from high-level descriptions of electronic design using placement based information
US6286128B1 (en) * 1998-02-11 2001-09-04 Monterey Design Systems, Inc. Method for design optimization using logical and physical information
BR9914200A (pt) * 1998-09-30 2002-01-22 Cadence Design Systems Inc Métodos para projetar um sistema de circuito, para expandir uma metodologia existente para avaliar a viabilidade de um projeto de circuito, para realizar uma avaliação de viabilidade para um projeto de circuito, para refinar uma primeira regra de decisão para um projeto de circuito, para formar uma segunda regra de decisão para um projeto de circuito, para organizar os dados de experiência de um projetista relativos a uma pluralidade de blocos de circuito pré-projetados, para aumentar a eficiência de distribuição de lógica de cola e para distribuir uma pluralidade de elementos lógicos de cola entre os blocos de projeto e distribuir lógica de cola para execução em um esquema de projeto de dispositivo de circuito integrado, para converter uma interface especìfica de um bloco de circuito, para selecionar um coletor de circuito, para projetar um dispositivo que incorpora o projeto e habilitar um teste do dispositivo, para verificar o correto funcionamento de um projeto de circuito e para desenvolver uma bancada de teste de nìvel comportamental, interface de colar e sistema de interface
US7017043B1 (en) * 1999-03-19 2006-03-21 The Regents Of The University Of California Methods and systems for the identification of circuits and circuit designs
US6553338B1 (en) * 1999-04-27 2003-04-22 Magma Design Automation, Inc. Timing optimization in presence of interconnect delays
US6993456B2 (en) * 1999-09-30 2006-01-31 Rockwell Automation Technologies, Inc. Mechanical-electrical template based method and apparatus
US6543036B1 (en) * 1999-11-30 2003-04-01 Synopsys, Inc. Non-linear, gain-based modeling of circuit delay for an electronic design automation system
US20020029370A1 (en) * 2000-04-20 2002-03-07 Zbigniew Michalewicz Test case generator
US6453451B1 (en) * 2000-10-02 2002-09-17 Lsi Logic Corporation Generating standard delay format files with conditional path delay for designing integrated circuits
US6532577B1 (en) * 2001-06-27 2003-03-11 Lsi Logic Corporation Timing driven interconnect analysis
US6618846B2 (en) * 2001-08-31 2003-09-09 Synopsys, Inc. Estimating capacitance effects in integrated circuits using congestion estimations
US6807655B1 (en) * 2002-05-17 2004-10-19 Lsi Logic Corporation Adaptive off tester screening method based on intrinsic die parametric measurements
US6826733B2 (en) * 2002-05-30 2004-11-30 International Business Machines Corporation Parameter variation tolerant method for circuit design optimization
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
WO2003104921A2 (en) * 2002-06-07 2003-12-18 Praesagus, Inc. Characterization adn reduction of variation for integrated circuits
US6854685B2 (en) * 2002-07-09 2005-02-15 Sonoco Development, Inc. Yarn dye tube having opposite end portions adapted for nested stacking
US7000684B2 (en) 2002-11-01 2006-02-21 Cooligy, Inc. Method and apparatus for efficient vertical fluid delivery for cooling a heat producing device
WO2004061898A2 (en) * 2003-01-02 2004-07-22 Pdf Solutions, Inc. Yield improvement
US20040236560A1 (en) * 2003-05-23 2004-11-25 Chen Thomas W. Power estimation using functional verification
US7251800B2 (en) * 2003-05-30 2007-07-31 Synplicity, Inc. Method and apparatus for automated circuit design
US7111260B2 (en) * 2003-09-18 2006-09-19 International Business Machines Corporation System and method for incremental statistical timing analysis of digital circuits

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04104374A (ja) * 1990-08-24 1992-04-06 Hitachi Ltd 実装設計チェック方法
JPH06180733A (ja) * 1992-12-11 1994-06-28 Toshiba Corp 論理合成システム
JPH09232436A (ja) * 1996-02-22 1997-09-05 Fujitsu Ltd 論理合成方法及び装置並びに半導体集積回路設計方法
JPH10125790A (ja) * 1996-10-17 1998-05-15 Matsushita Electric Ind Co Ltd ブロック間配線推定方法
JP2000076321A (ja) * 1998-09-03 2000-03-14 Nec Ic Microcomput Syst Ltd 機能ブロックのモデル作成によるｌｓｉ設計システム及びそのｌｓｉ設計方法
JP2000223578A (ja) * 1999-02-03 2000-08-11 Nec Corp 半導体集積回路の配線方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012053703A (ja) * 2010-09-01 2012-03-15 Fujitsu Ltd 最適化ネットリスト作成プログラム、最適化ネットリスト作成装置および最適化ネットリスト作成方法

Also Published As

Publication number Publication date
WO2004109562A1 (en) 2004-12-16
US7178118B2 (en) 2007-02-13
US8990743B2 (en) 2015-03-24
EP2275958A2 (en) 2011-01-19
JP2011103133A (ja) 2011-05-26
JP5197770B2 (ja) 2013-05-15
US8151228B2 (en) 2012-04-03
US20120185811A1 (en) 2012-07-19
US20040243953A1 (en) 2004-12-02
US20070089074A1 (en) 2007-04-19
EP2275958A3 (en) 2011-04-27
EP1629409A1 (en) 2006-03-01

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