JP2006527429A - 自動回路設計のための方法および装置 - Google Patents

自動回路設計のための方法および装置 Download PDF

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JP2006527429A
JP2006527429A JP2006515054A JP2006515054A JP2006527429A JP 2006527429 A JP2006527429 A JP 2006527429A JP 2006515054 A JP2006515054 A JP 2006515054A JP 2006515054 A JP2006515054 A JP 2006515054A JP 2006527429 A JP2006527429 A JP 2006527429A
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design
circuit design
circuit
path
implementation
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JP2006527429A5 (cg-RX-API-DMAC7.html
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ラマチャンドラン，シャンパカ
クルーズ，アンドリュー
マックエルバイン，ケネス・エス
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シンプリシティ・インコーポレーテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/08—Probabilistic or stochastic CAD
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2006515054A 2003-05-30 2004-05-28 自動回路設計のための方法および装置 Pending JP2006527429A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US47505903P 2003-05-30 2003-05-30
US10/850,808 US7178118B2 (en) 2003-05-30 2004-05-21 Method and apparatus for automated circuit design
PCT/US2004/017207 WO2004109562A1 (en) 2003-05-30 2004-05-28 Method and apparatus for automated circuit design

Related Child Applications (1)

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JP2011002374A Division JP5197770B2 (ja) 2003-05-30 2011-01-07 回路設計ツール

Publications (2)

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JP2006527429A true JP2006527429A (ja) 2006-11-30
JP2006527429A5 JP2006527429A5 (cg-RX-API-DMAC7.html) 2007-07-19

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JP2006515054A Pending JP2006527429A (ja) 2003-05-30 2004-05-28 自動回路設計のための方法および装置
JP2011002374A Expired - Lifetime JP5197770B2 (ja) 2003-05-30 2011-01-07 回路設計ツール

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JP2011002374A Expired - Lifetime JP5197770B2 (ja) 2003-05-30 2011-01-07 回路設計ツール

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US (3) US7178118B2 (cg-RX-API-DMAC7.html)
EP (2) EP1629409A1 (cg-RX-API-DMAC7.html)
JP (2) JP2006527429A (cg-RX-API-DMAC7.html)
WO (1) WO2004109562A1 (cg-RX-API-DMAC7.html)

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Publication number Priority date Publication date Assignee Title
JP2012053703A (ja) * 2010-09-01 2012-03-15 Fujitsu Ltd 最適化ネットリスト作成プログラム、最適化ネットリスト作成装置および最適化ネットリスト作成方法

Also Published As

Publication number Publication date
EP2275958A2 (en) 2011-01-19
JP5197770B2 (ja) 2013-05-15
US8990743B2 (en) 2015-03-24
JP2011103133A (ja) 2011-05-26
US7178118B2 (en) 2007-02-13
WO2004109562A1 (en) 2004-12-16
US8151228B2 (en) 2012-04-03
US20040243953A1 (en) 2004-12-02
EP1629409A1 (en) 2006-03-01
US20070089074A1 (en) 2007-04-19
US20120185811A1 (en) 2012-07-19
EP2275958A3 (en) 2011-04-27

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