JP2006520956A5 - - Google Patents

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Publication number
JP2006520956A5
JP2006520956A5 JP2006506673A JP2006506673A JP2006520956A5 JP 2006520956 A5 JP2006520956 A5 JP 2006520956A5 JP 2006506673 A JP2006506673 A JP 2006506673A JP 2006506673 A JP2006506673 A JP 2006506673A JP 2006520956 A5 JP2006520956 A5 JP 2006520956A5
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JP
Japan
Prior art keywords
bus
data
data processing
processing apparatus
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006506673A
Other languages
English (en)
Japanese (ja)
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JP2006520956A (ja
JP4892683B2 (ja
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Publication date
Application filed filed Critical
Priority claimed from PCT/IB2004/050197 external-priority patent/WO2004081803A1/en
Publication of JP2006520956A publication Critical patent/JP2006520956A/ja
Publication of JP2006520956A5 publication Critical patent/JP2006520956A5/ja
Application granted granted Critical
Publication of JP4892683B2 publication Critical patent/JP4892683B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2006506673A 2003-03-12 2004-03-03 データを転送するためのデータ処理の装置および方法 Expired - Fee Related JP4892683B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP03100629 2003-03-12
EP03100629.9 2003-03-12
PCT/IB2004/050197 WO2004081803A1 (en) 2003-03-12 2004-03-03 Data processing device and method for transferring data

Publications (3)

Publication Number Publication Date
JP2006520956A JP2006520956A (ja) 2006-09-14
JP2006520956A5 true JP2006520956A5 (enExample) 2007-04-26
JP4892683B2 JP4892683B2 (ja) 2012-03-07

Family

ID=32981918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006506673A Expired - Fee Related JP4892683B2 (ja) 2003-03-12 2004-03-03 データを転送するためのデータ処理の装置および方法

Country Status (5)

Country Link
US (1) US7340553B2 (enExample)
EP (1) EP1604288A1 (enExample)
JP (1) JP4892683B2 (enExample)
CN (1) CN100520754C (enExample)
WO (1) WO2004081803A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4437464B2 (ja) * 2005-06-01 2010-03-24 株式会社ルネサステクノロジ 半導体装置及びデータ処理システム
JP4224080B2 (ja) * 2006-06-05 2009-02-12 フェリカネットワークス株式会社 情報処理端末およびそのプログラム
US8271827B2 (en) * 2007-12-10 2012-09-18 Qimonda Memory system with extended memory density capability
US7895380B2 (en) * 2009-01-21 2011-02-22 Ati Technologies Ulc Communication protocol for sharing memory resources between components of a device
US8631256B2 (en) 2010-12-22 2014-01-14 Via Technologies, Inc. Distributed management of a shared power source to a multi-core microprocessor
US8637212B2 (en) 2010-12-22 2014-01-28 Via Technologies, Inc. Reticle set modification to produce multi-core dies
US8972707B2 (en) 2010-12-22 2015-03-03 Via Technologies, Inc. Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin
US8782451B2 (en) 2010-12-22 2014-07-15 Via Technologies, Inc. Power state synchronization in a multi-core processor
US8930676B2 (en) 2010-12-22 2015-01-06 Via Technologies, Inc. Master core discovering enabled cores in microprocessor comprising plural multi-core dies
US9460038B2 (en) * 2010-12-22 2016-10-04 Via Technologies, Inc. Multi-core microprocessor internal bypass bus

Family Cites Families (20)

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Publication number Priority date Publication date Assignee Title
US5193204A (en) * 1984-03-06 1993-03-09 Codex Corporation Processor interface circuitry for effecting data transfers between processors
US4932040A (en) * 1987-12-07 1990-06-05 Bull Hn Information Systems Inc. Bidirectional control signalling bus interface apparatus for transmitting signals between two bus systems
CA2080210C (en) * 1992-01-02 1998-10-27 Nader Amini Bidirectional data storage facility for bus interface unit
JPH064458A (ja) * 1992-06-18 1994-01-14 Fuji Xerox Co Ltd Ｄｍａ制御装置
US5335326A (en) * 1992-10-01 1994-08-02 Xerox Corporation Multichannel FIFO device channel sequencer
FR2699706B1 (fr) * 1992-12-22 1995-02-24 Bull Sa Système de transmission de données entre un bus d'ordinateur et un réseau.
US5761450A (en) * 1994-02-24 1998-06-02 Intel Corporation Bus bridge circuit flushing buffer to a bus during one acquire/relinquish cycle by providing empty address indications
US5835742A (en) * 1994-06-14 1998-11-10 Apple Computer, Inc. System and method for executing indivisible memory operations in multiple processor computer systems with multiple busses
US5627975A (en) * 1994-08-02 1997-05-06 Motorola, Inc. Interbus buffer for use between a pseudo little endian bus and a true little endian bus
US5916296A (en) * 1995-06-05 1999-06-29 Nippondenso Co., Ltd. Dual processor automotive control system having flexible processor standardization
US6279087B1 (en) * 1997-12-22 2001-08-21 Compaq Computer Corporation System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations
US6212590B1 (en) * 1997-12-22 2001-04-03 Compaq Computer Corporation Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base
US6199127B1 (en) * 1997-12-24 2001-03-06 Intel Corporation Method and apparatus for throttling high priority memory accesses
US6298407B1 (en) * 1998-03-04 2001-10-02 Intel Corporation Trigger points for performance optimization in bus-to-bus bridges
JP2000076180A (ja) * 1998-08-28 2000-03-14 Nec Corp バス接続装置及び情報処理システム
US6405276B1 (en) * 1998-12-10 2002-06-11 International Business Machines Corporation Selectively flushing buffered transactions in a bus bridge
US6253268B1 (en) * 1999-01-15 2001-06-26 Telefonaktiebolaget L M Ericsson (Publ) Method and system for multiplexing a second interface on an I2C interface
US6266723B1 (en) * 1999-03-29 2001-07-24 Lsi Logic Corporation Method and system for optimizing of peripheral component interconnect PCI bus transfers
US6715023B1 (en) * 1999-09-23 2004-03-30 Altera Corporation PCI bus switch architecture
US6996659B2 (en) * 2002-07-30 2006-02-07 Lsi Logic Corporation Generic bridge core

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