CN100520754C - 用于传送数据的数据处理设备以及方法 - Google Patents

用于传送数据的数据处理设备以及方法 Download PDF

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Publication number
CN100520754C
CN100520754C CNB2004800064385A CN200480006438A CN100520754C CN 100520754 C CN100520754 C CN 100520754C CN B2004800064385 A CNB2004800064385 A CN B2004800064385A CN 200480006438 A CN200480006438 A CN 200480006438A CN 100520754 C CN100520754 C CN 100520754C
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CN
China
Prior art keywords
bus
data
control module
bus master
processing equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004800064385A
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English (en)
Chinese (zh)
Other versions
CN1759385A (zh
Inventor
H·-J·格尔克
S·M·科赫
A·雷丁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
NXP BV
Koninklijke Philips Electronics NV
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Publication of CN1759385A publication Critical patent/CN1759385A/zh
Application granted granted Critical
Publication of CN100520754C publication Critical patent/CN100520754C/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
CNB2004800064385A 2003-03-12 2004-03-03 用于传送数据的数据处理设备以及方法 Expired - Fee Related CN100520754C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03100629 2003-03-12
EP03100629.9 2003-03-12

Publications (2)

Publication Number Publication Date
CN1759385A CN1759385A (zh) 2006-04-12
CN100520754C true CN100520754C (zh) 2009-07-29

Family

ID=32981918

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800064385A Expired - Fee Related CN100520754C (zh) 2003-03-12 2004-03-03 用于传送数据的数据处理设备以及方法

Country Status (5)

Country Link
US (1) US7340553B2 (enExample)
EP (1) EP1604288A1 (enExample)
JP (1) JP4892683B2 (enExample)
CN (1) CN100520754C (enExample)
WO (1) WO2004081803A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4437464B2 (ja) * 2005-06-01 2010-03-24 株式会社ルネサステクノロジ 半導体装置及びデータ処理システム
JP4224080B2 (ja) * 2006-06-05 2009-02-12 フェリカネットワークス株式会社 情報処理端末およびそのプログラム
US8271827B2 (en) * 2007-12-10 2012-09-18 Qimonda Memory system with extended memory density capability
US7895380B2 (en) * 2009-01-21 2011-02-22 Ati Technologies Ulc Communication protocol for sharing memory resources between components of a device
US8631256B2 (en) 2010-12-22 2014-01-14 Via Technologies, Inc. Distributed management of a shared power source to a multi-core microprocessor
US8637212B2 (en) 2010-12-22 2014-01-28 Via Technologies, Inc. Reticle set modification to produce multi-core dies
US8972707B2 (en) 2010-12-22 2015-03-03 Via Technologies, Inc. Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin
US8782451B2 (en) 2010-12-22 2014-07-15 Via Technologies, Inc. Power state synchronization in a multi-core processor
US8930676B2 (en) 2010-12-22 2015-01-06 Via Technologies, Inc. Master core discovering enabled cores in microprocessor comprising plural multi-core dies
US9460038B2 (en) * 2010-12-22 2016-10-04 Via Technologies, Inc. Multi-core microprocessor internal bypass bus

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1036466A (zh) * 1987-12-07 1989-10-18 霍内韦尔布尔公司 在两个总线系统间传送信号的双向控制信号总线接口装置
US5335326A (en) * 1992-10-01 1994-08-02 Xerox Corporation Multichannel FIFO device channel sequencer
US5644729A (en) * 1992-01-02 1997-07-01 International Business Machines Corporation Bidirectional data buffer for a bus-to-bus interface unit in a computer system
CN1333964A (zh) * 1999-01-15 2002-01-30 艾利森电话股份有限公司 接口交错

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US5193204A (en) * 1984-03-06 1993-03-09 Codex Corporation Processor interface circuitry for effecting data transfers between processors
JPH064458A (ja) * 1992-06-18 1994-01-14 Fuji Xerox Co Ltd Ｄｍａ制御装置
FR2699706B1 (fr) * 1992-12-22 1995-02-24 Bull Sa Système de transmission de données entre un bus d'ordinateur et un réseau.
US5761450A (en) * 1994-02-24 1998-06-02 Intel Corporation Bus bridge circuit flushing buffer to a bus during one acquire/relinquish cycle by providing empty address indications
US5835742A (en) * 1994-06-14 1998-11-10 Apple Computer, Inc. System and method for executing indivisible memory operations in multiple processor computer systems with multiple busses
US5627975A (en) * 1994-08-02 1997-05-06 Motorola, Inc. Interbus buffer for use between a pseudo little endian bus and a true little endian bus
US5916296A (en) * 1995-06-05 1999-06-29 Nippondenso Co., Ltd. Dual processor automotive control system having flexible processor standardization
US6279087B1 (en) * 1997-12-22 2001-08-21 Compaq Computer Corporation System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations
US6212590B1 (en) * 1997-12-22 2001-04-03 Compaq Computer Corporation Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base
US6199127B1 (en) * 1997-12-24 2001-03-06 Intel Corporation Method and apparatus for throttling high priority memory accesses
US6298407B1 (en) * 1998-03-04 2001-10-02 Intel Corporation Trigger points for performance optimization in bus-to-bus bridges
JP2000076180A (ja) * 1998-08-28 2000-03-14 Nec Corp バス接続装置及び情報処理システム
US6405276B1 (en) * 1998-12-10 2002-06-11 International Business Machines Corporation Selectively flushing buffered transactions in a bus bridge
US6266723B1 (en) * 1999-03-29 2001-07-24 Lsi Logic Corporation Method and system for optimizing of peripheral component interconnect PCI bus transfers
US6715023B1 (en) * 1999-09-23 2004-03-30 Altera Corporation PCI bus switch architecture
US6996659B2 (en) * 2002-07-30 2006-02-07 Lsi Logic Corporation Generic bridge core

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1036466A (zh) * 1987-12-07 1989-10-18 霍内韦尔布尔公司 在两个总线系统间传送信号的双向控制信号总线接口装置
US5644729A (en) * 1992-01-02 1997-07-01 International Business Machines Corporation Bidirectional data buffer for a bus-to-bus interface unit in a computer system
US5335326A (en) * 1992-10-01 1994-08-02 Xerox Corporation Multichannel FIFO device channel sequencer
CN1333964A (zh) * 1999-01-15 2002-01-30 艾利森电话股份有限公司 接口交错

Also Published As

Publication number Publication date
WO2004081803A1 (en) 2004-09-23
JP2006520956A (ja) 2006-09-14
JP4892683B2 (ja) 2012-03-07
CN1759385A (zh) 2006-04-12
US20060224809A1 (en) 2006-10-05
EP1604288A1 (en) 2005-12-14
US7340553B2 (en) 2008-03-04

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SE01 Entry into force of request for substantive examination
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Owner name: NXP CO., LTD.

Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V.

Effective date: 20071102

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Effective date of registration: 20071102

Address after: Holland Ian Deho Finn

Applicant after: Koninkl Philips Electronics NV

Address before: Holland Ian Deho Finn

Applicant before: Koninklijke Philips Electronics N.V.

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GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090729

Termination date: 20180303

CF01 Termination of patent right due to non-payment of annual fee