JP4892683B2 - データを転送するためのデータ処理の装置および方法 - Google Patents

データを転送するためのデータ処理の装置および方法 Download PDF

Info

Publication number
JP4892683B2
JP4892683B2 JP2006506673A JP2006506673A JP4892683B2 JP 4892683 B2 JP4892683 B2 JP 4892683B2 JP 2006506673 A JP2006506673 A JP 2006506673A JP 2006506673 A JP2006506673 A JP 2006506673A JP 4892683 B2 JP4892683 B2 JP 4892683B2
Authority
JP
Japan
Prior art keywords
bus
data
master
control unit
processing apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006506673A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006520956A (ja
JP2006520956A5 (enExample
Inventor
ハンス‐ヨアヒム、ゲルケ
シュテファン、マルコ、コッホ
アントン、レディング
Original Assignee
エスティー‐エリクソン、ソシエテ、アノニム
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エスティー‐エリクソン、ソシエテ、アノニム filed Critical エスティー‐エリクソン、ソシエテ、アノニム
Publication of JP2006520956A publication Critical patent/JP2006520956A/ja
Publication of JP2006520956A5 publication Critical patent/JP2006520956A5/ja
Application granted granted Critical
Publication of JP4892683B2 publication Critical patent/JP4892683B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP2006506673A 2003-03-12 2004-03-03 データを転送するためのデータ処理の装置および方法 Expired - Fee Related JP4892683B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP03100629 2003-03-12
EP03100629.9 2003-03-12
PCT/IB2004/050197 WO2004081803A1 (en) 2003-03-12 2004-03-03 Data processing device and method for transferring data

Publications (3)

Publication Number Publication Date
JP2006520956A JP2006520956A (ja) 2006-09-14
JP2006520956A5 JP2006520956A5 (enExample) 2007-04-26
JP4892683B2 true JP4892683B2 (ja) 2012-03-07

Family

ID=32981918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006506673A Expired - Fee Related JP4892683B2 (ja) 2003-03-12 2004-03-03 データを転送するためのデータ処理の装置および方法

Country Status (5)

Country Link
US (1) US7340553B2 (enExample)
EP (1) EP1604288A1 (enExample)
JP (1) JP4892683B2 (enExample)
CN (1) CN100520754C (enExample)
WO (1) WO2004081803A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4437464B2 (ja) * 2005-06-01 2010-03-24 株式会社ルネサステクノロジ 半導体装置及びデータ処理システム
JP4224080B2 (ja) * 2006-06-05 2009-02-12 フェリカネットワークス株式会社 情報処理端末およびそのプログラム
US8271827B2 (en) * 2007-12-10 2012-09-18 Qimonda Memory system with extended memory density capability
US7895380B2 (en) * 2009-01-21 2011-02-22 Ati Technologies Ulc Communication protocol for sharing memory resources between components of a device
US8631256B2 (en) 2010-12-22 2014-01-14 Via Technologies, Inc. Distributed management of a shared power source to a multi-core microprocessor
US8637212B2 (en) 2010-12-22 2014-01-28 Via Technologies, Inc. Reticle set modification to produce multi-core dies
US8972707B2 (en) 2010-12-22 2015-03-03 Via Technologies, Inc. Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin
US8782451B2 (en) 2010-12-22 2014-07-15 Via Technologies, Inc. Power state synchronization in a multi-core processor
US8930676B2 (en) 2010-12-22 2015-01-06 Via Technologies, Inc. Master core discovering enabled cores in microprocessor comprising plural multi-core dies
US9460038B2 (en) * 2010-12-22 2016-10-04 Via Technologies, Inc. Multi-core microprocessor internal bypass bus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0863425A (ja) * 1994-08-02 1996-03-08 Motorola Inc インタバス・バッファ
JP2000076180A (ja) * 1998-08-28 2000-03-14 Nec Corp バス接続装置及び情報処理システム

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5193204A (en) * 1984-03-06 1993-03-09 Codex Corporation Processor interface circuitry for effecting data transfers between processors
US4932040A (en) * 1987-12-07 1990-06-05 Bull Hn Information Systems Inc. Bidirectional control signalling bus interface apparatus for transmitting signals between two bus systems
CA2080210C (en) * 1992-01-02 1998-10-27 Nader Amini Bidirectional data storage facility for bus interface unit
JPH064458A (ja) * 1992-06-18 1994-01-14 Fuji Xerox Co Ltd Ｄｍａ制御装置
US5335326A (en) * 1992-10-01 1994-08-02 Xerox Corporation Multichannel FIFO device channel sequencer
FR2699706B1 (fr) * 1992-12-22 1995-02-24 Bull Sa Système de transmission de données entre un bus d'ordinateur et un réseau.
US5761450A (en) * 1994-02-24 1998-06-02 Intel Corporation Bus bridge circuit flushing buffer to a bus during one acquire/relinquish cycle by providing empty address indications
US5835742A (en) * 1994-06-14 1998-11-10 Apple Computer, Inc. System and method for executing indivisible memory operations in multiple processor computer systems with multiple busses
US5916296A (en) * 1995-06-05 1999-06-29 Nippondenso Co., Ltd. Dual processor automotive control system having flexible processor standardization
US6279087B1 (en) * 1997-12-22 2001-08-21 Compaq Computer Corporation System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations
US6212590B1 (en) * 1997-12-22 2001-04-03 Compaq Computer Corporation Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base
US6199127B1 (en) * 1997-12-24 2001-03-06 Intel Corporation Method and apparatus for throttling high priority memory accesses
US6298407B1 (en) * 1998-03-04 2001-10-02 Intel Corporation Trigger points for performance optimization in bus-to-bus bridges
US6405276B1 (en) * 1998-12-10 2002-06-11 International Business Machines Corporation Selectively flushing buffered transactions in a bus bridge
US6253268B1 (en) * 1999-01-15 2001-06-26 Telefonaktiebolaget L M Ericsson (Publ) Method and system for multiplexing a second interface on an I2C interface
US6266723B1 (en) * 1999-03-29 2001-07-24 Lsi Logic Corporation Method and system for optimizing of peripheral component interconnect PCI bus transfers
US6715023B1 (en) * 1999-09-23 2004-03-30 Altera Corporation PCI bus switch architecture
US6996659B2 (en) * 2002-07-30 2006-02-07 Lsi Logic Corporation Generic bridge core

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0863425A (ja) * 1994-08-02 1996-03-08 Motorola Inc インタバス・バッファ
JP2000076180A (ja) * 1998-08-28 2000-03-14 Nec Corp バス接続装置及び情報処理システム

Also Published As

Publication number Publication date
WO2004081803A1 (en) 2004-09-23
CN100520754C (zh) 2009-07-29
JP2006520956A (ja) 2006-09-14
CN1759385A (zh) 2006-04-12
US20060224809A1 (en) 2006-10-05
EP1604288A1 (en) 2005-12-14
US7340553B2 (en) 2008-03-04

Similar Documents

Publication Publication Date Title
CN100440184C (zh) 一种能同时进行读写操作的dma控制器及传输方法
CN100549992C (zh) 可减少延迟的数据传送与接收方法与系统
US8032686B2 (en) Protocol translation in a data storage system
EP1535169B1 (en) Improved inter-processor communication system for communication between processors
US20060004976A1 (en) Shared memory architecture
US7016994B2 (en) Retry mechanism for blocking interfaces
KR20040044366A (ko) 공유 메모리 데이터 전송장치
US20020055979A1 (en) Inter-processor communication system for communication between processors
JP4892683B2 (ja) データを転送するためのデータ処理の装置および方法
KR20180116717A (ko) 직렬 시스템 버스 인터페이스 및 직접메모리액세스 컨트롤러를 갖는 전자 시스템 및 그 동작 방법
US6567881B1 (en) Method and apparatus for bridging a digital signal processor to a PCI bus
KR20050043303A (ko) 다중 프로세서 환경에서의 ｄｍａ를 이용한 고속 데이터전송 방법 및 그 장치
US7096290B2 (en) On-chip high speed data interface
KR100291409B1 (ko) 컴퓨터 시스템내의 동일 버스상에 두 개의 부 디코드 에이전트를 지원하는 방법 및 장치
TW200521678A (en) Virtual first-in, first-out DMA device
US6754780B1 (en) Providing data in response to a read command that maintains cache line alignment
US7296109B1 (en) Buffer bypass circuit for reducing latency in information transfers to a bus
US7610415B2 (en) System and method for processing data streams
EP1759297B1 (en) Interrupt scheme for bus controller
US20070180180A1 (en) Storage system, and storage control method
JP2727514B2 (ja) 転送先ｉｄ指定回路
CA2282166C (en) Method and apparatus for bridging a digital signal processor to a pci bus
CN112783811A (zh) 微控制器架构及架构内数据读取方法
KR100393983B1 (ko) 프로세서의 과부하를 개선한 데이터 전송 장치
KR100191242B1 (ko) 데이타 전송장치

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070305

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070305

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20080529

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20091224

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100316

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20100616

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20100623

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100713

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110114

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20110414

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20110421

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20110513

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20110520

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110609

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20111104

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20111124

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111124

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150106

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees