JP2006520089A - 基板上に多層素子を製造する方法およびシステム - Google Patents

基板上に多層素子を製造する方法およびシステム Download PDF

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JP2006520089A
JP2006520089A JP2005500831A JP2005500831A JP2006520089A JP 2006520089 A JP2006520089 A JP 2006520089A JP 2005500831 A JP2005500831 A JP 2005500831A JP 2005500831 A JP2005500831 A JP 2005500831A JP 2006520089 A JP2006520089 A JP 2006520089A
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layer
semiconductor layer
bonded
substrate
layers
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Japanese (ja)
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JP2006520089A5 (enExample
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ファリス，サデグ，エム．
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レビオ インコーポレーティッド
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C99/00—Subject matter not provided for in other groups of this subclass
    • B81C99/0035—Testing
    • B81C99/0045—End test of the packaged device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Micromachines (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
JP2005500831A 2002-11-20 2003-11-20 基板上に多層素子を製造する方法およびシステム Withdrawn JP2006520089A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US42812502P 2002-11-20 2002-11-20
PCT/US2003/037304 WO2004112089A2 (en) 2002-11-20 2003-11-20 Method and system for fabricating multi layer devices on a substrate

Publications (2)

Publication Number Publication Date
JP2006520089A true JP2006520089A (ja) 2006-08-31
JP2006520089A5 JP2006520089A5 (enExample) 2007-01-11

Family

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Family Applications (1)

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JP2005500831A Withdrawn JP2006520089A (ja) 2002-11-20 2003-11-20 基板上に多層素子を製造する方法およびシステム

Country Status (8)

Country Link
US (1) US7056751B2 (enExample)
EP (1) EP1573788A3 (enExample)
JP (1) JP2006520089A (enExample)
KR (1) KR20050083935A (enExample)
CN (1) CN1742358A (enExample)
AU (1) AU2003304218A1 (enExample)
TW (3) TW200423261A (enExample)
WO (1) WO2004112089A2 (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2839505B1 (fr) * 2002-05-07 2005-07-15 Univ Claude Bernard Lyon Procede pour modifier les proprietes d'une couche mince et substrat faisant application du procede
US7659631B2 (en) * 2006-10-12 2010-02-09 Hewlett-Packard Development Company, L.P. Interconnection between different circuit types
US20090026524A1 (en) * 2007-07-27 2009-01-29 Franz Kreupl Stacked Circuits
CN102844176A (zh) * 2009-09-30 2012-12-26 微型实验室诊断股份有限公司 微流体装置中选择性的粘结性降低
KR101348655B1 (ko) * 2010-03-24 2014-01-08 한국전자통신연구원 미세유체 제어 장치 및 그 제조 방법
US8829329B2 (en) * 2010-08-18 2014-09-09 International Business Machines Corporation Solar cell and battery 3D integration
DE102010041763A1 (de) 2010-09-30 2012-04-05 Siemens Aktiengesellschaft Mikromechanisches Substrat
US10543662B2 (en) 2012-02-08 2020-01-28 Corning Incorporated Device modified substrate article and methods for making
US10086584B2 (en) 2012-12-13 2018-10-02 Corning Incorporated Glass articles and methods for controlled bonding of glass sheets with carriers
US9340443B2 (en) 2012-12-13 2016-05-17 Corning Incorporated Bulk annealing of glass sheets
TWI617437B (zh) 2012-12-13 2018-03-11 康寧公司 促進控制薄片與載體間接合之處理
US10014177B2 (en) 2012-12-13 2018-07-03 Corning Incorporated Methods for processing electronic devices
US10510576B2 (en) 2013-10-14 2019-12-17 Corning Incorporated Carrier-bonding methods and articles for semiconductor and interposer processing
CN106132688B (zh) 2014-01-27 2020-07-14 康宁股份有限公司 用于薄片与载体的受控粘结的制品和方法
KR20160145062A (ko) 2014-04-09 2016-12-19 코닝 인코포레이티드 디바이스 변경된 기판 물품 및 제조 방법
EP3297824A1 (en) 2015-05-19 2018-03-28 Corning Incorporated Articles and methods for bonding sheets with carriers
CN107810168A (zh) 2015-06-26 2018-03-16 康宁股份有限公司 包含板材和载体的方法和制品
US20170186730A1 (en) * 2015-12-26 2017-06-29 Invensas Corporation System and method for providing 3d wafer assembly with known-good-dies
KR102627237B1 (ko) 2016-06-01 2024-01-23 퀀텀-에스아이 인코포레이티드 분자들을 검출 및 분석하기 위한 통합 디바이스
TW201825623A (zh) 2016-08-30 2018-07-16 美商康寧公司 用於片材接合的矽氧烷電漿聚合物
TWI821867B (zh) 2016-08-31 2023-11-11 美商康寧公司 具以可控制式黏結的薄片之製品及製作其之方法
WO2019036710A1 (en) 2017-08-18 2019-02-21 Corning Incorporated TEMPORARY BINDING USING POLYCATIONIC POLYMERS
CN111615567B (zh) 2017-12-15 2023-04-14 康宁股份有限公司 用于处理基板的方法和用于制备包括粘合片材的制品的方法
US11315789B2 (en) * 2019-04-24 2022-04-26 Tokyo Electron Limited Method and structure for low density silicon oxide for fusion bonding and debonding
EP3925003B1 (en) 2020-02-20 2024-09-04 Yangtze Memory Technologies Co., Ltd. Dram memory device with xtacking architecture
US11829077B2 (en) * 2020-12-11 2023-11-28 Kla Corporation System and method for determining post bonding overlay
US11782411B2 (en) 2021-07-28 2023-10-10 Kla Corporation System and method for mitigating overlay distortion patterns caused by a wafer bonding tool
CN114035030B (zh) * 2021-11-05 2023-10-24 爱迪特（秦皇岛）科技股份有限公司 一种测试组件
CN116387256A (zh) * 2023-04-26 2023-07-04 上海易卜半导体有限公司 芯片堆栈及制备方法
CN119275214B (zh) * 2024-12-10 2025-02-25 电子科技大学 一种用于腐蚀工艺监控的表征器件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251517A (ja) * 1998-02-27 1999-09-17 Seiko Epson Corp ３次元デバイスの製造方法
JP2002164354A (ja) * 2000-09-14 2002-06-07 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63155731A (ja) * 1986-12-19 1988-06-28 Agency Of Ind Science & Technol 半導体装置
US5094697A (en) * 1989-06-16 1992-03-10 Canon Kabushiki Kaisha Photovoltaic device and method for producing the same
JP3214631B2 (ja) * 1992-01-31 2001-10-02 キヤノン株式会社 半導体基体及びその作製方法
US6133582A (en) * 1998-05-14 2000-10-17 Lightspeed Semiconductor Corporation Methods and apparatuses for binning partially completed integrated circuits based upon test results
US6965895B2 (en) * 2001-07-16 2005-11-15 Applied Materials, Inc. Method and apparatus for analyzing manufacturing data

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251517A (ja) * 1998-02-27 1999-09-17 Seiko Epson Corp ３次元デバイスの製造方法
JP2002164354A (ja) * 2000-09-14 2002-06-07 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法

Also Published As

Publication number Publication date
TW200423261A (en) 2004-11-01
WO2004112089A2 (en) 2004-12-23
AU2003304218A1 (en) 2005-01-04
US20040241888A1 (en) 2004-12-02
US7056751B2 (en) 2006-06-06
CN1742358A (zh) 2006-03-01
KR20050083935A (ko) 2005-08-26
TW200428538A (en) 2004-12-16
AU2003304218A8 (en) 2005-01-04
TW200421497A (en) 2004-10-16
EP1573788A2 (en) 2005-09-14
EP1573788A3 (en) 2005-11-02
WO2004112089A3 (en) 2005-09-15

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