JP2006515468A - ウェーハについての不均一性の定量化および有意性の図解化のためのユーザインタフェース - Google Patents

ウェーハについての不均一性の定量化および有意性の図解化のためのユーザインタフェース Download PDF

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Publication number
JP2006515468A
JP2006515468A JP2005501992A JP2005501992A JP2006515468A JP 2006515468 A JP2006515468 A JP 2006515468A JP 2005501992 A JP2005501992 A JP 2005501992A JP 2005501992 A JP2005501992 A JP 2005501992A JP 2006515468 A JP2006515468 A JP 2006515468A
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JP
Japan
Prior art keywords
wafer
measurement data
user interface
graphical user
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005501992A
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English (en)
Japanese (ja)
Inventor
ルーケ・ジョージ
サード・アンドリュー・ディ． ベイリー・ザ
ウィルコックソン・マーク
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/331,194 external-priority patent/US7239737B2/en
Priority claimed from US10/452,248 external-priority patent/US7738693B2/en
Application filed by Lam Research Corp filed Critical Lam Research Corp
Publication of JP2006515468A publication Critical patent/JP2006515468A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Image Processing (AREA)
JP2005501992A 2002-09-26 2003-09-24 ウェーハについての不均一性の定量化および有意性の図解化のためのユーザインタフェース Pending JP2006515468A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US41402102P 2002-09-26 2002-09-26
US10/331,194 US7239737B2 (en) 2002-09-26 2002-12-24 User interface for quantifying wafer non-uniformities and graphically explore significance
US10/452,248 US7738693B2 (en) 2002-12-24 2003-05-30 User interface for wafer data analysis and visualization
PCT/US2003/030456 WO2004030083A2 (fr) 2002-09-26 2003-09-24 Interface utilisateur permettant de quantifier les aspects non uniformes d'une plaquette et d'explorer graphiquement leur signification

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2011136899A Division JP5496955B2 (ja) 2002-09-26 2011-06-21 ウェーハについての不均一性の定量化および有意性の図解化のためのユーザインタフェース
JP2011136898A Division JP5460648B2 (ja) 2002-09-26 2011-06-21 ウェーハについての不均一性の定量化および有意性の図解化のためのユーザインタフェース

Publications (1)

Publication Number Publication Date
JP2006515468A true JP2006515468A (ja) 2006-05-25

Family

ID=32045857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005501992A Pending JP2006515468A (ja) 2002-09-26 2003-09-24 ウェーハについての不均一性の定量化および有意性の図解化のためのユーザインタフェース

Country Status (6)

Country Link
EP (1) EP1543550A2 (fr)
JP (1) JP2006515468A (fr)
KR (1) KR101127779B1 (fr)
AU (1) AU2003299056A1 (fr)
TW (1) TWI229914B (fr)
WO (1) WO2004030083A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012032344A (ja) * 2010-08-02 2012-02-16 Keyence Corp 画像測定装置、画像測定方法及び画像測定装置用のプログラム

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4290204B2 (ja) * 2007-02-13 2009-07-01 東京エレクトロン株式会社 基板処理装置の設定操作支援装置，設定操作支援方法，プログラムを記憶する記憶媒体

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1145919A (ja) * 1997-07-24 1999-02-16 Hitachi Ltd 半導体基板の製造方法
JP2000161948A (ja) * 1998-11-30 2000-06-16 Hitachi Ltd 回路パターン検査装置、および回路パターン検査方法
JP2000228430A (ja) * 1998-11-30 2000-08-15 Hitachi Ltd 回路パターンの検査装置、検査システム、および検査方法
JP2001255278A (ja) * 2000-03-08 2001-09-21 Hitachi Ltd 表面検査装置およびその方法
JP2002014054A (ja) * 2000-06-28 2002-01-18 Hitachi Ltd 検査装置および検査方法
US20020051565A1 (en) * 2000-10-26 2002-05-02 Takashi Hiroi Circuit pattern inspection method and apparatus
JP2002148027A (ja) * 2000-11-09 2002-05-22 Hitachi Ltd パターン検査方法及び装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5127726A (en) * 1989-05-19 1992-07-07 Eastman Kodak Company Method and apparatus for low angle, high resolution surface inspection
JP2941308B2 (ja) * 1989-07-12 1999-08-25 株式会社日立製作所 検査システムおよび電子デバイスの製造方法
US6185324B1 (en) 1989-07-12 2001-02-06 Hitachi, Ltd. Semiconductor failure analysis system
US5448399A (en) * 1992-03-13 1995-09-05 Park Scientific Instruments Optical system for scanning microscope
US5761064A (en) * 1995-10-06 1998-06-02 Advanced Micro Devices, Inc. Defect management system for productivity and yield improvement
US6477685B1 (en) * 1999-09-22 2002-11-05 Texas Instruments Incorporated Method and apparatus for yield and failure analysis in the manufacturing of semiconductors
US6586263B2 (en) * 2000-09-18 2003-07-01 Neuristics Physics Laboratory, Inc. Correction of overlay offset between inspection layers in integrated circuits

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1145919A (ja) * 1997-07-24 1999-02-16 Hitachi Ltd 半導体基板の製造方法
JP2000161948A (ja) * 1998-11-30 2000-06-16 Hitachi Ltd 回路パターン検査装置、および回路パターン検査方法
JP2000228430A (ja) * 1998-11-30 2000-08-15 Hitachi Ltd 回路パターンの検査装置、検査システム、および検査方法
JP2001255278A (ja) * 2000-03-08 2001-09-21 Hitachi Ltd 表面検査装置およびその方法
JP2002014054A (ja) * 2000-06-28 2002-01-18 Hitachi Ltd 検査装置および検査方法
US20020051565A1 (en) * 2000-10-26 2002-05-02 Takashi Hiroi Circuit pattern inspection method and apparatus
JP2002148027A (ja) * 2000-11-09 2002-05-22 Hitachi Ltd パターン検査方法及び装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012032344A (ja) * 2010-08-02 2012-02-16 Keyence Corp 画像測定装置、画像測定方法及び画像測定装置用のプログラム

Also Published As

Publication number Publication date
EP1543550A2 (fr) 2005-06-22
KR101127779B1 (ko) 2012-03-27
WO2004030083A2 (fr) 2004-04-08
TW200414395A (en) 2004-08-01
AU2003299056A1 (en) 2004-04-19
TWI229914B (en) 2005-03-21
WO2004030083A3 (fr) 2004-07-15
KR20050084603A (ko) 2005-08-26

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