JP2006509375A - 多層ゲートスタック - Google Patents

多層ゲートスタック Download PDF

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Publication number
JP2006509375A
JP2006509375A JP2004559293A JP2004559293A JP2006509375A JP 2006509375 A JP2006509375 A JP 2006509375A JP 2004559293 A JP2004559293 A JP 2004559293A JP 2004559293 A JP2004559293 A JP 2004559293A JP 2006509375 A JP2006509375 A JP 2006509375A
Authority
JP
Japan
Prior art keywords
layer
gate
nitride layer
semiconductor
sccm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004559293A
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English (en)
Japanese (ja)
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JP2006509375A5 (https=
Inventor
ソウラブ デュッタ チャウドフリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cypress Semiconductor Corp
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Publication of JP2006509375A publication Critical patent/JP2006509375A/ja
Publication of JP2006509375A5 publication Critical patent/JP2006509375A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01354—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2004559293A 2002-12-06 2003-12-04 多層ゲートスタック Pending JP2006509375A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/314,380 US7229929B2 (en) 2002-12-06 2002-12-06 Multi-layer gate stack
PCT/US2003/038631 WO2004053936A2 (en) 2002-12-06 2003-12-04 Multi-layer gate stack

Publications (2)

Publication Number Publication Date
JP2006509375A true JP2006509375A (ja) 2006-03-16
JP2006509375A5 JP2006509375A5 (https=) 2007-01-25

Family

ID=32468458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004559293A Pending JP2006509375A (ja) 2002-12-06 2003-12-04 多層ゲートスタック

Country Status (5)

Country Link
US (1) US7229929B2 (https=)
JP (1) JP2006509375A (https=)
KR (1) KR20050085415A (https=)
AU (1) AU2003300819A1 (https=)
WO (1) WO2004053936A2 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7229929B2 (en) * 2002-12-06 2007-06-12 Cypress Semiconductor Corporation Multi-layer gate stack
US20040217006A1 (en) * 2003-03-18 2004-11-04 Small Robert J. Residue removers for electrohydrodynamic cleaning of semiconductors
US7371637B2 (en) * 2003-09-26 2008-05-13 Cypress Semiconductor Corporation Oxide-nitride stack gate dielectric
US7153780B2 (en) * 2004-03-24 2006-12-26 Intel Corporation Method and apparatus for self-aligned MOS patterning
US7351663B1 (en) * 2004-06-25 2008-04-01 Cypress Semiconductor Corporation Removing whisker defects
KR100753138B1 (ko) * 2006-09-29 2007-08-30 주식회사 하이닉스반도체 반도체 소자 제조방법
US8252640B1 (en) 2006-11-02 2012-08-28 Kapre Ravindra M Polycrystalline silicon activation RTA
JP2008218867A (ja) * 2007-03-07 2008-09-18 Elpida Memory Inc 半導体装置の製造方法
US7951728B2 (en) * 2007-09-24 2011-05-31 Applied Materials, Inc. Method of improving oxide growth rate of selective oxidation processes
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US9406530B2 (en) 2014-03-27 2016-08-02 International Business Machines Corporation Techniques for fabricating reduced-line-edge-roughness trenches for aspect ratio trapping
US10204960B2 (en) * 2015-09-17 2019-02-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming polysilicon gate structure in image sensor device
US20170330764A1 (en) * 2016-05-12 2017-11-16 Lam Research Corporation Methods and apparatuses for controlling transitions between continuous wave and pulsing plasmas
US10566211B2 (en) 2016-08-30 2020-02-18 Lam Research Corporation Continuous and pulsed RF plasma for etching metals
US9865473B1 (en) * 2016-11-15 2018-01-09 Globalfoundries Inc. Methods of forming semiconductor devices using semi-bidirectional patterning and islands
TW202505978A (zh) * 2023-07-18 2025-02-01 聯華電子股份有限公司 記憶體結構及製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001051424A (ja) * 1999-06-02 2001-02-23 Semiconductor Leading Edge Technologies Inc 微細パターン形成方法
JP2002222868A (ja) * 2001-01-29 2002-08-09 Fujitsu Ltd 半導体装置及びその製造方法
JP2006505141A (ja) * 2002-10-31 2006-02-09 アプライド　マテリアルズ　インコーポレイテッド シリコン含有誘電物質をエッチングする方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW320749B (https=) * 1994-09-22 1997-11-21 Tokyo Electron Co Ltd
US5817579A (en) * 1997-04-09 1998-10-06 Vanguard International Semiconductor Corporation Two step plasma etch method for forming self aligned contact
JP3902835B2 (ja) * 1997-06-27 2007-04-11 東京応化工業株式会社 ポジ型ホトレジスト組成物
US6635185B2 (en) * 1997-12-31 2003-10-21 Alliedsignal Inc. Method of etching and cleaning using fluorinated carbonyl compounds
US6107135A (en) * 1998-02-11 2000-08-22 Kabushiki Kaisha Toshiba Method of making a semiconductor memory device having a buried plate electrode
US6342452B1 (en) * 1999-05-20 2002-01-29 International Business Machines Corporation Method of fabricating a Si3N4/polycide structure using a dielectric sacrificial layer as a mask
US6740566B2 (en) * 1999-09-17 2004-05-25 Advanced Micro Devices, Inc. Ultra-thin resist shallow trench process using high selectivity nitride etch
US6258677B1 (en) * 1999-10-01 2001-07-10 Chartered Seminconductor Manufacturing Ltd. Method of fabricating wedge isolation transistors
US6897120B2 (en) * 2001-01-03 2005-05-24 Micron Technology, Inc. Method of forming integrated circuitry and method of forming shallow trench isolation in a semiconductor substrate
US6624068B2 (en) * 2001-08-24 2003-09-23 Texas Instruments Incorporated Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography
US6451647B1 (en) * 2002-03-18 2002-09-17 Advanced Micro Devices, Inc. Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual
US7229929B2 (en) * 2002-12-06 2007-06-12 Cypress Semiconductor Corporation Multi-layer gate stack

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001051424A (ja) * 1999-06-02 2001-02-23 Semiconductor Leading Edge Technologies Inc 微細パターン形成方法
JP2002222868A (ja) * 2001-01-29 2002-08-09 Fujitsu Ltd 半導体装置及びその製造方法
JP2006505141A (ja) * 2002-10-31 2006-02-09 アプライド　マテリアルズ　インコーポレイテッド シリコン含有誘電物質をエッチングする方法

Also Published As

Publication number Publication date
US20040110387A1 (en) 2004-06-10
AU2003300819A8 (en) 2004-06-30
US7229929B2 (en) 2007-06-12
AU2003300819A1 (en) 2004-06-30
WO2004053936A2 (en) 2004-06-24
WO2004053936A3 (en) 2005-03-17
KR20050085415A (ko) 2005-08-29

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