JP2006508414A5 - - Google Patents

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Publication number
JP2006508414A5
JP2006508414A5 JP2003586743A JP2003586743A JP2006508414A5 JP 2006508414 A5 JP2006508414 A5 JP 2006508414A5 JP 2003586743 A JP2003586743 A JP 2003586743A JP 2003586743 A JP2003586743 A JP 2003586743A JP 2006508414 A5 JP2006508414 A5 JP 2006508414A5
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JP
Japan
Prior art keywords
instruction
group
standard
augmented
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2003586743A
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English (en)
Japanese (ja)
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JP4002554B2 (ja
JP2006508414A (ja
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Publication date
Priority claimed from US10/127,087 external-priority patent/US7447886B2/en
Application filed filed Critical
Publication of JP2006508414A publication Critical patent/JP2006508414A/ja
Publication of JP2006508414A5 publication Critical patent/JP2006508414A5/ja
Application granted granted Critical
Publication of JP4002554B2 publication Critical patent/JP4002554B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2003586743A 2002-04-22 2003-04-14 拡張命令エンコーディングのシステムおよびその方法 Expired - Fee Related JP4002554B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/127,087 US7447886B2 (en) 2002-04-22 2002-04-22 System for expanded instruction encoding and method thereof
PCT/US2003/011571 WO2003090067A2 (en) 2002-04-22 2003-04-14 System for expanded instruction encoding and method thereof

Publications (3)

Publication Number Publication Date
JP2006508414A JP2006508414A (ja) 2006-03-09
JP2006508414A5 true JP2006508414A5 (enExample) 2006-05-25
JP4002554B2 JP4002554B2 (ja) 2007-11-07

Family

ID=29215173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003586743A Expired - Fee Related JP4002554B2 (ja) 2002-04-22 2003-04-14 拡張命令エンコーディングのシステムおよびその方法

Country Status (5)

Country Link
US (1) US7447886B2 (enExample)
EP (1) EP1497712A2 (enExample)
JP (1) JP4002554B2 (enExample)
AU (1) AU2003234102A1 (enExample)
WO (1) WO2003090067A2 (enExample)

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US20080040590A1 (en) * 2006-08-11 2008-02-14 Lea Hwang Lee Selective branch target buffer (btb) allocaiton
US20080040591A1 (en) * 2006-08-11 2008-02-14 Moyer William C Method for determining branch target buffer (btb) allocation for branch instructions
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US8281109B2 (en) * 2007-12-27 2012-10-02 Intel Corporation Compressed instruction format
US20090240928A1 (en) * 2008-03-18 2009-09-24 Freescale Semiconductor, Inc. Change in instruction behavior within code block based on program action external thereto
JP5300294B2 (ja) * 2008-03-25 2013-09-25 パナソニック株式会社 処理装置、難読化装置、プログラムおよび集積回路
US9182959B2 (en) * 2008-08-15 2015-11-10 Apple Inc. Predicate count and segment count instructions for processing vectors
US8209525B2 (en) * 2008-08-15 2012-06-26 Apple Inc. Method and apparatus for executing program code
US8621448B2 (en) 2010-09-23 2013-12-31 Apple Inc. Systems and methods for compiler-based vectorization of non-leaf code
US8949808B2 (en) 2010-09-23 2015-02-03 Apple Inc. Systems and methods for compiler-based full-function vectorization
US9529574B2 (en) 2010-09-23 2016-12-27 Apple Inc. Auto multi-threading in macroscalar compilers
US20120185670A1 (en) * 2011-01-14 2012-07-19 Toll Bret L Scalar integer instructions capable of execution with three registers
WO2013095634A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction
US9052888B2 (en) 2013-02-21 2015-06-09 International Business Machines Corporation Vectorization in an optimizing compiler
US10180829B2 (en) * 2015-12-15 2019-01-15 Nxp Usa, Inc. System and method for modulo addressing vectorization with invariant code motion
US11614941B2 (en) * 2018-03-30 2023-03-28 Qualcomm Incorporated System and method for decoupling operations to accelerate processing of loop structures
US11216281B2 (en) * 2019-05-14 2022-01-04 International Business Machines Corporation Facilitating data processing using SIMD reduction operations across SIMD lanes
CN114327815B (zh) * 2021-12-10 2025-03-04 龙芯中科技术股份有限公司 原子性保持方法、处理器及电子设备
US12530197B2 (en) * 2023-03-08 2026-01-20 SiFive, Inc. Vector instruction processing after primary decode

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