JPH1091434A5 - - Google Patents

Info

Publication number
JPH1091434A5
JPH1091434A5 JP1997205455A JP20545597A JPH1091434A5 JP H1091434 A5 JPH1091434 A5 JP H1091434A5 JP 1997205455 A JP1997205455 A JP 1997205455A JP 20545597 A JP20545597 A JP 20545597A JP H1091434 A5 JPH1091434 A5 JP H1091434A5
Authority
JP
Japan
Prior art keywords
instruction
memory location
data processor
state
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997205455A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1091434A (ja
JP3830236B2 (ja
Filing date
Publication date
Priority claimed from US08/684,717 external-priority patent/US6523095B1/en
Application filed filed Critical
Publication of JPH1091434A publication Critical patent/JPH1091434A/ja
Publication of JPH1091434A5 publication Critical patent/JPH1091434A5/ja
Application granted granted Critical
Publication of JP3830236B2 publication Critical patent/JP3830236B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP20545597A 1996-07-22 1997-07-15 クイック・デコード命令を用いるための方法およびデータ処理システム Expired - Fee Related JP3830236B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US684717 1996-07-22
US08/684,717 US6523095B1 (en) 1996-07-22 1996-07-22 Method and data processing system for using quick decode instructions

Publications (3)

Publication Number Publication Date
JPH1091434A JPH1091434A (ja) 1998-04-10
JPH1091434A5 true JPH1091434A5 (enExample) 2005-05-19
JP3830236B2 JP3830236B2 (ja) 2006-10-04

Family

ID=24749266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20545597A Expired - Fee Related JP3830236B2 (ja) 1996-07-22 1997-07-15 クイック・デコード命令を用いるための方法およびデータ処理システム

Country Status (3)

Country Link
US (1) US6523095B1 (enExample)
JP (1) JP3830236B2 (enExample)
KR (1) KR100678354B1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9098297B2 (en) * 1997-05-08 2015-08-04 Nvidia Corporation Hardware accelerator for an object-oriented programming language
US20090240928A1 (en) * 2008-03-18 2009-09-24 Freescale Semiconductor, Inc. Change in instruction behavior within code block based on program action external thereto
US9851990B2 (en) * 2015-01-30 2017-12-26 American Megatrends, Inc. Method and system for performing on-demand data write through based on UPS power status
US9886387B2 (en) 2015-01-30 2018-02-06 American Megatrends, Inc. Method and system for performing on-demand data write through based on virtual machine types

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910656A (en) * 1987-09-21 1990-03-20 Motorola, Inc. Bus master having selective burst initiation
EP0349123B1 (en) * 1988-06-27 1995-09-20 Digital Equipment Corporation Multi-processor computer systems having shared memory and private cache memories
US5155824A (en) * 1989-05-15 1992-10-13 Motorola, Inc. System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
JPH0625984B2 (ja) * 1990-02-20 1994-04-06 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン マルチプロセツサ・システム
US5426765A (en) * 1991-08-30 1995-06-20 Compaq Computer Corporation Multiprocessor cache abitration
GB2260628A (en) * 1991-10-11 1993-04-21 Intel Corp Line buffer for cache memory
US5428761A (en) * 1992-03-12 1995-06-27 Digital Equipment Corporation System for achieving atomic non-sequential multi-word operations in shared memory
JP3242161B2 (ja) * 1992-09-11 2001-12-25 株式会社日立製作所 データプロセッサ
US5572700A (en) * 1993-04-30 1996-11-05 Intel Corporation Cache access controller and method for permitting caching of information in selected cache lines
US5555392A (en) * 1993-10-01 1996-09-10 Intel Corporation Method and apparatus for a line based non-blocking data cache

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