JP3830236B2 - クイック・デコード命令を用いるための方法およびデータ処理システム - Google Patents

クイック・デコード命令を用いるための方法およびデータ処理システム Download PDF

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Publication number
JP3830236B2
JP3830236B2 JP20545597A JP20545597A JP3830236B2 JP 3830236 B2 JP3830236 B2 JP 3830236B2 JP 20545597 A JP20545597 A JP 20545597A JP 20545597 A JP20545597 A JP 20545597A JP 3830236 B2 JP3830236 B2 JP 3830236B2
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Japan
Prior art keywords
instruction
memory location
data processor
execution
meaning
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Expired - Fee Related
Application number
JP20545597A
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English (en)
Japanese (ja)
Other versions
JPH1091434A (ja
JPH1091434A5 (enExample
Inventor
マウリシオ・ブレターニッツ，ジュニア
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NXP USA Inc
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NXP USA Inc
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Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JPH1091434A publication Critical patent/JPH1091434A/ja
Publication of JPH1091434A5 publication Critical patent/JPH1091434A5/ja
Application granted granted Critical
Publication of JP3830236B2 publication Critical patent/JP3830236B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
JP20545597A 1996-07-22 1997-07-15 クイック・デコード命令を用いるための方法およびデータ処理システム Expired - Fee Related JP3830236B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US684717 1996-07-22
US08/684,717 US6523095B1 (en) 1996-07-22 1996-07-22 Method and data processing system for using quick decode instructions

Publications (3)

Publication Number Publication Date
JPH1091434A JPH1091434A (ja) 1998-04-10
JPH1091434A5 JPH1091434A5 (enExample) 2005-05-19
JP3830236B2 true JP3830236B2 (ja) 2006-10-04

Family

ID=24749266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20545597A Expired - Fee Related JP3830236B2 (ja) 1996-07-22 1997-07-15 クイック・デコード命令を用いるための方法およびデータ処理システム

Country Status (3)

Country Link
US (1) US6523095B1 (enExample)
JP (1) JP3830236B2 (enExample)
KR (1) KR100678354B1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9098297B2 (en) * 1997-05-08 2015-08-04 Nvidia Corporation Hardware accelerator for an object-oriented programming language
US20090240928A1 (en) * 2008-03-18 2009-09-24 Freescale Semiconductor, Inc. Change in instruction behavior within code block based on program action external thereto
US9886387B2 (en) 2015-01-30 2018-02-06 American Megatrends, Inc. Method and system for performing on-demand data write through based on virtual machine types
US9851990B2 (en) * 2015-01-30 2017-12-26 American Megatrends, Inc. Method and system for performing on-demand data write through based on UPS power status

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910656A (en) * 1987-09-21 1990-03-20 Motorola, Inc. Bus master having selective burst initiation
DE68924306T2 (de) * 1988-06-27 1996-05-09 Digital Equipment Corp Mehrprozessorrechneranordnungen mit gemeinsamem Speicher und privaten Cache-Speichern.
US5155824A (en) * 1989-05-15 1992-10-13 Motorola, Inc. System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
JPH0625984B2 (ja) * 1990-02-20 1994-04-06 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン マルチプロセツサ・システム
US5426765A (en) * 1991-08-30 1995-06-20 Compaq Computer Corporation Multiprocessor cache abitration
GB2260628A (en) * 1991-10-11 1993-04-21 Intel Corp Line buffer for cache memory
US5428761A (en) * 1992-03-12 1995-06-27 Digital Equipment Corporation System for achieving atomic non-sequential multi-word operations in shared memory
JP3242161B2 (ja) * 1992-09-11 2001-12-25 株式会社日立製作所 データプロセッサ
US5572700A (en) * 1993-04-30 1996-11-05 Intel Corporation Cache access controller and method for permitting caching of information in selected cache lines
US5555392A (en) * 1993-10-01 1996-09-10 Intel Corporation Method and apparatus for a line based non-blocking data cache

Also Published As

Publication number Publication date
JPH1091434A (ja) 1998-04-10
KR980010777A (ko) 1998-04-30
US6523095B1 (en) 2003-02-18
KR100678354B1 (ko) 2007-11-12

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