AU2003234102A1 - System for expanded instruction encoding and method thereof - Google Patents

System for expanded instruction encoding and method thereof

Info

Publication number
AU2003234102A1
AU2003234102A1 AU2003234102A AU2003234102A AU2003234102A1 AU 2003234102 A1 AU2003234102 A1 AU 2003234102A1 AU 2003234102 A AU2003234102 A AU 2003234102A AU 2003234102 A AU2003234102 A AU 2003234102A AU 2003234102 A1 AU2003234102 A1 AU 2003234102A1
Authority
AU
Australia
Prior art keywords
instruction encoding
expanded instruction
expanded
encoding
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003234102A
Other languages
English (en)
Other versions
AU2003234102A8 (en
Inventor
Lea-Hwang Lee
William C. Moyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU2003234102A1 publication Critical patent/AU2003234102A1/en
Publication of AU2003234102A8 publication Critical patent/AU2003234102A8/xx
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Devices For Executing Special Programs (AREA)
AU2003234102A 2002-04-22 2003-04-14 System for expanded instruction encoding and method thereof Abandoned AU2003234102A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/127,087 2002-04-22
US10/127,087 US7447886B2 (en) 2002-04-22 2002-04-22 System for expanded instruction encoding and method thereof
PCT/US2003/011571 WO2003090067A2 (en) 2002-04-22 2003-04-14 System for expanded instruction encoding and method thereof

Publications (2)

Publication Number Publication Date
AU2003234102A1 true AU2003234102A1 (en) 2003-11-03
AU2003234102A8 AU2003234102A8 (en) 2003-11-03

Family

ID=29215173

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003234102A Abandoned AU2003234102A1 (en) 2002-04-22 2003-04-14 System for expanded instruction encoding and method thereof

Country Status (5)

Country Link
US (1) US7447886B2 (enExample)
EP (1) EP1497712A2 (enExample)
JP (1) JP4002554B2 (enExample)
AU (1) AU2003234102A1 (enExample)
WO (1) WO2003090067A2 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7734898B2 (en) * 2004-09-17 2010-06-08 Freescale Semiconductor, Inc. System and method for specifying an immediate value in an instruction
EP1994467A2 (en) * 2006-03-02 2008-11-26 Nxp B.V. Optimized compilation method during conditional branching
US20080040591A1 (en) * 2006-08-11 2008-02-14 Moyer William C Method for determining branch target buffer (btb) allocation for branch instructions
US20080040590A1 (en) * 2006-08-11 2008-02-14 Lea Hwang Lee Selective branch target buffer (btb) allocaiton
US8959500B2 (en) * 2006-12-11 2015-02-17 Nytell Software LLC Pipelined processor and compiler/scheduler for variable number branch delay slots
US8281109B2 (en) 2007-12-27 2012-10-02 Intel Corporation Compressed instruction format
US20090240928A1 (en) * 2008-03-18 2009-09-24 Freescale Semiconductor, Inc. Change in instruction behavior within code block based on program action external thereto
JP5300294B2 (ja) * 2008-03-25 2013-09-25 パナソニック株式会社 処理装置、難読化装置、プログラムおよび集積回路
US8131979B2 (en) * 2008-08-15 2012-03-06 Apple Inc. Check-hazard instructions for processing vectors
US9182959B2 (en) * 2008-08-15 2015-11-10 Apple Inc. Predicate count and segment count instructions for processing vectors
US9529574B2 (en) 2010-09-23 2016-12-27 Apple Inc. Auto multi-threading in macroscalar compilers
US8949808B2 (en) 2010-09-23 2015-02-03 Apple Inc. Systems and methods for compiler-based full-function vectorization
US8621448B2 (en) 2010-09-23 2013-12-31 Apple Inc. Systems and methods for compiler-based vectorization of non-leaf code
US20120185670A1 (en) * 2011-01-14 2012-07-19 Toll Bret L Scalar integer instructions capable of execution with three registers
CN104081337B (zh) * 2011-12-23 2017-11-07 英特尔公司 用于响应于单个指令来执行横向部分求和的系统、装置和方法
US9052888B2 (en) 2013-02-21 2015-06-09 International Business Machines Corporation Vectorization in an optimizing compiler
US10180829B2 (en) * 2015-12-15 2019-01-15 Nxp Usa, Inc. System and method for modulo addressing vectorization with invariant code motion
US11614941B2 (en) * 2018-03-30 2023-03-28 Qualcomm Incorporated System and method for decoupling operations to accelerate processing of loop structures
US11216281B2 (en) * 2019-05-14 2022-01-04 International Business Machines Corporation Facilitating data processing using SIMD reduction operations across SIMD lanes
CN114327815B (zh) * 2021-12-10 2025-03-04 龙芯中科技术股份有限公司 原子性保持方法、处理器及电子设备
US20240303082A1 (en) * 2023-03-08 2024-09-12 SiFive, Inc. Vector Instruction Processing After Primary Decode

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4434459A (en) 1980-04-25 1984-02-28 Data General Corporation Data processing system having instruction responsive apparatus for both a basic and an extended instruction set
JPS59128670A (ja) * 1983-01-12 1984-07-24 Hitachi Ltd ベクトル処理装置
JPH06101044B2 (ja) * 1988-01-23 1994-12-12 シャープ株式会社 デッドロック回避実行制御方式
US5303358A (en) 1990-01-26 1994-04-12 Apple Computer, Inc. Prefix instruction for modification of a subsequent instruction
US5247696A (en) * 1991-01-17 1993-09-21 Cray Research, Inc. Method for compiling loops having recursive equations by detecting and correcting recurring data points before storing the result to memory
US5361354A (en) * 1991-12-17 1994-11-01 Cray Research, Inc. Optimization of alternate loop exits
US5530804A (en) * 1994-05-16 1996-06-25 Motorola, Inc. Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes
US5802375A (en) * 1994-11-23 1998-09-01 Cray Research, Inc. Outer loop vectorization
US5748964A (en) * 1994-12-20 1998-05-05 Sun Microsystems, Inc. Bytecode program interpreter apparatus and method with pre-verification of data type restrictions
US6081880A (en) * 1995-03-09 2000-06-27 Lsi Logic Corporation Processor having a scalable, uni/multi-dimensional, and virtually/physically addressed operand register file
JP3711422B2 (ja) 1995-12-20 2005-11-02 セイコーエプソン株式会社 情報処理回路
US5799163A (en) * 1997-03-04 1998-08-25 Samsung Electronics Co., Ltd. Opportunistic operand forwarding to minimize register file read ports
US5903769A (en) * 1997-03-31 1999-05-11 Sun Microsystems, Inc. Conditional vector processing
US6044222A (en) * 1997-06-23 2000-03-28 International Business Machines Corporation System, method, and program product for loop instruction scheduling hardware lookahead
US6108768A (en) * 1998-04-22 2000-08-22 Sun Microsystems, Inc. Reissue logic for individually reissuing instructions trapped in a multiissue stack based computing system
US6292886B1 (en) * 1998-10-12 2001-09-18 Intel Corporation Scalar hardware for performing SIMD operations
US6496923B1 (en) * 1999-12-17 2002-12-17 Intel Corporation Length decode to detect one-byte prefixes and branch
US6795908B1 (en) * 2000-02-16 2004-09-21 Freescale Semiconductor, Inc. Method and apparatus for instruction execution in a data processing system

Also Published As

Publication number Publication date
WO2003090067A2 (en) 2003-10-30
WO2003090067A3 (en) 2004-04-01
US7447886B2 (en) 2008-11-04
AU2003234102A8 (en) 2003-11-03
JP4002554B2 (ja) 2007-11-07
US20030200426A1 (en) 2003-10-23
JP2006508414A (ja) 2006-03-09
EP1497712A2 (en) 2005-01-19

Similar Documents

Publication Publication Date Title
AU2003243646A1 (en) System and method for facilitating ridesharing
AU2003259115A1 (en) System and method for reward-based education
AU2003275045A1 (en) Knowledge system method and apparatus
AU2003282702A1 (en) System and method for creating systolic solvers
AU2002307768A1 (en) System and method for phytomonitoring
AU2003290758A1 (en) System and method for discovery and configuration
AU2003245639A1 (en) System and method for pose-angle estimation
AU2003283762A1 (en) Object positioning system, object positioning apparatus and object positioning method
AU2003302327A8 (en) System and method for below-market trading
AU2003277410A1 (en) Suturing system and method
AU2003222143A1 (en) Open platform system and method
AU2003268373A1 (en) Polymorphic computational system and method
AU2003234102A1 (en) System for expanded instruction encoding and method thereof
AU2003231377A1 (en) Recycle method and system thereof
AU2003272707A1 (en) Sender-address-based callback system and method
AU2003272506A1 (en) System and method for making casingless sausage
AU2003302049A1 (en) System and method for characterizing three-dimensional structures
AU2003267660A1 (en) System and method for preferred memory affinity
AU2003247051A1 (en) System and method for segmenting
AU2003253830A1 (en) Application modification system and method
AU2003215359A1 (en) System and method for object activation
GB2390439B (en) Dataconferencing system and method
AU2003269731A1 (en) Regasification system and method
AU2003242268A1 (en) Exposure system and exposure method
AU2002257312A1 (en) Offer system and method

Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase