JP4002554B2 - 拡張命令エンコーディングのシステムおよびその方法 - Google Patents

拡張命令エンコーディングのシステムおよびその方法 Download PDF

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Publication number
JP4002554B2
JP4002554B2 JP2003586743A JP2003586743A JP4002554B2 JP 4002554 B2 JP4002554 B2 JP 4002554B2 JP 2003586743 A JP2003586743 A JP 2003586743A JP 2003586743 A JP2003586743 A JP 2003586743A JP 4002554 B2 JP4002554 B2 JP 4002554B2
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instruction
standard
execution
vector
augmented
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Japanese (ja)
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JP2006508414A5 (enExample
JP2006508414A (ja
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リー、リー−ウォン
シー． モイヤー、ウィリアム
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NXP USA Inc
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NXP USA Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Devices For Executing Special Programs (AREA)
JP2003586743A 2002-04-22 2003-04-14 拡張命令エンコーディングのシステムおよびその方法 Expired - Fee Related JP4002554B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/127,087 US7447886B2 (en) 2002-04-22 2002-04-22 System for expanded instruction encoding and method thereof
PCT/US2003/011571 WO2003090067A2 (en) 2002-04-22 2003-04-14 System for expanded instruction encoding and method thereof

Publications (3)

Publication Number Publication Date
JP2006508414A JP2006508414A (ja) 2006-03-09
JP2006508414A5 JP2006508414A5 (enExample) 2006-05-25
JP4002554B2 true JP4002554B2 (ja) 2007-11-07

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JP2003586743A Expired - Fee Related JP4002554B2 (ja) 2002-04-22 2003-04-14 拡張命令エンコーディングのシステムおよびその方法

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Country Link
US (1) US7447886B2 (enExample)
EP (1) EP1497712A2 (enExample)
JP (1) JP4002554B2 (enExample)
AU (1) AU2003234102A1 (enExample)
WO (1) WO2003090067A2 (enExample)

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US7734898B2 (en) * 2004-09-17 2010-06-08 Freescale Semiconductor, Inc. System and method for specifying an immediate value in an instruction
EP1994467A2 (en) * 2006-03-02 2008-11-26 Nxp B.V. Optimized compilation method during conditional branching
US20080040591A1 (en) * 2006-08-11 2008-02-14 Moyer William C Method for determining branch target buffer (btb) allocation for branch instructions
US20080040590A1 (en) * 2006-08-11 2008-02-14 Lea Hwang Lee Selective branch target buffer (btb) allocaiton
US8959500B2 (en) * 2006-12-11 2015-02-17 Nytell Software LLC Pipelined processor and compiler/scheduler for variable number branch delay slots
US8281109B2 (en) 2007-12-27 2012-10-02 Intel Corporation Compressed instruction format
US20090240928A1 (en) * 2008-03-18 2009-09-24 Freescale Semiconductor, Inc. Change in instruction behavior within code block based on program action external thereto
JP5300294B2 (ja) * 2008-03-25 2013-09-25 パナソニック株式会社 処理装置、難読化装置、プログラムおよび集積回路
US8131979B2 (en) * 2008-08-15 2012-03-06 Apple Inc. Check-hazard instructions for processing vectors
US9182959B2 (en) * 2008-08-15 2015-11-10 Apple Inc. Predicate count and segment count instructions for processing vectors
US9529574B2 (en) 2010-09-23 2016-12-27 Apple Inc. Auto multi-threading in macroscalar compilers
US8949808B2 (en) 2010-09-23 2015-02-03 Apple Inc. Systems and methods for compiler-based full-function vectorization
US8621448B2 (en) 2010-09-23 2013-12-31 Apple Inc. Systems and methods for compiler-based vectorization of non-leaf code
US20120185670A1 (en) * 2011-01-14 2012-07-19 Toll Bret L Scalar integer instructions capable of execution with three registers
CN104081337B (zh) * 2011-12-23 2017-11-07 英特尔公司 用于响应于单个指令来执行横向部分求和的系统、装置和方法
US9052888B2 (en) 2013-02-21 2015-06-09 International Business Machines Corporation Vectorization in an optimizing compiler
US10180829B2 (en) * 2015-12-15 2019-01-15 Nxp Usa, Inc. System and method for modulo addressing vectorization with invariant code motion
US11614941B2 (en) * 2018-03-30 2023-03-28 Qualcomm Incorporated System and method for decoupling operations to accelerate processing of loop structures
US11216281B2 (en) * 2019-05-14 2022-01-04 International Business Machines Corporation Facilitating data processing using SIMD reduction operations across SIMD lanes
CN114327815B (zh) * 2021-12-10 2025-03-04 龙芯中科技术股份有限公司 原子性保持方法、处理器及电子设备
US20240303082A1 (en) * 2023-03-08 2024-09-12 SiFive, Inc. Vector Instruction Processing After Primary Decode

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JPS59128670A (ja) * 1983-01-12 1984-07-24 Hitachi Ltd ベクトル処理装置
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US6795908B1 (en) * 2000-02-16 2004-09-21 Freescale Semiconductor, Inc. Method and apparatus for instruction execution in a data processing system

Also Published As

Publication number Publication date
WO2003090067A2 (en) 2003-10-30
AU2003234102A1 (en) 2003-11-03
WO2003090067A3 (en) 2004-04-01
US7447886B2 (en) 2008-11-04
AU2003234102A8 (en) 2003-11-03
US20030200426A1 (en) 2003-10-23
JP2006508414A (ja) 2006-03-09
EP1497712A2 (en) 2005-01-19

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