JP2006504274A - 集積受動電子素子を備えた電子素子およびその製造方法 - Google Patents
集積受動電子素子を備えた電子素子およびその製造方法 Download PDFInfo
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- JP2006504274A JP2006504274A JP2004547382A JP2004547382A JP2006504274A JP 2006504274 A JP2006504274 A JP 2006504274A JP 2004547382 A JP2004547382 A JP 2004547382A JP 2004547382 A JP2004547382 A JP 2004547382A JP 2006504274 A JP2006504274 A JP 2006504274A
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Abstract
Description
Claims (28)
- 第1絶縁層(1)と、
上記第1絶縁層(1)の上に形成された上段金属層(5)(特に、導電性のボンディングパッド層)と、
上記第1絶縁層(1)に集積されており、特に上段金属層(5)をボンディングする際および/または電子素子(EB)を実装する際の機械的な力の作用に対して第1絶縁層(1)を機械的に安定させる、受動電子素子として形成されている導電性構造(2)とを備えた電子素子。 - 上記第1絶縁層(1)が、誘電率4未満(特に3未満)の材料から形成されていることを特徴とする、請求項1に記載の電子素子。
- 上記上段金属層(1)がボンディング領域(BB)を備え、このボンディング領域(BB)のほぼ真下に、上記導電性構造(2)が配置されていることを特徴とする、請求項1または2に記載の電子素子。
- 上記導電性構造(2)の、上段金属層(5)に対して平行な面の面積が、少なくともボンディング領域(BB)の面積と等しいことを特徴とする、請求項3に記載の電子素子。
- 上記導電性構造(2)が、バイアホール(V)と電気コンタクト片(KM)(特にコンタクト金属細片)とを介して、印加電圧源と接地電位とに接続されることを特徴とする、請求項1〜4のいずれか1項に記載の電子素子。
- 少なくとも1つの導電性遮蔽層(3)が、上段金属層(5)と導電性構造(2)との間に、それらから電気的に絶縁された状態で形成されていることを特徴とする、請求項1〜5のいずれか1項に記載の電子素子。
- 上記遮蔽層(3)が第2金属層であり、この遮蔽層(3)が接地電位に接続されていることを特徴とする、請求項6に記載の電子素子。
- 上記遮蔽層(3)が第3絶縁層(4a)の中に形成されており、上記第3絶縁層(4a)が、第1絶縁層(1)と上段金属層(5)との間に配置されていることを特徴とする、請求項6または7に記載の電子素子。
- 上記遮蔽層(3)が、切れ目のない板または格子構造として形成されていることを特徴とする、請求項6〜8のいずれか1項に記載の電子素子。
- 導電性構造(2)と向かい合う遮蔽層(3)の領域が、遮蔽層(3)と向かい合う導電性構造(2)の領域と少なくとも等しい面積を有し、これらの領域を上下に重ねたとした場合に、遮蔽層(3)の上記領域が導電性構造(2)の上記領域を完全に含むようになっていることを特徴とする、請求項6〜9のいずれか1項に記載の電子素子。
- 上記導電性構造(2)が、容量構造および/またはインダクタンス構造として形成されていることを特徴とする、請求項1〜10のいずれか1項に記載の電子素子。
- 上記導電性構造(2)の少なくとも1つの部分領域が、容量構造として形成されているとともに少なくとも2つの金属配線面を備えており、
第1金属配線面には、互いに平行に配置されて互いに絶縁されている細片(M11、M12、M13)が形成されており、これらの細片は、第2金属配線面に互いに平行に配置されて互いに絶縁されている細片(M21、M22、M23)と重なり合うように配置されており、
上記2つの金属配線面において上下に配置された細片(M11、M21;M12、M22;M13、M23)が、バイアホール(V)を介して電気的に接続されていることを特徴とする、請求項11に記載の電子素子。 - 上記導電性構造(2)の少なくとも1つの部分領域が、インダクタンス構造として形成されているとともに少なくとも1つの金属配線面を備え、この金属配線面には螺旋状の金属配線が形成されていることを特徴とする、請求項11または12に記載の電子素子。
- 上記上段金属層(5)が、第3絶縁層(4a)のコンタクト領域(6)を介して、導電性領域(7)に電気的に接続されており、この導電性領域(7)が、特に第2または第3絶縁層(4)の中に配置されていることを特徴とする、請求項8に記載の電子素子。
- 上記コンタクト領域(6)および第2導電性領域(7)が、導電性構造(2)と上段金属層(5)のボンディング領域(BB)とに対して水平方向にずれて配置されていることを特徴とする、請求項14に記載の電子素子。
- 上記導電性構造(2)は、その上面および下面が第1絶縁層(1)の上面および下面と一致するように形成されており、第1導電性構造(2)の表面領域が、第1絶縁層(1)の上面および下面の一部を形成していることを特徴とする、請求項1〜16のいずれか1項に記載の電子素子。
- 基板と、請求項1〜16のいずれか1項または複数項に記載の電子素子(EB)とを備え、この電子素子(EB)が上記基板上に形成されている集積回路。
- 第1絶縁層を形成する工程と、
上記第1絶縁層(1)の上に、上段金属層(5)(特に、導電性のボンディングパッド層)を形成する工程と、
上記第1絶縁層(1)の中に、導電性構造(2)を、上段金属層(5)から電気的に絶縁された状態で、受動電子素子および機械的安定構造として形成する工程と、を有する電子素子の製造方法。 - 上記第1絶縁層(1)が、誘電率4未満(特に3未満)の材料から形成されることを特徴とする、請求項18に記載の方法。
- 上記導電性構造(2)が、上段金属層(5)のボンディング領域のほぼ下に形成され、上記導電性構造(2)の、上段金属層(5)に対して平行な面が、ボンディング領域(BB)と少なくとも等しい大きさに形成されることを特徴とする、請求項18または19に記載の方法。
- 上記導電性構造(2)が、バイアホールおよびコンタクト片(KM)(特に、コンタクト金属細片)を介して、印加電圧源と接地電位とに接続されることを特徴とする、請求項18〜20のいずれか1項に記載の方法。
- 上記上段金属層(5)と導電性構造(2)との間に、導電性遮蔽層(3)が、上段金属層(5)と導電性構造(2)とから電気的に絶縁された状態で、特に第1絶縁層(1)の上に形成された第3絶縁層(4a)の中に形成されることを特徴とする、請求項18〜21のいずれか1項に記載の方法。
- 上記導電性遮蔽層(3)が、板または格子構造として形成され、接地電位に接続されることを特徴とする、請求項22に記載の方法。
- 上記導電性遮蔽層(3)の水平方向における広がりが、導電性構造(2)の水平方向における広がりと少なくとも等しい大きさとなり、導電性遮蔽層(3)の上記広がりが導電性構造(2)の上記広がりを完全に覆うように、上記導電性遮蔽層(3)が形成されることを特徴とする、請求項22または23に記載の方法。
- 上記導電性構造(2)が、容量構造および/またはインダクタンス構造として形成されることを特徴とする、請求項18〜24のいずれか1項に記載の方法。
- 上記導電性構造(2)の少なくとも1つの部分領域が、容量構造として形成され、
第1金属配線面と第2金属配線面とに、互いに電気的に絶縁された状態で互いに平行となるように導電性細片(M11、M12、M13;M21、M22、M23)がそれぞれ形成され、
上記第1金属配線面と第2金属配線面とに形成された導電性細片(M11、M12、M13;M21、M22、M23)が、ほぼ重なり合うように配置され、バイアホール(V)を介して電気的に接続され、水平方向に隣接する細片(M11、M12、M13;M21、M22、M23)が、第1電位と第2電位とに交互に接続されることを特徴とする、請求項25に記載の方法。 - 上記導電性構造(2)の少なくとも1つの部分領域が、インダクタンス構造として形成され、少なくとも1つの金属配線面に螺旋状の金属配線が形成されることを特徴とする、請求項25または26に記載の方法。
- 基板を形成し、上記基板の上に、請求項18〜27のいずれか1項または複数項に記載の電子素子を形成する集積回路の製造方法。
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JP2007059867A (ja) * | 2005-07-26 | 2007-03-08 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2008047718A (ja) * | 2006-08-17 | 2008-02-28 | Nec Corp | 半導体装置 |
JP2011199225A (ja) * | 2010-03-24 | 2011-10-06 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
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JP5643580B2 (ja) | 2009-11-27 | 2014-12-17 | 株式会社東芝 | 血流動態解析装置、血流動態解析プログラム、流体解析装置及び流体解析プログラム |
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JP2007059867A (ja) * | 2005-07-26 | 2007-03-08 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2008047718A (ja) * | 2006-08-17 | 2008-02-28 | Nec Corp | 半導体装置 |
US8334759B2 (en) | 2008-01-29 | 2012-12-18 | Renesas Electronics Corporation | Semiconductor device, method of manufacturing thereof, signal transmission/reception method using such semiconductor device, and tester apparatus |
US8729651B2 (en) | 2008-01-29 | 2014-05-20 | Renesas Electronics Corporation | Semiconductor device, method of manufacturing thereof, signal transmission/reception method using such semiconductor device, and tester apparatus |
US9105501B2 (en) | 2008-01-29 | 2015-08-11 | Renesas Electronics Corporation | Semiconductor device, method of manufacturing thereof, signal transmission/reception method using such semiconductor device, and tester apparatus |
JP2011199225A (ja) * | 2010-03-24 | 2011-10-06 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
US9042117B2 (en) | 2010-03-24 | 2015-05-26 | Renesas Electronics Corporation | Semiconductor device |
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KR20050071600A (ko) | 2005-07-07 |
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WO2004040646A1 (de) | 2004-05-13 |
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