TWI284420B - Semiconductor chip with partially embedded decoupling capacitors - Google Patents

Abstract

A partially embedded decoupling capacitor is provided as an integral part of a semiconductor chip for reducing delta-I noise. The semiconductor chip includes a plurality of embedded metal layers, a passivation layer formed above the plurality of embedded metal layers as a topmost layer of the semiconductor chip, and a plurality of bonding pads disposed on the passivation layer. A surface planar metal pattern is formed on the passivation layer and electrically connected to one of the plurality of embedded metal layers through one of the plurality of bonding pads or a via hole opened on the passivation layer. For example, the surface planar metal pattern may be connected to a power layer or a ground layer of the semiconductor chip. Therefore, the partially embedded decoupling capacitor is made up of the surface planar metal pattern as an electrode, others of the plurality of embedded metal layers as opposite electrodes, and the passivation layer sandwiched therebetween as a dielectric layer. Since connected to one of the plurality of embedded metal layers, the surface planar metal pattern further serves as a heat sink for dissipating heat directly from the inside of the semiconductor chip.

Description

V. INSTRUCTIONS OF THE INVENTION (1) 1. Technical Field to Which the Invention A Field The present invention relates to a 1-33⁄4 μ, ^ yv ^ 禋 + 蛉 body wafer, especially for a semiconductor solar yoke, which is useful for indigo Decoupling capacitors from the 丄 type. The part of the 降低 降低 del del del del 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Switching on the logic gate operation Conductor chip resistance: electric [: large f change. The change in current is caused by the inductive nature of the power line and the ground line. When the body crystal is operated at a high speed, the power supply of the source is reduced, and the circuit is half of the circuit. Guide 艚曰 斟 private τ Α, guide, and plus. In this case, the sensitivity of the 7/body day film to the heart 1 "-1 noise is increased as a frequency. The maximum 操 Τ / noise for the semiconductor wafer 1 shows the usual semi-conductor mounted on the lead frame As shown in Fig.!, the semiconductor wafer i is provided with a plurality of::; sheet:: according to the topmost layer of the semiconductor wafer 1 纯化 打开 打开 打开 打开 而 而 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 对应The buried metal layer (not shown) is connected to the corresponding terminal 13 of one of the lead frames 14 via a bonding wire 15 . 1284420

: The circuit diagram of the equivalent circuit of Figure 1 is not shown. As shown in Fig. 2, the symbol :J is electrically supplied to the outside Dc on the mother board (not shown) of the support lead frame 14. The symbol Rt and , respectively, represent the external DC power supply, and the equivalent resistance value between the lead frame and the lead frame ^ ^ ^ r ^ jjx 屯丨 value inductance value. The symbols Cpl and (^ both represent the mid-frequency mid-frequency) decoupling capacitors. Regarding the bonding wires 15, each of them has an equivalent resistance value 匕 and an inductance value, and an equivalent resistance value 连接 connected between the two adjacent bonding wires 1, 5. Regarding the semiconductor wafer, the symbols I and p represent the current flowing from the power supply line )]) to the ground line vss in the semiconductor wafer, and the symbol C_p represents the built-in high-frequency decoupling capacitance. As is clear from Fig. 2, the bonding wiring 15 has an equivalent inductance value, and the delta-I noise is formed in the switch of the logic gate inside the semiconductor wafer 1A. Specifically, when the logic gate is switched, the change in current (indicated by 1) causes a voltage (represented by Δu) to be generated, as shown by the following equation: ΔV: 'f ” This is due to delta-I noise. The resulting voltage instability makes the supply quality to the semiconductor wafer 10 worse, thus suppressing the possibility of high operation. One strategy for dealing with del ta-I noise is to insert a decoupling capacitor into the semiconductor wafer 1 0 and the bonding wiring 1 5. The valley Figure 3 shows a top view of a conventional decoupling capacitor semiconductor wafer. As shown in Figure 3, for example, two layers of ceramic capacitors -

Layer Ceramic Capacitor ’MLCC) 16 as a light capacitor. Each MLCC 16 is connected in series to the power supply of the semiconductor chip.

1284420_________ V. Description of invention (3). The equivalent circuit of each MLCC 16 includes a resistor I, an inductor Lg, and a capacitor Q connected in series with each other, as shown in FIG. While the addition of MLCC 16 can successfully reduce del ta-I noise, the use of MLCC 16 is associated with at least two disadvantages. First, the MLCC 16 must be bonded to the semiconductor wafer 1 . This bonding of the ML·CC not only increases the overall manufacturing steps, but also deteriorates the reliability of the semiconductor wafer 10. In addition, the efficiency of the MLCC 16 to reduce delta-I noise is inevitably limited by the equivalent inductance Lg. In order to avoid these disadvantages, a conventional Metal-Insulator-Metal (MIM) process is employed to form another type of decoupling capacitor. Typically, a semiconductor wafer having a high degree of circuit integration includes a plurality of embedded metal layers separated by an insulator layer. Two of the metal layers, for example, the n-th metal layer and the (n-1)th metal layer in the n-layer metal layer wafer structure are used as the power supply metal layer and the ground metal layer, respectively. According to the ΜIΜ process, an additional metal layer is embedded in the insulator layer between the power metal layer and the ground metal layer to work as a decoupling capacitor together with the ground metal layer. Figure 5 shows that there are!! A circuit diagram of an equivalent circuit of a semiconductor wafer of the decoupling capacitor 17. Although the use of the decoupling capacitor 17 has the advantage of eliminating the equivalent inductance compared to the use of the MLCC, the fabrication process of the semiconductor wafer is further complicated by the formation of the decoupling capacitor 17. Third, [invention content]

In view of the foregoing problems, it is an object of the present invention to provide a semiconductor wafer that can reduce deltH by a decoupling capacitor having no equivalent inductance.

Page 11 1284420 ___ V. Description of invention (4) Noise. Another object of the present invention is to provide a semiconductor wafer that can reduce delta-I noise by decoupling capacitors without changing the original circuit layout and fabrication process of the semiconductor wafer. It is still another object of the present invention to provide a semiconductor wafer which can reduce del t a-I noise by decoupling capacitors fabricated at low cost and high reliability. According to the present invention, a partially embedded decoupling capacitor is provided as an integral portion of a semiconductor wafer for reducing del t a-I noise. The semiconductor wafer includes a plurality of embedded metal layers and a passivation layer formed over the plurality of embedded metal layers as a topmost layer of the semiconductor wafer and a plurality of pads disposed on the purification layer. a surface planar metal pattern is formed on the passivation layer and electrically connected to the plurality of buried vias via one of the plurality of pads or a via separated from the plurality of pads on the passivation layer One of the layers. For example, the surface planar metal pattern is connected to one of the power pads or a ground layer of the semiconductor wafer. = " The decoupling type decoupling capacitor is connected by a surface planar metal ^ ^ pole, an electrode, and other layers of a plurality of embedded metal layers: as a dielectric layer. Both the pattern is more as a genus: one of the f, the surface of the planar metal is hot. "," state, which is used to directly disperse the inside of the semiconductor wafer according to the present invention, the 屌 knife embedded type decoupling capacitor is easy to manufacture without changing the original circuit layout and manufacturing procedure of the semiconductor. Health

Page 12 1284420 V. INSTRUCTIONS (5) Reduced production costs and solutions. The capacitance is formed as a semi-conductor; 曰: the reliability is increased. In addition, since the decoupling surface capacitance 2 = : one of the integral parts, the conductor wafer and the solution are obtained; ί: 部分 part of the embedded decoupling capacitor of the semiconductor 曰 侍 女装 具有 具有 具有 具有Let ~ 亍 I 焊 a pad electrically connect to a lead frame of ij, so that the complex number is passed through a number of terminals. For example, the plurality of solder bumps; borrow = upper:;; =: connected to the plurality of terminals. Thus, the upper portion of the wire frame is obtained by encapsulating the electron-conducting wire frame to form a semi-conducting wafer. Fourth, [the lower feature, the passivation of the wafer pad 11 is under the bonding pad 11 13 . The above and other objects and advantages of the present invention will become more apparent from the description and accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments in accordance with the present invention will be described in detail. 6 shows a top view of a semiconducting portion of a partially embedded decoupling capacitor in accordance with the present invention. As shown in Fig. 6, a plurality of semiconductor wafers 1 are provided thereon. The pad 11 is formed on the topmost layer 12 of the semiconductor wafer 1 and is connected to the buried metal layer of the semiconductor wafer 1 via the via hole opened in the passivation layer (2 (not shown). ). Each of the corresponding ends connected to one of the lead frames 14 via a bonding wire 15 is formed on the passivation layer 12 by sputtering, printing, or deposition according to the present invention. Further, the surface planar metal pattern becomes in contact with the pad 1 1. As mentioned earlier, with high circuit accumulation

Page 13 1284420 V. INSTRUCTION DESCRIPTION (6) ^ The semiconductor wafer 10 includes a layer of the genus. In the second of the metal layers, the nth metal layer and the (n") 1 metal layer. In the case of the surface planar type gold H source metal layer, the decoupling pattern 18 is used as the upper electrode, the blunt is used as the dielectric layer, and the grounded metal surface is used. In the case of the surface planar metal pattern layer, the decoupling capacitor 1 is decoupled. 8 as the upper electrode, the purification layer i 2 electric layer, and the power supply metal layer as the middle 'because of the decoupler wafer 10 according to the present invention, the present inventors are embedded. The plurality of embedded 2 layers separated by the body layer are respectively connected to the stomach through the solder wire 11 as a power source and a contact pattern, respectively, and are connected to the capacitor by the surface planar type gold layer 12 and / or embedded layer of insulator as a lower electrode. The other side 18 is connected to the ground gold via the bonding pad 11 by a surface planar metal pattern and/or an embedded insulator layer as a dielectric electrode. In both cases, the electrodes are embedded in the semiconductor under the capacitance. This decoupling capacitor is referred to as the circuit diagram of the equivalent circuit of the partially embedded decoupling capacitor according to the present invention. 7, the equivalent capacitance L is formed between the surface plane 1 metal pattern 18 and the embedded third layer, equivalent capacitance, formed between the surface planar metal pattern 18 and the embedded (n-丨) metal layer. And an equivalent electric valley Cgi is formed between the surface planar metal pattern 18 and the buried first metal layer. Although it has been connected to the mat 11 by a surface-oriented metal pattern 18 as an upper electrode The present invention is not limited thereto. Referring to FIG. 6, for example, in the step of forming the passivation layer 丨2, a through hole is opened at a position separated from the pad on the purification layer 12.

1284420 Description of invention (8) Equivalent inductance (Lg) Equivalent capacitance (Cg) —---------- · Maximum transient current VDD peak voltage without handle-to-handle capacitance ^ ---—--- οΙΓ~ ~~ -------- OF 400 mA 1.030 V 650 mH 5 pF 400 mA 1.139 V MLCC 650 mH 10 pF 400 mA 1.185 V 650 mH 15 pF 400 mA 1.218 V --- 5 —__ 650 mH 20 pF 400 mA 1.247 V MIM Decoupling oT^—— 400 mA ' ~~ 1.145 V |ΓΓ~ 10 pF 400 mA 1.200 V Valley Fh 15 pF 400 mA 1.224 V 〇l ~ 20 pF 400 mA 1.252 V Partially embedded The decoupling capacitor condition is the same as the MIM decoupling capacitor. In Table 1, the VDD peak voltage is calculated under various conditions in which the equivalent inductance Lg and the equivalent capacitance Cg are assigned different values. The d e 11 a -1 noise causes the VDD peak voltage to deviate from the external DC power supply Vs = 2· 5 V. Accordingly, when the VDD peak voltage of the semiconductor wafer obtained by the simulation is very close to the external DC power supply Vs, it means that the semiconductor wafer is considerably prevented from being affected by the delta-1 noise. As is clear from Table 1, a portion of the embedded decoupling capacitor in accordance with the present invention successfully reduces the I of the semiconductor chip by more. Specifically, "for embedded embedding type light and electricity with 20 pF

Page 16 1284420 31, invention description (9) It t ΐ VDD peak power is i 252 v, and for semiconductor wafers without depletion valley VDD peak voltage is 丨 · 〇 3 〇 V. In the case of a semiconductor wafer having an unembedded coupling capacitor, it has a portion; The delta_i noise of the semiconductor chip of the /a capacitor is reduced. In addition, the partially embedded decoupling capacitor according to the present invention achieves a better effect than the conventional MLCC in the reduction of e t9^1 and noise. * % Eye Note Although the DM peak voltage is the same, the delta_i noise of the MIM decoupling electric t is the same as that of the partially embedded decoupling electric = gossip, as shown in the simulation results of Table 1, but in terms of manufacturing In view of the above, the scabbard decouples the buried razor, and the combined capacitance 'is required for many additional lithography steps. Therefore, the partial embedded type solution according to the present invention is applied lightly. —: Change the original circuit layout and manufacturing process advantages of semiconductor wafers. F-semiconductor wafers have been used to provide low cost and high reliability, and it has been confirmed that some of the best-in-class buried capacitors have been tested without decoupling.

栌曰Η 栌曰Η 栌曰Η 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰 丰In the body, the part to be used is buried. The measured value is about 0.007464. The maturity of the area is about _ 700. The test results are listed in the following table = product [Table 2]

1284420 V. Description of invention (10)

In terms of the semi-conducting Zhao wafer, which is divided into high-level accumulation, the part provides a better planar plastic metal pattern 18 or 2° with a semi-conducting static solution. Fig. 8 is a cross-sectional view showing an electronic package structure having a partially embedded decoupling-deuterium film. Figure 18, page 18, 1284420. Brief description of the diagram. 5. [Simplified illustration of the diagram] Figure 1 shows a top view of a typical semiconductor wafer mounted on a lead frame; Figure 2 shows a circuit diagram of the equivalent circuit of Figure 1. Figure 3 shows a top view of a semiconductor wafer having a conventional decoupling capacitor; Figure 4 shows a circuit diagram of the equivalent circuit of Figure 3; Figure 5 shows a circuit diagram of an equivalent circuit of a semiconductor wafer having a ΜI Μ decoupling capacitor; A top view of a semiconductor wafer having a partially embedded decoupling capacitor according to the shoulder of the present invention is shown, and FIG. 7 is a circuit diagram showing an equivalent circuit of a partially embedded decoupling capacitor according to the present invention; and FIG. 8 is partially embedded. A cross-sectional view of an electronic package structure of a semiconductor wafer of a type decoupling capacitor. Description of component symbols: 10 Semiconductor wafer 11 Pad 12 Passivation layer 13 Terminal 14 Lead frame 15 Bonding wiring 16 Multilayer ceramic capacitor (MLCC)

Page 20 1284420 Brief description of the diagram 17 MIM decoupling capacitor ^ 1 8 Surface flat metal pattern 19 Through hole 20 Surface flat gold lip pattern 2 1 Package mould

Page 21

Claims (1)

Its capacity ^3⁄4 coupling and decoupling embedded part of the item 11 The following paragraph Fan Li special application for example 3·中 1284420 丨丨_一_ Six, the scope of application for patents, combined capacitance, with "! noise, metal layer The conductor wafer includes a plurality of layers of the buried metal layer of the semiconductor wafer as a purification layer, the capacitor layer top layer, and a plurality of solder bumps disposed on the surface of the planar metal pattern The passivation layer is electrically connected to one of the plurality of embedded metal layers, wherein the surface planar metal pattern is electrically connected as one of the decoupling capacitor electrodes and the other layers of the embedded metal layer At least one layer is used as the other electrode of the electric valley, and the passivation layer acts as a coupling dielectric layer of the decoupling capacitor, and the surface planar metal pattern is used as a heat sink for multiple embedding The buried metal layer is electrically connected to the layer of the surface planar metal pattern to directly dissipate heat from the interior of the semiconductor wafer. 2. The partially embedded decoupling capacitor of claim 1, wherein the surface planar metal pattern is connected to the plurality of embedded metal layers via one of the plurality of pads layer. ^ The semiconductor wafer further includes a via opening on the passivation layer, at a position of the plurality of pads, the through hole passing down through the passivation layer 2 to expose the plurality of embedded metal layers One layer, and 2 '2 ΐ""" ~~ 1284420 VI. Scope of application: The surface of the planar metal pattern covers and fills the through hole so that the exposed layer of the plurality of embedded metal layers is exposed.连. : ; .. - · Part of the scope of the patent application, the buried plastic solution light-capacitor, in which "two of the embedded metal is electrically connected to the surface of the planar gold, the layer of the conductive conductor crystal H +@ 蜀(二) is one of the power layers of γ-limb day and day. 5. If the patent application scope flute 1 TS > Α _ _ . ^ Part 1 of the first member wants to embed the surface capacitance, one of which: embedded Electrical connection in the metal layer: the first layer is the semiconductor layer V-ground layer. The pattern 6 · a semiconductor wafer, comprising: a plurality of embedded metal layers; a purification layer to form the plurality of semiconductor wafers One of the most tributary layers; a plurality of solder bumps disposed on the blunt portion of the buried type decoupling capacitor comprising a surface planar metal pattern, and a pattern of the plurality of embedded metal layers is used as the decoupling capacitor At least one of the other layers in the layer is used as the decoupling electric-surface type metal pattern, and is electrically connected to the surface of the metal layer embedded in the surface of the surface. On the layer; a ta-I noise, a passivation layer and an electrical connection layer, wherein the surface planar type of gold is embedded in the other electrode of the metal capacitor, and a dielectric layer is formed, and the surface is flatly embedded by the plurality of layers The electrode, the decoupling 'for straight through the layer of the planar metal pattern Page 23 1284420 Doping, dissipating heat from the inside of the semiconductor wafer. 7. According to the sixth item of the patent application, the 金属-type metal pattern is via the 曰曰, +-conductor 纟, the surface of the 数, the embedded surface of the metal layer; One of the pads is electrically connected to the plurality of vias, such as a half via of the sixth item of the patent application, opened at the position of the passivation layer, the through hole passing down one of the layers of the blunt metal layer, _conductor The wafer further includes: a layer separated from the plurality of pads to expose the plurality of embedded electrodes, wherein the surface planar metal is attached to the plurality of embedded metal patterns to cover and fill the via holes, The exposed layer of the layer. 9. The semiconductor device of claim 6 wherein the plurality of embedding: the layer of the genus layer electrically connected to the surface planar metal pattern is a power supply layer of the semiconductor wafer. 10. The semiconductor wafer of claim 6, wherein the one of the plurality of embedded metal layers electrically connected to the surface planar metal pattern is a ground layer of the semiconductor wafer. 11. An electronic package structure comprising: a lead frame having a plurality of terminals; a semiconductor wafer mounted on the lead frame such that the plurality of /,, the scope of the patent application is connected to the plurality of terminals - a semiconductor wafer, the plurality of embedded metal layers V of the semiconductor crystal is a passivation layer, forming a plurality of embedded metal layers, One of the topmost layers of the +conductor wafer; a plurality of pads, disposed on the passivation layer; and the signal, the package is divided into two sub-type buried junction capacitors, to reduce the dew-1 hybrid connection to 'full a y-surface metal pattern is formed on the passivation layer and electrically connected to one of the plurality of buried metal lips, the metal pattern being used as the decoupling + capacitor - at least one of the other layers as === ί a flattening layer as a dielectric of the (four) capacitor, and an electrical connection in the buried metal layer: 兮 is used to connect to the layer of the surface planar metal pattern via the plurality of embedded twos & Directly dissipating heat from the interior of the semiconductor wafer; and a "chip.-package mold" covering the lead frame for encapsulating the semiconductor crystal package structure, wherein one of the surface pads is electrically connected to 12 11 items of electronic flat type The genus pattern is soldered to the one of the plurality of embedded metal layers via the plurality of electrodes, and the semiconductor wafer further includes a via sub-package structure in which the semiconductor layer is opened on the passivation layer. Points 13. 1284420 6. The patent application scope is away from the position of the plurality of solder pads, the through hole exposing one of the plurality of embedded metal layers] and passing through the passivation layer to cover the surface planar metal pattern and The exposed layer is attached to the plurality of embedded metal layers. μ k ? ' is electrically connected to π · as the electronic seal of the scope of the patent application # ^ ^ ^ ^ ', you bear one of the power supply layers of the conductor chip. 15. If the electronic seal of the nth item of the patent application scope is stipulated, the i is made up of the 私 私 Γ Γ Γ surface planar metal pattern. 16. The electronic package broadcast i1 Φ # $ machine of the application scope of claim 11 is soldered to the plurality of terminals by the plurality of connection wires.