JP2006352175A - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
JP2006352175A
JP2006352175A JP2006270656A JP2006270656A JP2006352175A JP 2006352175 A JP2006352175 A JP 2006352175A JP 2006270656 A JP2006270656 A JP 2006270656A JP 2006270656 A JP2006270656 A JP 2006270656A JP 2006352175 A JP2006352175 A JP 2006352175A
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Japan
Prior art keywords
lead
plating
wire
solder
resin
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JP2006270656A
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English (en)
Japanese (ja)
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JP2006352175A5 (enExample
Inventor
Yoshinori Miyaki
美典 宮木
Hiromichi Suzuki
博通 鈴木
Takeshi Kaneda
剛 金田
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2006270656A priority Critical patent/JP2006352175A/ja
Publication of JP2006352175A publication Critical patent/JP2006352175A/ja
Publication of JP2006352175A5 publication Critical patent/JP2006352175A5/ja
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
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  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2006270656A 2006-10-02 2006-10-02 半導体集積回路装置 Pending JP2006352175A (ja)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8319330B2 (en) 2010-07-16 2012-11-27 Renesas Electronics Corporation Semiconductor package having exterior plating films formed over surfaces of outer leads
JP2017195252A (ja) * 2016-04-19 2017-10-26 富士通テン株式会社 プリント配線板

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8319330B2 (en) 2010-07-16 2012-11-27 Renesas Electronics Corporation Semiconductor package having exterior plating films formed over surfaces of outer leads
JP2017195252A (ja) * 2016-04-19 2017-10-26 富士通テン株式会社 プリント配線板
US10573619B2 (en) 2016-04-19 2020-02-25 Fujitsu Ten Limited Printed wiring board

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