JP2006352175A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means which effectively prevents a wire from breaking due to an increase in heat quantity applied to a semiconductor integrated circuit device. <P>SOLUTION: A metal layer containing a palladium layer is formed on a portion to which a connecting member having conductivity is connected; and an alloy layer which has a melting point higher than that of tin-lead eutectic solder and does not contain lead as main constitutional metal is provided on a portion outside a portion sealed with resin. The metal layer is provided on the connecting portion so that the thickness of a portion where the connecting member having conductivity is crimped is 10 μm or more. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective in preventing wire breakage.

  In the conventional assembly process of a semiconductor integrated circuit, the following steps are performed. That is, in the Ag spot plating process, the tip of the lead (hereinafter referred to as the inner lead) of the pressed or etched lead frame sealed by the mold (including a portion where the chip and the lead frame are wire-bonded with Au (gold) wire) ) Ag spot plating. Next, in the assembly process of the package, die bonding, wire bonding, and assembly of the package to be sealed are performed. In the subsequent exterior plating process (including the dipping process), Sn-Pb (tin) is attached in advance to the portion including the contact portion of the lead (hereinafter referred to as the outer lead) that is not sealed by the mold to be attached to the printed circuit board or circuit board. -Lead) solder layer is deposited by exterior plating. After the outer spot plating process is completed from the Ag spot plating process, the process proceeds to the product processing process.

  However, in recent years when countermeasures against environmental problems have been demanded, especially as for Pb, as pointed out in JP-A-5-270860 (Patent Document 1), etc., in general electronic components such as semiconductor integrated circuit devices and mounting substrates, etc. Therefore, it is required to reduce Pb to an appropriate level for environmental measures.

Conventionally, in order to reduce Pb, Sn-Pb solder used in the exterior plating process is replaced with other solders (alloys) that do not contain Pb as the main metal, that is, lead-free alternative solder (solder composed of lead-free metal). It has been dealt with by replacing. Lead-free alternative solder is required to have the same melting temperature range as Sn-Pb and excellent bondability, especially wettability. There is currently no composition that completely meets these requirements, and the present situation is that the composition is properly used according to members such as a printed wiring board, a chip component, and a semiconductor package. Therefore, depending on the application, Sn-based alloys based on Sn are used in various compositions, for example, a solder layer that is attached to a conventional outer lead in Japanese Patent Laid-Open No. 10-93004 (Patent Document 2). There has been proposed an invention in which a Sn—Bi (tin-bismuth) system is used instead of a Sn—Pb (tin-lead) system. Regarding the configuration of the metal component of the solder, an invention in which a package outer lead and a substrate are mounted using Sn-Ag-Bi (tin-silver-bismuth) solder in Japanese Patent Laid-Open No. 11-179586 (Patent Document 3) is disclosed. Proposed.
JP-A-5-270860 Japanese Patent Laid-Open No. 10-93004 JP 11-179586 A Japanese Patent Laid-Open No. 11-40723 Japanese Patent Laid-Open No. 11-220084 JP-A-10-284666 JP-A-10-298798 Japanese Patent Laid-Open No. 10-18056 Japanese Patent Laid-Open No. 11-8341

  When using Sn-Pb eutectic alternative lead-free solder for exterior plating, selecting an Sn-based alloy for each application is as described in the prior art. In equipment and highly reliable parts, alloys having excellent bonding strength and heat fatigue resistance are desired. Sn-Ag alloy is known as an Sn-based alloy with excellent bonding strength and heat fatigue resistance and high reliability, and the melting point of Sn-Pb eutectic solder is generally 183 ° C In contrast, the melting point of most Sn—Ag alloys is 200 ° C. or higher, which is higher than the melting point of Sn—Pb eutectic solder. Therefore, at present, the reflow temperature when mounting a semiconductor integrated circuit using Sn-Pb eutectic alternative lead-free solder must be increased. Therefore, the present inventor mounted a semiconductor integrated circuit device in which the inner lead is Ag-plated and the outer lead is plated using a lead-free alternative solder having a melting point higher than that of the Sn-Pb eutectic solder at a higher reflow temperature than before. The evaluation was performed. As a result, it was found that a product defect caused by wire breakage occurred.

  Accordingly, one object of the present invention is that a semiconductor integrated circuit device in which outer leads are plated using a lead-free alternative solder having a higher melting point than Sn-Pb eutectic solder is mounted at a higher reflow temperature than before. An object of the present invention is to provide means for effectively preventing wire breakage that occurs.

  Another object of the present invention is not to increase the reflow temperature, but to provide means for effectively preventing wire breakage caused by an increase in the amount of heat generally applied to a semiconductor integrated circuit device.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. That is, a conductive connecting member and a metal layer including a palladium layer are provided at a portion to which the connecting member is connected, and has a melting point higher than that of solder containing lead as a main constituent metal, and does not contain lead as a main constituent metal. A semiconductor integrated circuit device comprising: a member to be connected provided in a portion outside the portion where the alloy layer is sealed with resin; and a resin that seals the portion to be connected.

  In the above invention, Pd (palladium) is used as the metal provided through a means such as plating to form a portion to which the connection member is connected. There is no problem in bonding properties with wires such as Au wires as conductive connecting members and frame materials as connected members such as Cu alloys and 42 alloys, and Pd is a metal that is harder than Ag and capillary This is because there are few defects due to the penetration, and there is little variation in the thickness of the attached metal for each connected member. However, the part where the connection member is connected as the place of adhesion formation is the minimum as long as there is no problem in bondability with the connection member because Pd is not lower in cost than Sn-Pb metal and Ag. This is because it should be limited to a limited area. In particular, when it is used for adhesion formation of a portion outside the resin sealing body such as an outer lead having a large area, the purpose of cost reduction cannot be effectively achieved.

  After adhesion formation, problems such as plating cracks that may occur due to molding processing or the like that applies physical deformation force to the adhesion formation location are problematic because the plating location is sealed and not molded in the present invention. Must not. In addition, the use of Pd has advantages such as avoiding Ag migration and eliminating the need for highly toxic cyan during plating.

  In addition, the melting point is higher than that of solder containing lead as a main constituent metal, and the connected member formed by adhering an alloy containing no lead as a main constituent metal to a portion outside the portion sealed with the resin is as follows. In order to be able to use materials other than Cu frame such as 42Ni-Fe alloy which is the material of the frame as the connected member, and the same Pd plating as the inner lead tip part, the material cost This is because the cost cannot be reduced and the problems inherent to the entire surface Pd plating are avoided.

  Furthermore, the technical idea of the present invention that Pd plating is applied to the tip of the inner lead can be applied to the thinning of the wire accompanying chip shrink because it can reduce the plating thickness variation and increase the bonding strength. The present inventor has also found out.

  Therefore, the outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a wire having a diameter of 30 μm or less and a metal layer including a palladium layer are provided at a portion to which the wire is connected, and a solder containing lead as a main constituent metal is provided at a portion outside the portion sealed with resin. A semiconductor integrated circuit device comprising: a connected member to be connected; and a resin for sealing the connected portion.

  Since the palladium metal layer is adhered and formed on the bonding member, the bonding strength is improved, so even in the current situation where the transition to lead-free has not been made completely, the number of pins or the size of the package is increased, and the wire associated with chip shrink This is effective for improving the assembly yield and improving the reliability even when the wire is thinned (the wire diameter is 30 μm or less at present). In addition, since the palladium metal layer only needs to be attached and formed at the connected part, the palladium metal layer is attached to the tab in addition to the tip of the inner lead due to the cost of the adhesion forming process and the material cost. It may be formed.

  The background of the idea for the invention described in the present application will be described in detail below.

  The inventor of the present application repeated evaluation to find out the cause of the wire breakage, and newly identified the cause of the occurrence. As a result of the analysis, it has been found that there are two types of wire-side disconnection failures: “wire disconnection failure after molding” and “wire disconnection failure of lead crimp after reflow”. First, it is considered that the cause of wire disconnection failure after molding is stress due to vibration of the lead and stress due to hardening shrinkage of the resin. As shown in FIG. 1, when the resin is injected from the gate 33 (filling time is 10 seconds), the tip of the inner lead 4 vibrates up and down by the resin flow. This vibration causes the wire 19 to be stressed, and in particular, the pin near the gate is most susceptible to vibration stress. Further, since the resin is cured and contracted from a position far from the gate 33 toward the gate 33 (from the right to the left in the figure), a tensile force is applied to the wire 19 and the wire breaks from the lead side crimping portion having a relatively low bonding strength. Is considered to have occurred.

  Next, it is considered that the cause of the disconnection failure of the lead crimping portion after reflow is due to the difference between the expansion 36 of the lead frame and the expansion 35 of the resin. FIG. 2 shows a schematic diagram thereof. The physical properties of the cured resin greatly change at the glass transition point Tg (150 to 160 ° C.) of the resin. Particularly, the coefficient of thermal expansion α (= 1.4) is (α1) in the region (α2) above Tg and below (α1). The value is about 4 to 5 times. Since the temperature at the time of reflow is higher than the temperature of Tg, the wire 19 is damaged due to the expansion (α2) of the resin at the time of reflow, and a crack 37 enters a weak portion (portion A in FIG. 2). As shown in FIG. 5, the disconnection is caused by the difference 34 between the expansion 36 of the lead frame and the expansion 35 of the resin.

  If an alternative solder of Sn-based alloy having a high melting point is used due to lead-free soldering, the reflow temperature rises, so the amount of heat applied to the package increases, and in particular, the difference between the expansion of the lead frame and the expansion of the resin is promoted. Therefore, it has been found that among the above-mentioned wire disconnection failures, the disconnection failure of the lead-side crimped portion after reflow is particularly problematic.

  Here, this inventor evaluated the relationship between the thickness of Ag plating and a wire breakage. As a result, it has been clarified that wire breakage tends to occur unless the plating thickness is within a certain range. Analyzing the reason, if the plating thickness is too thin, it is possible that the area of the joint surface between Ag and Au cannot be secured sufficiently when crimping Au wire, and wire breakage may occur due to deformation of the wire due to thermal stress. . Further, if the Ag plating is made thicker than a certain thickness, the Ag plating surface is deformed more than necessary when the wire is crimped, and the bonding energy is absorbed. As a result, it is considered that sufficient bonding cannot be obtained, and the cross-sectional shape of the bonding surface is weak against pulling due to stress against thermal deformation of the gold wire.

  Furthermore, the disconnection defect of the lead side crimping part after reflow will be described from the side of the shape. FIG. 4 shows a cross-sectional view when the wire 19 is pressure-bonded to the Ag spot plating surface by the capillary 20. 4 is the tip of the capillary 20, the diameter of the tip is 170 μm, and the diameter of the Au wire 19 is 30 μm. In the drawing, the thickness of the lead frame 7 is 150 μm. As described above, the thickness of the Ag plating 38 varies from 1.5 μm to 10 μm for each Ag-plated lead frame, so it is difficult to specify the Ag plating thickness. Therefore, in the figure, it is assumed that the plating thickness, which is considered to cause disconnection failure, is relatively thick.

  When wire is crimped, since Ag is a relatively soft metal, the capillary 20 sinks into the surface of the Ag plating 38, and a part of the surface of the Ag plating 38 rises as shown in FIG. Then, the thickness of the Au wire 19 in the portion A in FIG. 4 becomes relatively thin, and the wire strength is weak. FIG. 5 shows a perspective view of the lead side crimping portion after bonding. In FIG. 5, the portion indicated by the A line is the portion A in FIG. After reflow, disconnection occurs from the portion A in FIG. 4 due to the difference between the expansion of the lead frame and the expansion of the resin. For reference, FIG. 7 shows a perspective view of the lead-side crimping portion with defective wire breakage after molding. The disconnection failure of the lead side crimping portion after reflow is disconnected so that the disconnected wire overlaps with the crimping portion. However, in the case of the wire disconnection failure of the lead side crimping portion after molding, the disconnected wire is disconnected so as to be separated from the crimping portion. As described above, it has been clarified as a result of the analysis by the present inventor that the cause is that a portion having weak wire strength is formed by the capillary 20 being recessed into a relatively thick Ag-plated surface.

  In recent years, the Ag plating thickness required for design has become as thin as several μm, and as a result of evaluating the variation in the thickness of the Ag plating surface, the current Ag plating process is the initial stage when handling a large number of objects to be plated. It is difficult to maintain the set plating thickness, and it has been found that when the plating thickness for each object to be plated is compared, it varies within the range of 1.5 μm to 10 μm. Therefore, the inventor of the present application tried to keep the maximum thickness within the range of 10 μm to 5 to 8 μm in order to suppress variations in Ag plating thickness for each lead frame. However, in the current Ag plating process, as described above, the maximum thickness is 10 μm, and it is difficult to keep the maximum thickness in the range of 5 to 8 μm. Therefore, it is considered that it is difficult to further reduce the plating thickness variation in the current Ag plating process.

  Therefore, in order to solve the above-mentioned problem that a portion with weak wire strength is formed, a new idea of using a metal that is harder than Ag and has a small variation in thickness is used for the metal layer adhered to the tip of the inner lead. In addition, as a result of evaluation and examination to adopt an optimum metal for minimizing the manufacturing cost, the present invention has been conceived.

  Next, the reason why the lead-side crimped portion after reflow can be prevented from being disconnected by forming the palladium metal layer on the tip of the inner lead as described above will be described from the viewpoint of the lead-side crimped portion shape.

  A cross-sectional view when the wire 19 is pressure-bonded to the surface of the Pd plating 10 by the capillary 20 is shown in FIG. The hatched portion in FIG. 8 is the tip of the capillary 20, the diameter of the tip is 170 μm, and the diameter of the Au wire 19 is 30 μm. When the wire 19 is crimped, since the Pd is a relatively hard metal, the capillary 20 is not so depressed compared to when the plated surface is Ag. Then, the thickness t of the Au wire 19 in the portion A in FIG. 8 can be sufficiently thick as compared with the portion A in FIG. 4, and the wire strength can be maintained. FIG. 9 shows a perspective view of the lead side crimping portion after bonding. In FIG. 9, the portion indicated by the A line is the portion A in FIG. It can be seen that the thickness of the gold wire is secured in FIG. 9 compared to FIG. After reflow, stress is applied in the direction of the arrow in FIG. 9 due to the difference between the expansion of the lead frame and the expansion of the resin. However, since there is no weak portion, there is no disconnection in which the disconnected wire overlaps with the crimping part as in Ag plating. The crimping force of the capillary 20 is as long as the wire thickness t is 10 μm or more when the lead frame 7 has a thickness of 150 μm, the Pd plating 10 has a minimum thickness of 0.02 μm, and a maximum of 0.15 μm. Disconnection does not occur at least.

  Next, the reason why the technical idea of the present invention of depositing and forming a Pd metal layer on a member to be connected can be applied to the thinning of the connecting member without being directly related to lead-free is described.

  As a result of evaluating the conditions in the representative invention of the present application, it was noted that the evaluation was based on the premise that the size of the package does not change. Here, as described above, the wire breakage is caused by the difference between the expansion of the lead frame and the expansion of the resin. Therefore, it is considered that the difference in expansion becomes more conspicuous as the package becomes larger as the number of pins increases. This is because the volume increases, the heat capacity increases, and the amount of heat applied to the resin during reflow also increases. In addition, since the number of pins is increased, the amount of heat flowing from the substrate through the pins during reflow also increases.

  Furthermore, even when the pitch is narrowed by chip shrink, a larger amount of heat is applied to the package than a package of the same size. Therefore, even for a package having the same number of pins, the package size is reduced due to chip shrink, and accordingly, the pad pitch of wire bonding is reduced and the wire diameter is also reduced. It is considered that it is necessary to make the plating thickness thinner as the wire becomes thinner due to chip shrink, that is, as the current wire diameter of 30 μm becomes thinner. This is because, in the future, it is considered that the variation in the plating thickness that can be realized by the current Ag spot plating process is too large and the bonding becomes unstable.

  That is, even if there is no change in the reflow temperature, an increase in the amount of heat applied to the package due to the increase in the number of pins and the narrowing of pitch associated with chip shrinking corresponds to an increase in the reflow temperature. Therefore, the technical idea of depositing and forming the Pd metal layer on the connected member can be applied without being directly related to lead-free because it can reduce the variation in metal thickness and increase the bonding strength.

  Although the technical idea is completely different from the invention described in the present application, there is a PPL (Pre-solder Plated Leadframe) process as a countermeasure that can realize lead-free. The PPL process is a process in which palladium metal having good connectivity is plated on the entire lead frame including the die bonding portion, inner leads, and outer leads before sealing. The PPL process can be made lead-free because the metal used for plating is palladium. Furthermore, the PPL process does not require the exterior plating process that has been performed after sealing, so that the assembly time can be shortened and the entire assembly process can be automated by omitting solder plating of the outer leads.

  However, since a local battery is formed by the potential difference between the material of the frame material and the Pd metal, there is a risk of corrosion, and it is impossible to use an Fe-based frame such as 42 alloy (42Ni-Fe) alloy as the frame material, Limited to copper alloys. However, it is possible to use an Fe-based frame by placing the barrier metal between the Pd metal layer, but the material of the cross section is exposed when the dam bar cut or lead tip is cut in the actual assembly process. Since corrosion is intensively accelerated and the manufacturing process becomes complicated, it is disadvantageous in terms of manufacturing costs. In addition, since the outer leads are plated from the frame state, it is possible to contaminate the outer lead surfaces and deteriorate the solder wettability during board mounting in the deburring operation to remove resin burrs generated by sealing. It will be high. Furthermore, since palladium is a metal harder than lead-based solder, there also arises a problem that if the outer lead is formed after plating, peeling of the plating occurs.

  Therefore, even if the Pd plating process as described above is adopted as a means for solving the wire disconnection prevention which is the subject of the present invention, it is possible to reduce the difference in plating thickness for each object to be plated. However, it is needless to say that the above-mentioned disadvantages are inappropriate as a means for solving the problem.

  In addition, the inventor of the present application conducted a known example investigation from the viewpoint of “Pd plating on the lead frame” when applying. As a result, in Japanese Patent Laid-Open No. 11-40723 (Patent Document 4) and Japanese Patent Laid-Open No. 11-220084 (Patent Document 5), at least a part or all of the lead including the outer lead is plated with a Pd (palladium) metal. An invention has been proposed. Japanese Patent Laid-Open No. 10-284666 (Patent Document) discloses an invention in which all the leads are plated with a Pd (palladium) metal, with the primary objective of eliminating the need for an exterior plating process and enabling automation of the entire assembly process. 6), Japanese Patent Laid-Open No. 10-298798 (Patent Document 7) and Japanese Patent Laid-Open No. 10-18056 (Patent Document 8) have been proposed, and an Au-Ag compound is further formed on the outermost surface of the Pd (palladium) metal layer. Japanese Patent Laid-Open No. 11-8341 (Patent Document 9) has been proposed from the viewpoint of applying gold plating.

  The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.

  According to the present invention, it is possible to provide an LSI package compatible with lead-free, particularly an LSI package using a lead-free alternative solder having a melting point higher than that of a lead-based solder, and can improve assembly yield and reliability. It becomes possible. Further, it is possible to provide an LSI package that can cope with an increase in the number of pins or an increase in the size of the package and a reduction in the thickness of the wire due to chip shrink, and it is possible to improve the assembly yield and the reliability.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  The semiconductor integrated circuit device of this embodiment is a semiconductor integrated circuit device in which the tip of the inner lead is spot-plated with palladium and the outer lead is plated with Sn—Ag alloy.

  In this embodiment, 208 pins and a package size of 28 mm square are listed as an example.

  FIG. 10 shows four lead frame repeating units used in the semiconductor integrated circuit device. Needless to say, the number of repeating units is not limited to four. The material is a Cu alloy in this embodiment, but may be an iron-based lead frame such as 42Ni-Fe. This is because, in this embodiment, the entire palladium plating is not performed, so that local batteries are not generated on the outer leads, which is a problem with the entire palladium plating.

  FIG. 11 shows an enlarged view of one lead frame 7 in which the inner lead 4 is plated with palladium 1. The tab (die pad) 2 is a so-called small tab, and the area of the chip mounting surface is set smaller than the area of the main surface of the semiconductor chip mounted thereon. By using a small tab, it is possible to prevent the risk of reflow cracks. In this embodiment, it is a small tab, but it may be a cross tab method (a method having only the width of the suspension lead 3) or a normal tab. In this embodiment, the die pad 2 is not palladium plated, but the die pad 2 may be palladium plated.

  FIG. 12 shows an A-B cross-sectional view of an enlarged view of the lead frame 7 of FIG. A palladium plating 1 is applied to the tip of the lead. The portion to be plated with palladium may be at least as large as the wire bonding portion is spot-plated. When the plating is performed, the rear surface of the lead frame 7 and the portion other than the tip of the lead are masked with an insulating material and electrolytic plating is performed. Therefore, in addition to the minimum required plating of the surface of the inner lead tip described later, plating is also applied in the thickness direction. The minimum required plating area will be described by taking as an example the case of wire bonding using an Au wire wire 19 having a wire diameter of 30 μm. As shown in FIG. 19, the minimum required area 21 for spot plating includes a crimping width a and a crimping length b. In this embodiment, both a and b are at least 90 μm, and the position of the minimum required region 21 is 300 μm from the tip of the lead frame. Is coming.

  In addition, so-called tab lowering is performed such that the die pad 2 is positioned below the surface of the inner lead 4 by deforming the suspension lead 3. This is because the difference in resin injection speed between the top and bottom of the chip is eased during resin injection to prevent vibration.

  FIG. 13 shows the structure of palladium plating at the tip of the inner lead in this embodiment. The palladium plating consists of three layers. First, Ni plating 11 is applied to the inner lead as a base plating, then palladium plating 10 is applied thereon, and finally Au flash plating 9 is applied to improve corrosion resistance. The specific thickness of each layer in this example is 150 μm for the inner lead thickness, 1.0 μm for Ni plating, 0.15 μm for palladium plating, and about 1 nm for Au flash plating.

  The die bonding process will be described with reference to FIG. FIG. 14 is a sectional view taken along the line CD of FIG. The lead frame 7 after the tab is lowered is placed on the stage 16 and brought into contact with the lower surface of the die pad 2. The dispenser 13 in which the adhesive material 15 for die bonding is placed in the syringe 12 is positioned above the die pad, and the adhesive material 15 is attached to the upper surface of the die pad. Here, the adhesive 15 uses a conductive paste (an organic resin containing silver powder or carbon) for semiconductor devices with low power consumption. The characteristics required for the die-bonding material are good heat conductor characteristics, solder wettability with the film of the semiconductor element and the lead frame 7, and the heat of the solder due to the temperature difference between when the semiconductor device is used and when it is not used. This is because the conductive paste is effective in terms of fatigue characteristics. In addition, since the present invention aims to reduce Pb, metal solder mainly composed of Pb, which is usually used in power devices, is not used. However, this does not mean that metal solder is not used, and any lead-free solder can be used. However, it goes without saying that in the case of another representative invention without the viewpoint of lead-free, a metal solder mainly composed of Pb may be used. The next step will be described with reference to FIG. After the semiconductor chip 18 is moved by the collet 17 above the lead frame to which the adhesive material 15 is adhered, the chip is fixed to the chip fixing position. The shape of the collet 17 is a quadrangular pyramid as shown in FIG. 15, and the collet 17 and the semiconductor chip 18 are brought into close contact with the collet 17 by vacuum suction.

  The wire bonding process will be described with reference to FIG. After the die bonding process, the lower surface of the chip 18 and the lower surface of the inner lead 4 are fixed to the stage 16. In the stage 16, a part for storing the die pad 2 such as a notch is provided in advance. After fixing, the capillary 20 is bonded from the pad on the chip 18 onto the inner lead 4. FIG. 17 shows an enlarged view of the wire bonding portion. A schematic diagram of the shape of the crimping part after wire bonding is shown in FIG. In the present invention, the wire diameter d is 30 μm, the crimping width W is 105 μm at the maximum, and the crimping length is also 105 μm at the maximum. As a result of the inventor's evaluation, it is possible to obtain a good crimped state if the relationship between L, W and d is within the range of 1.5 ≦ W / d ≦ 3.5 and 1.5 ≦ L / d ≦ 3.5. It is clear.

  The lead frame 7 after the completion of the above-described wire bonding process is as shown in FIG. 20, and then resin sealing is performed in a molding process. In the molding step, the lead frame 7 is sandwiched between the sealing molds 22 and the resin 24 is poured from the resin injection port 23. In this embodiment, the pouring speed is set so that the filling time is 10 seconds. When pouring, the resin needs to be poured at the same speed above and below the lead frame 7. This is because the vibration width of the lead frame 7 is made as small as possible during molding to reduce the stress applied to the wire 19 and prevent wire breakage.

  FIG. 22 shows a state where the outer lead 5 is subjected to exterior plating after the resin sealing, and the exterior plating is completed. In this embodiment, the metal used for the exterior plating is an alloy obtained by adding Cu and / or Bi or both to a Sn—Ag metal. This is because Pb reduction is realized and reflow mounting with a high reflow temperature is assumed. Therefore, it goes without saying that not only the above alloy but also an alloy of Zn, In, Sb, etc. and Sn or Sn-based alloy may be used. In the case of reflow mounting, there are soldering solders with different mounting temperatures such as Sn-Ag, Sn-Zn, and Sn-Bi. At present, Sn-Ag metal has a melting point higher than that of Pb-containing solder. However, in other embodiments, the exterior plating uses lead-based solder. This is because the outer plating need not be limited to lead-based solder when attention is paid to increasing the connection strength between the inner lead 4 and the wire 19 by plating the inner lead 4 with palladium.

  There is a step of forming the outer lead 5 after the exterior plating is completed. First, as shown in FIG. 23, the resin sealing body is sandwiched and fixed at the base of the outer lead 5, and the outer lead 5 is formed by the punch 25. After molding, as shown in FIG. 24, the tip of the outer lead 5 is cut and molded by moving the die from below.

  FIG. 25 is a schematic diagram of the finished product in this example, FIG. 27 is a perspective view of the schematic diagram, and FIG. 26 is a cross-sectional view taken along line EF in FIG. Although the number of pins is 208, in order to avoid complication, the number of pins is omitted in FIG. The shape of the resin encapsulant is dropped at one corner and imprinted with a mark to ensure the directionality of the package during handling during mounting. The specific dimensions of the finished product in this example are as follows: the size D of the resin sealing body is 28 mm square, the external dimensions of the semiconductor package including the outer leads 5 are 30.6 ± 0.2 mm, and the maximum height is 3.56 mm. is there. The lead pitch p is 0.5 mm, the width w of each lead is 0.2 mm, and the thickness t is 0.15 mm. The length a in the horizontal direction from the resin sealing body to the outer lead tip is 1.3 mm, and the length k of the bent outer lead tip is 0.5 mm.

  The process of mounting on a wiring board will be described with reference to FIGS. A solder paste 28 is applied to a footprint 29 larger than the previous mounting surface of the outer lead 5. After application, the package 31 is placed from above and mounted by applying heat. Reflow methods include vapor phase reflow, air reflow, and infrared reflow. In the embodiment, the reflow temperature is 255 ° C., which is about 20 ° C. higher than the reflow temperature of 235 ° C. of ordinary Sn—Pb solder. This is to cope with the high melting point of the solder. The specific size of the footprint 29 of the wiring board 30 is such that the width a is 0.20 to 0.25 mm and the length b is 1.3 mm.

  This is because, within this size range, even if the position of the package is slightly shifted at the time of placement, self-alignment is performed by reflow, and there is no problem due to a shift in the mounting position.

  In the above-described embodiments, the case where the present invention is applied to manufacture a QFP has been described. However, the present invention is not limited to the QFP, and can be applied to a surface mount package such as QFN or QFJ. It can be applied to all packages that have wire connection parts such as Small Outline Non-leaded packages that are connected to leads with wires. Further, in the embodiment, the connection strength of the portion where the wire as the connection member is crimped and connected to the inner lead as the connection member is improved, but the connection member is not limited to the wire, and the connection member is also limited to the lead. Absent. For example, as shown in the schematic cross-sectional view of FIG. 30, the lead as the connection member 42 is crimped and connected to the semiconductor chip 39 in a chip size package or the like in which an insulating material such as polyimide tape 43 is used as the base material and the substrate is mounted with solder balls. The present invention can also be applied to the case where Pd plating is applied to the pad 40 that is a portion to be applied. In other words, the present invention can be applied to the improvement of the connectivity and reliability of the connection parts in semiconductor products.

It is a figure of the generation | occurrence | production mechanism of the wire disconnection defect after a mold. It is a figure of the crack generation mechanism of the lead side crimping part after reflow. It is a figure of the disconnection generation | occurrence | production of the lead side crimping | compression-bonding part after reflow. It is an enlarged view at the time of wire crimping of wire bonding to the Ag plating surface. It is a perspective view of the wire crimping | compression-bonding part of the wire bonding to Ag plating surface. It is a figure of the wire disconnection after reflow of Ag plating. It is a figure of the wire disconnection after resin hardening shrinkage | contraction of Ag plating. It is an enlarged view at the time of wire crimping of wire bonding to a Pd plating surface. It is a perspective view of the wire crimping | compression-bonding part of the wire bonding to a Pd plating surface. It is a top view of the lead frame which is one Example of the present invention. 1 is an enlarged plan view of a lead frame that is one embodiment of the present invention. FIG. FIG. 12 is a cross-sectional view taken along the line A-B in FIG. 11. It is Pd plating detailed sectional drawing of the inner lead front-end | tip. It is a figure of adhesive application of the die bonding process using this frame. It is a figure of chip mounting of the die bonding process using this frame. It is a figure of the wire bonding process using this frame. It is a Pd plating part enlarged view of the wire bonding process using this frame. It is a figure of the shape of the Au wire crimping part at the time of wire bonding to the Pd plating surface. It is a perspective view of the wire bonding crimping | compression-bonding part to a Pd plating surface. It is an enlarged plan view after completion of wire bonding of the lead frame which is one embodiment of the present invention. It is sectional drawing of the resin sealing process which uses this flame | frame. It is sectional drawing after outer lead plating which uses this flame | frame. It is a figure of the bending process which uses this frame. It is a figure of lead tip alignment processing using this frame. It is a finished product top view of a package using this frame. It is EF sectional drawing of the finished product of the package which uses this flame | frame. It is a finished product perspective view of a package using this frame. It is a board | substrate mounting drawing of this package. It is a top view of the mounting board after board mounting of this package. FIG. 6 is a schematic cross-sectional view of a Fan-In type CSP having a peripheral pad structure.

Explanation of symbols

1: Inner lead tip plating 2: Die pad 3: Suspended lead 4: Inner lead 5: Outer lead 6: Dam bar 7: Lead frame 8: Dam bar position 9: Au (gold) flash plating 10: Pd (palladium) plating 11: Ni (Nickel) plating 12: Syringe 13: Dispenser 14: Nozzle 15: Adhesive 16: Stage 17: Collet 18: Semiconductor chip 19: Au (gold) wire 20: Capillary 21: Minimum required area 22: Sealing mold 23 : Resin injection port 24: Resin 25: Punch 26: Die 27: Heater 28: Solder paste 29: Footprint 30: Wiring substrate 31: Semiconductor package 32: Wiring 33: Gate 34: Expansion difference 35: Resin expansion 36: Lead Expansion of frame 37: Crack 38: Ag (silver) plating 39: Semiconductor chip 40: Pad 41: Insulating resin 42: Connection member 43: Tape base material

Claims (1)

A conductive connecting member;
A connected member in which a palladium layer is provided in a portion to which the connecting member is crimped;
A semiconductor integrated circuit device having a resin for sealing the crimping portion,
A semiconductor integrated circuit device, wherein a thickness of a crimping portion of the connection member is 10 μm or more.