JP2006339317A - 表面実装型半導体装置 - Google Patents
表面実装型半導体装置 Download PDFInfo
- Publication number
- JP2006339317A JP2006339317A JP2005160683A JP2005160683A JP2006339317A JP 2006339317 A JP2006339317 A JP 2006339317A JP 2005160683 A JP2005160683 A JP 2005160683A JP 2005160683 A JP2005160683 A JP 2005160683A JP 2006339317 A JP2006339317 A JP 2006339317A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- sealing resin
- electrode pad
- semiconductor device
- cut
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05555—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48647—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
【解決手段】互いに対向する第1及び第2の表面を有すると共に、中央部に切り込み部を有し、前記第2の表面にボールランド、接続端子及びこれらを接続する配線回路とを有する支持基板11と、少なくとも中央部に電極パッド17が設けられた半導体素子16であって、前記電極パッドが前記切り込み部内に位置し、前記半導体素子16の幅が前記切り込み部の長手方向の長さより短く、前記第1の表面に載置された半導体素子16と、前記第2の表面において前記電極パッドと前記接続端子とを電気的に接続する金属細線18と、前記第1の表面において前記半導体素子を封止するように設けられた第1の封止樹脂20と、前記第2の表面において前記切り込み部12を封止するように設けられた第2の封止樹脂21とを具備する。
【選択図】図11
Description
図1乃至図11は、第1の実施例による表面実装型半導体装置10の各部品構造を示している。図1及び図2は、それぞれ半導体素子を実装する基板部品11の上面図及び下面図である。基板部品11は従来と同様にガラスエポキシ材もしくはポリイミド材等からなり、基板部品11の中央部には、細長形状の切り込み部(スリット)12が設けられている。前記切り込み部12は、封止樹脂材が裏面に回り込むように、第1の表面、即ち、上面において樹脂封止される半導体素子の端部を越える長さの細長形状を有している。
図12乃至図14は第2の実施例による表面実装型半導体装置10における前記基板部品11の下面側を示し、基本的には実施例1と同様であるので、共通する部分については省略し、特徴的な部分のみについて説明する。
(9)露出した各電極パッドと前記配線回路に接続された前記接続端子とを細線により電気的に接続する。
Claims (5)
- 互いに対向する第1及び第2の表面を有すると共に、中央部に切り込み部を有し、前記第2の表面にボールランド、接続端子及びこれらを接続する配線回路とを有する支持基板と、
少なくとも中央部に電極パッドが設けられた半導体素子であって、前記電極パッドが前記切り込み部内に位置し、前記半導体素子の幅が前記切り込み部の長手方向の長さより短く、前記切り込み部の両端が前記半導体素子の端部より外に位置するよう前記第1の表面に載置された半導体素子と、
前記第2の表面において前記電極パッドと前記接続端子とを電気的に接続する金属細線と、
前記第1の表面において前記半導体素子を封止するように設けられた第1の封止樹脂部材と、
前記第2の表面において前記切り込み部を封止するように設けられた第2の封止樹脂部材とを具備することを特徴とする表面実装型半導体装置。 - 前記支持基板は周辺部に少なくとも1つの他の切り込み部を有すると共に、前記半導体素子は周辺部に設けられた電極パッドを具備し、前記第2の表面において前記他の切り込み部を封止するように設けられた少なくとも1つの第3の封止樹脂部材をさらに有することを特徴とする請求項1記載の表面実装型半導体装置。
- 前記各切り込み部はそれぞれ前記電極パッド、前記金属細線及び前記接続端子を含むように封止樹脂で封止されていることを特徴とする請求項1又は2記載の表面実装型半導体装置。
- 前記少なくとも1つの他の切り込み部は前記半導体素子の端部を越える長さを有することを特徴とする請求項3記載の表面実装型半導体装置。
- 前記少なくとも1つの第3の封止樹脂部材は前記半導体素子の端部よりも長いか又は短いことを特徴とする請求項1乃至4のいずれか1つ記載の表面実装型半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005160683A JP2006339317A (ja) | 2005-05-31 | 2005-05-31 | 表面実装型半導体装置 |
TW095118431A TW200703593A (en) | 2005-05-31 | 2006-05-24 | Surface-mounted semiconductor device and manufacturing method thereof |
KR1020060048642A KR100743319B1 (ko) | 2005-05-31 | 2006-05-30 | 표면 실장형 반도체 장치 및 그 제조 방법 |
US11/442,996 US20060270118A1 (en) | 2005-05-31 | 2006-05-31 | Surface mount type semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005160683A JP2006339317A (ja) | 2005-05-31 | 2005-05-31 | 表面実装型半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006339317A true JP2006339317A (ja) | 2006-12-14 |
Family
ID=37463965
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005160683A Pending JP2006339317A (ja) | 2005-05-31 | 2005-05-31 | 表面実装型半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20060270118A1 (ja) |
JP (1) | JP2006339317A (ja) |
KR (1) | KR100743319B1 (ja) |
TW (1) | TW200703593A (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000156435A (ja) * | 1998-06-22 | 2000-06-06 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2001053094A (ja) * | 1999-08-10 | 2001-02-23 | Towa Corp | 樹脂封止方法及び装置 |
JP2002033418A (ja) * | 2000-07-17 | 2002-01-31 | Nec Kyushu Ltd | 半導体装置およびその製造方法 |
JP2004203983A (ja) * | 2002-12-24 | 2004-07-22 | Matsushita Electric Works Ltd | W−bga用半導体封止材料及びw−bga型半導体装置 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3883531B2 (ja) | 1994-12-20 | 2007-02-21 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2002026179A (ja) * | 2000-07-04 | 2002-01-25 | Nec Kyushu Ltd | 半導体装置およびその製造方法 |
JP2001326238A (ja) * | 2000-05-17 | 2001-11-22 | Toshiba Corp | 半導体装置、半導体装置の製造方法、樹脂封止金型及び半導体製造システム |
JP2003007971A (ja) * | 2001-06-25 | 2003-01-10 | Toshiba Corp | 半導体装置 |
US6963142B2 (en) * | 2001-10-26 | 2005-11-08 | Micron Technology, Inc. | Flip chip integrated package mount support |
US20030100174A1 (en) * | 2001-11-28 | 2003-05-29 | Walsin Advanced Electronics Ltd | Process for making a ball grid array semiconductor package |
SG118103A1 (en) * | 2001-12-12 | 2006-01-27 | Micron Technology Inc | BOC BGA package for die with I-shaped bond pad layout |
US6984545B2 (en) * | 2002-07-22 | 2006-01-10 | Micron Technology, Inc. | Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask |
US20040061222A1 (en) * | 2002-09-30 | 2004-04-01 | Jin-Chuan Bai | Window-type ball grid array semiconductor package |
US6879030B2 (en) * | 2002-09-30 | 2005-04-12 | Ultratera Corporation | Strengthened window-type semiconductor package |
JP2004128155A (ja) * | 2002-10-01 | 2004-04-22 | Renesas Technology Corp | 半導体パッケージ |
KR100621991B1 (ko) * | 2003-01-03 | 2006-09-13 | 삼성전자주식회사 | 칩 스케일 적층 패키지 |
US20040251532A1 (en) * | 2003-06-10 | 2004-12-16 | Potter Chien | Chip package structure |
KR100587081B1 (ko) * | 2004-06-30 | 2006-06-08 | 주식회사 하이닉스반도체 | 개선된 열방출 특성을 갖는 반도체 패키지 |
JP2006073825A (ja) * | 2004-09-02 | 2006-03-16 | Toshiba Corp | 半導体装置及びその実装方法 |
TWI241697B (en) * | 2005-01-06 | 2005-10-11 | Siliconware Precision Industries Co Ltd | Semiconductor package and fabrication method thereof |
-
2005
- 2005-05-31 JP JP2005160683A patent/JP2006339317A/ja active Pending
-
2006
- 2006-05-24 TW TW095118431A patent/TW200703593A/zh not_active IP Right Cessation
- 2006-05-30 KR KR1020060048642A patent/KR100743319B1/ko not_active IP Right Cessation
- 2006-05-31 US US11/442,996 patent/US20060270118A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000156435A (ja) * | 1998-06-22 | 2000-06-06 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2001053094A (ja) * | 1999-08-10 | 2001-02-23 | Towa Corp | 樹脂封止方法及び装置 |
JP2002033418A (ja) * | 2000-07-17 | 2002-01-31 | Nec Kyushu Ltd | 半導体装置およびその製造方法 |
JP2004203983A (ja) * | 2002-12-24 | 2004-07-22 | Matsushita Electric Works Ltd | W−bga用半導体封止材料及びw−bga型半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US20060270118A1 (en) | 2006-11-30 |
KR20060125537A (ko) | 2006-12-06 |
TWI311801B (ja) | 2009-07-01 |
TW200703593A (en) | 2007-01-16 |
KR100743319B1 (ko) | 2007-07-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7547963B2 (en) | Semiconductor device and its wiring method | |
JP5400094B2 (ja) | 半導体パッケージ及びその実装方法 | |
KR100984132B1 (ko) | 반도체 패키지 및 그 실장방법 | |
KR20040080955A (ko) | 반도체 모듈의 몰딩에 관한 제조 방법 및 이에 사용되는인쇄회로기판 | |
KR20150047168A (ko) | 반도체 패키지 | |
US6774500B1 (en) | Substrate for semiconductor device, semiconductor chip mounting substrate, semiconductor device and method of fabrication thereof, and circuit board, together with electronic equipment | |
JP5378643B2 (ja) | 半導体装置及びその製造方法 | |
JP2006339317A (ja) | 表面実装型半導体装置 | |
KR20080020137A (ko) | 역피라미드 형상의 적층 반도체 패키지 | |
KR100922370B1 (ko) | 반도체 패키지 제조용 자재 | |
US7635642B2 (en) | Integrated circuit package and method for producing it | |
JP2007287820A5 (ja) | ||
JP2004281486A (ja) | 半導体パッケージ及び同パッケージを用いた半導体装置 | |
JP5804762B2 (ja) | 圧電デバイス | |
KR100907730B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
KR100922372B1 (ko) | 반도체 패키지 제조 방법 | |
JP2003068922A (ja) | 半導体チップ搭載基板及びそれを用いた半導体装置 | |
JP2015032705A (ja) | モールドパッケージ | |
KR20020028473A (ko) | 적층 패키지 | |
JPH06216492A (ja) | 電子装置 | |
JPH10214934A (ja) | 半導体装置及びその製造方法 | |
JP2005197438A (ja) | Bga型半導体装置 | |
JP2018125436A (ja) | 電子装置 | |
JPH09172042A (ja) | 半導体装置 | |
JP2007150078A5 (ja) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080408 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20090210 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100416 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100420 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100817 |