JP2006339296A - Manufacturing method for printed-wiring board with capacitor circuit and printed-wiring board obtained by its manufacturing method and multilayer printed-wiring board with built-in capacitor circuit using its printed-wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing technique for a printed-wiring board in which a dielectric layer except a capacitor circuit part is removed as much as possible, without requiring a complicate manufacturing method. <P>SOLUTION: The capacitor-circuit forming layer of a lower-electrode forming layer/a dielectric layer/an upper-electrode forming layer is formed on the surface of a base material 2, the upper-electrode forming layer positioned on an external layer is etched and worked, and the dielectric layer 4 is exposed in a region excepting a circuit section such as the upper-electrode circuit 9. An etching resist layer is left on the surface of the upper-electrode circuit 9 or the like, the exposed dielectric layer 4 is roughly and physically removed, and the remaining dielectric layer 4 is etched and removed. The etching resist layer left on the surfaces of the upper-electrode circuit 9 and other circuit sections is peeled, the etching resist layer for forming a lower electrode shape is formed, a second etching-resist pattern 10 is formed, a lower electrode circuit 11 is formed by an etching working, and the printed-wiring board 1 with a capacitor circuit is manufactured. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a printed wiring board, a printed wiring board obtained by the manufacturing method, and a multilayer printed wiring board including a built-in capacitor circuit using the printed wiring board.

  Conventionally, a multilayer printed wiring board incorporating a capacitor circuit (element) uses one or more of the insulating layers located in the inner layer as a dielectric layer, and the capacitor as an inner layer circuit located on both sides of the dielectric layer. Upper and lower electrodes have been formed and used. Therefore, such a capacitor circuit has been called a built-in capacitor circuit.

  For manufacturing a multilayer printed wiring board having such a built-in capacitor, a manufacturing method shown in FIGS. 5 to 7 has been studied by applying a general manufacturing process of a printed wiring board. That is, the inner layer core material 20 shown in FIG. 5A (in the figure, the lower electrode circuit 11 is formed on both surfaces of the base material 2), and the dielectric layer 4 using a high dielectric constant material on both surfaces is used. And the upper electrode forming layer (metal foil) 5 are bonded to each other, and a state as shown in FIG. 5B is expected.

  Then, the first conductive metal layer 6 located in the outer layer is processed to be the upper electrode circuit 9 of the capacitor by etching or the like, and the state shown in FIG. 6C is obtained. At this time, the dielectric layer in the region other than the circuit portion is exposed.

  Next, as shown in FIG. 6 (d), the prepreg 21 and the metal foil 22 are pasted on the upper electrode circuit 9 (in the drawing, the skeletal material included in the prepreg is omitted. The same applies throughout the book.) Then, the metal foil 22 located in the outer layer is processed into the outer layer circuit 23 by etching or the like, the necessary plating layer 24 is formed, the via hole 25 is formed, etc., as shown in FIG. A multilayer printed wiring board 30 having a built-in capacitor circuit is obtained.

  The manufacturing method of the multilayer printed wiring board provided with the built-in capacitor circuit shown in FIGS. 5 to 7 is obtained by diverting the normal manufacturing method of the multilayer printed wiring board as it is, and the dielectric layer is the entire surface of the multilayer printed wiring board. A dielectric layer is also present in the power supply line other than the capacitor circuit, the lower part of the signal transmission line, and the periphery thereof. Since this dielectric layer has a high dielectric constant, there has been a problem in that parasitic capacitance that impedes transmission of signal signals and the like occurs. In addition, there are many cases where it is impossible to embed other circuit elements such as inductors in this dielectric layer, and circuit design is usually subject to certain restrictions.

  However, when the above-described general printed wiring board manufacturing process is diverted to produce a multilayer printed wiring board having a built-in capacitor layer, both surfaces of the inner layer core material 2 shown in FIG. A great problem has occurred in bonding the dielectric layer 4 and the upper electrode forming layer 5 using materials. Generally, the filler content in the dielectric layer 4 generally exceeds 80 wt%, and since the amount of resin is small, there is little resin flow at the time of bonding, and the gap between the lower electrodes can be embedded well. Therefore, the ideal state as shown in FIG. In addition, the multilayer printed wiring board obtained by the above manufacturing method has a dielectric layer spreading over the entire surface, and it is not possible to leave the dielectric layer only at a necessary portion.

  Therefore, various methods have been studied by those skilled in the art in order to form the dielectric layer only at a necessary portion. For example, as disclosed in Patent Document 1, an insulating layer provided on the surface of the inner layer substrate is subjected to an opening treatment, and a high dielectric material is embedded in the portion, or as disclosed in Patent Document 2, a resin film is previously provided. A method of transferring the layer with capacitor circuit formed on the surface of the inner layer core material, as disclosed in Patent Document 3, a paste containing a dielectric filler is printed only on a necessary portion by a screen printing method, etc. The method has been adopted.

JP 09-116247 A JP 2000-323845 A Japanese Patent Laid-Open No. 08-125302

  However, in the inventions disclosed in Patent Documents 2 to 3, the state in which the dielectric layer remains in the unnecessary part can be eliminated, but the film thickness uniformity of the dielectric layer is lacking, and the positional accuracy during transfer or screen printing is reduced. There was a problem.

A capacitor is required as a basic quality to have as much electric capacity as possible. The capacitance (C) of the capacitor is calculated from the equation C = εε ₀ (A / d) (ε ₀ is the dielectric constant of vacuum). In particular, due to the recent trend of light and thin electronic and electrical equipment, the same demands will be made on printed wiring boards, and it is not possible to take a large capacitor electrode area within a certain printed wiring board area. It is almost impossible and it is clear that there is a limit to the improvement in terms of surface area (A). Accordingly, in order to increase the capacitance of the capacitor, it is necessary to reduce the thickness (d) of the dielectric layer if the surface area (A) of the capacitor electrode and the relative dielectric constant (ε) of the dielectric layer are constant. In addition, lack of film thickness uniformity is not preferable because of the large variation in quality as a capacitor.

  In addition, when there is a problem with positional accuracy during transfer or screen printing, the position between the upper electrode and the lower electrode formed at the corner is displaced, and the effective area of the surface area (A) that affects the capacitance of the capacitor is As a result, the capacitor performance as designed cannot be obtained, and the product quality is out of specification.

  Therefore, without requiring a complicated manufacturing method, it is excellent in film thickness uniformity of the dielectric layer and the positional accuracy of the capacitor circuit, and a printed wiring board manufacturing technique in which the dielectric layer is removed as much as possible except for the capacitor circuit part. In addition, there has been a demand for a multilayer printed wiring board having a built-in capacitor circuit.

  Thus, as a result of diligent research, the inventors of the present invention have come up with a method for manufacturing a printed wiring board incorporating the capacitor circuit according to the present invention. Since this manufacturing method can employ the most common conventional printed wiring board manufacturing process, it requires no significant capital investment and has great industrial merit.

  The manufacturing method of a printed wiring board provided with the capacitor circuit which concerns on this invention comprises the following process A-process H, It is characterized by the above-mentioned.

Step A: Lamination step of providing a capacitor circuit forming layer having a three-layer structure of lower electrode forming layer / dielectric layer / upper electrode forming layer on the surface of the substrate.
Step B: A first etching resist pattern forming step in which an etching resist layer is formed on the upper electrode forming layer located in the outer layer to form a first etching resist pattern.
Step C: An upper electrode formation step of forming a first etching resist pattern and then etching to expose a dielectric layer in a region other than the upper electrode circuit and other circuit portions.
Step D: A first dielectric layer removing step of physically removing the exposed dielectric layer while leaving the etching resist layer on the surfaces of the upper electrode circuit and other circuit portions.
Step E: a second dielectric layer that removes the dielectric layer that remains even if the exposed dielectric layer in regions other than the upper electrode circuit and other circuit portions is physically removed by the first dielectric layer removing step. Removal process.
Step F: A first etching resist layer peeling step for peeling off the etching resist layer left on the surfaces of the upper electrode circuit and other circuit portions.
Step G: A second etching resist pattern forming step of forming an etching resist layer for forming a lower electrode shape and forming a second etching resist pattern.
Step H: A second etching step of forming a second etching resist pattern and then performing an etching process to form a lower electrode circuit to obtain a printed wiring board including a capacitor circuit.

  And in the manufacturing method of a printed wiring board provided with the capacitor circuit according to the present invention, a capacitor circuit forming layer (lower electrode forming layer / dielectric layer / upper electrode forming layer) having a three-layer structure on the surface of the base material in the laminating step Is formed by bonding a lower electrode forming layer of a capacitor layer forming material having a three-layer structure (lower electrode forming layer / dielectric layer / upper electrode forming layer) to a substrate.

  Further, in the method of manufacturing a printed wiring board provided with the capacitor circuit according to the present invention, a capacitor circuit forming layer (lower electrode forming layer / dielectric layer / upper electrode forming layer) having a three-layer structure on the surface of the base material in the laminating step Is formed by forming a lower electrode forming layer on the surface of the substrate, forming a dielectric layer on the surface of the lower electrode forming layer, and further forming an upper electrode forming layer (hereinafter referred to as “sequential laminating method”). It is also possible to adopt.

  In the above-described sequential lamination method, the lower electrode formation layer can form a metal layer on a polyimide resin by an aerosol deposition method.

  Further, in the above-described sequential lamination method, the lower electrode forming layer is provided with a seed layer made of any one of copper, nickel, cobalt, or an alloy thereof by sputtering deposition on a base material, and then, by electrolytic method, copper, nickel, It can also be obtained by precipitation growth of any nickel alloy.

  In the above-described sequential lamination method, the lower electrode forming layer is provided with a seed layer made of any of copper, nickel, cobalt, or an alloy thereof by a direct metallization method on a polyimide resin base material, and then an electrolytic method. It can also be obtained by precipitation growth of any of copper, nickel and nickel alloys.

  Further, in the above-described sequential lamination method, the lower electrode forming layer can be obtained by casting a polyimide resin as a base material on the surface of the metal foil to have the lower electrode forming layer on the base surface.

  Furthermore, in the above-described sequential lamination method, the dielectric layer can be formed using either a sputtering vapor deposition method or an aerosol deposition method.

  In the sequential lamination method described above, either the sputtering vapor deposition method or the aerosol deposition method can be used for forming the upper electrode formation layer.

  The printed wiring board obtained by the method of manufacturing a printed wiring board having the above capacitor circuit has no dielectric layer in the extra part, and there is no residual dielectric in the part from which the dielectric layer is removed. Become.

  Furthermore, a multilayer printed wiring board having a high-quality built-in capacitor circuit can be obtained by using a printed wiring board having the above-described capacitor circuit as an inner layer core material in a normal multilayer printed wiring board manufacturing process.

  The manufacturing method of a printed wiring board provided with a capacitor circuit according to the present invention uses a combination of a physical removal step and a chemical removal (etching removal) step in removing unnecessary portions of the dielectric layer in the step. . By employing a manufacturing method having such characteristics, the dielectric layer can be satisfactorily removed at an unnecessary portion of the dielectric layer without damaging the circuit. As a result, even if the signal circuit is formed in the same plane or adjacent plane as the capacitor circuit is formed, the parasitic capacitance that obstructs the transmission of the high-frequency signal signal is small, and other circuit elements such as inductors are embedded. This also makes it possible to greatly relax the constraint conditions of circuit design. Therefore, the printed wiring board including the capacitor circuit obtained by this manufacturing method is of extremely high quality. Furthermore, the multilayer printed wiring board provided with the built-in capacitor circuit obtained by using the printed wiring board provided with this capacitor circuit as an inner layer core material becomes of high quality.

<Method of manufacturing printed wiring board including capacitor circuit>
The manufacturing method of a printed wiring board provided with the capacitor circuit which concerns on this invention comprises the following process A-process H, It is characterized by the above-mentioned. In particular, it is characterized in that physical removal and chemical removal (etching removal), which will be described later, are combined in removing unnecessary portions of the dielectric layer. Hereafter, it demonstrates for every process mainly using FIGS. 1-3.

Step A: In this laminating step, as shown in FIG. 1A, a capacitor circuit forming layer 6 having a three-layer structure of a lower electrode forming layer 3 / dielectric layer 4 / upper electrode forming layer 5 is formed on the surface of a substrate 2. It is a process of providing, and there is no particular limitation on the formation method. And the capacitor circuit formation layer 6 can also be provided in the single side | surface or both surfaces of the base material 2. FIG. In the drawings used for explanation, the case of one side is used as an example.

  However, in providing a three-layer structure of a capacitor circuit forming layer (lower electrode forming layer / dielectric layer / upper electrode forming layer) on the surface of the substrate, it is preferable to employ the following method. For the production of this capacitor circuit formation layer, two types of production methods are mainly employed. Hereinafter, the “capacitor circuit formation layer manufacturing method I” and the “capacitor circuit formation layer manufacturing method II” will be described separately.

Capacitor circuit forming layer manufacturing method I: This capacitor circuit forming layer manufacturing method preliminarily uses a capacitor layer forming material 6 having a three-layer structure (lower electrode forming layer 3 / dielectric layer 4 / upper electrode forming layer 5). In this method, as shown in FIG. 4A, the lower electrode forming layer 3 of the capacitor layer forming material 6 is brought into contact with and bonded to the base material 2. At this time, although not shown in FIG. 4, it is also possible to provide an adhesive layer 7 as shown in FIG. 1 on the substrate surface.

  First, the “base material” will be described. The base material referred to here is a resin excellent in electrical insulation such as epoxy resin, polyimide resin, polyamide resin, and liquid crystal polymer, which is a base material used for manufacturing rigid printed wiring boards or flexible printed wiring boards. It is described as including all the concepts of film-like and layer-like ones whose raw materials are main ingredients. And regarding the shape of these base materials, there is no special limitation, such as a sheet form and a tape form. Furthermore, these base materials may contain skeleton materials such as glass cloth and glass nonwoven fabric. Moreover, when using a polyimide resin film etc. for a base material, it is also possible to provide an adhesive bond layer on the surface, and it is possible to use all the commercially available well-known adhesive agents. Accordingly, FIGS. 1 to 3 show a case where a polyimide resin film is used for the substrate 2 and an epoxy resin-based adhesive layer 7 is provided on the surface of the substrate 2 as an example having the most components.

  In the preliminary manufacture of the capacitor layer forming material 6 having a three-layer structure (lower electrode forming layer 3 / dielectric layer 4 / upper electrode forming layer 5), the dielectric layer 4 is formed on the surface of the metal foil used as the lower electrode forming layer 3. Then, the upper electrode forming layer 5 is provided on the surface of the dielectric layer 4. The metal foil used as the lower electrode formation layer 3 includes various copper foils, nickel foils, cobalt foils, nickel alloy foils (nickel-phosphorus alloy foils, nickel-cobalt alloy foils), nickel foils provided with nickel-phosphorus alloy layers, and the like. A metal foil can be used, and it may be appropriately selected and used in accordance with a method for forming a dielectric layer.

  The formation of the lower electrode forming layer 3 here is mainly intended to use a metal foil. Therefore, when the lower electrode formation layer 3 is a nickel layer, it is a layer formed of a pure nickel foil having a so-called purity of 99.9% (other unavoidable impurities) or more. In this case, the lower electrode formation layer 3 is a nickel alloy layer. When a nickel-phosphorus alloy composition is used, the phosphorus content is preferably 0.1 wt% to 11 wt%. The phosphorus component of the nickel-phosphorus alloy layer diffuses into the dielectric layer and can adhere to the dielectric layer if it is subjected to high temperature loads in the manufacturing process of the capacitor layer forming material and the normal printed wiring board manufacturing process. It is considered that the dielectric constant is deteriorated and the dielectric constant is also changed. However, a nickel-phosphorus alloy layer having an appropriate phosphorus content improves the electrical characteristics as a capacitor. When the phosphorus content is less than 0.1 wt%, it becomes the same as when pure nickel is used, and the significance of alloying is lost. On the other hand, when the phosphorus content exceeds 11 wt%, phosphorus segregates at the interface of the dielectric layer, the adhesiveness with the dielectric layer is deteriorated, and it becomes easy to peel off. Therefore, the phosphorus content is preferably in the range of 0.1 wt% to 11 wt%. In order to ensure more stable adhesion with the dielectric layer, a stable quality capacitor circuit can be obtained even if there is a certain variation in the process if the phosphorus content is in the range of 0.2 wt% to 3 wt%. Formation is possible. If the optimum range is pointed out, the phosphorus content is 0.25 wt% to 1 wt% to ensure the best adhesion with the dielectric layer and at the same time to ensure a good dielectric constant. The phosphorus content in the present invention is a value converted as [P component weight] / [Ni component weight] × 100 (wt%).

  The nickel foil and nickel alloy foil referred to in the present invention include all of the products obtained by the rolling method, the electrolytic method and the like. It is described as a concept including a composite foil provided with these nickel or nickel alloy layers in the outermost layer of the metal foil. For example, as a material constituting the metal substrate, a composite material having a nickel layer or a nickel alloy layer on the surface of the copper foil can be used.

  As long as such physical properties are provided, there is almost no deterioration in strength even after a high temperature processing process of 300 ° C. to 400 ° C. used in a printed wiring board manufacturing process using a fluororesin substrate, a liquid crystal polymer or the like as a substrate material. In addition, it is preferable that the crystal structure of the nickel foil and the nickel alloy foil referred to in the present invention has a crystal grain as fine as possible with improved strength. More specifically, it is preferable that the material is refined to an average crystal grain size of 0.5 μm or less and has physical properties with high mechanical strength.

  And it is preferable that the thickness of the lower electrode formation layer 3 is 1 micrometer-100 micrometers. If the thickness is less than 1 μm, the reliability as an electrode when a capacitor circuit is formed is remarkably lacking, and it is extremely difficult to form a dielectric layer on the surface. On the other hand, there is almost no practical requirement for a thickness exceeding 100 μm. Further, when the capacitor layer forming material 6 is manufactured by setting the thickness of the lower electrode forming layer 3 to 10 μm or less, handling becomes difficult. Therefore, it is preferable to use a metal foil with a carrier foil that is bonded to the carrier foil via a bonding interface as the metal foil that becomes the lower electrode forming layer 3. The carrier foil may be removed at a subsequent stage after processing into the capacitor layer forming material referred to in the present invention.

Next, the method for forming the dielectric layer 4 on the surface of the metal foil used as the lower electrode formation layer 3 is not particularly limited. For example, the dielectric layer 4 can be obtained through a high-temperature firing process at 600 ° C. to 700 ° C. using a sol-gel method. It is also possible to form the dielectric layer 4 having an arbitrary composition by the MOCVD method performed while heating the substrate 2. Alternatively, a resin solution containing a dielectric filler can be prepared, applied to the surface of the metal foil using a gravure coater, dried, and cured. However, it is preferable to employ a manufacturing method in a low temperature process such as a sputtering deposition method or an aerosol deposition method. This is because no high temperature load is applied, so that there is almost no change in physical properties of the metal foil used as the lower electrode formation layer 3 and the adhesion between the formed dielectric layer 4 and the lower electrode formation layer 3 is improved. The dielectric layer referred to here is a dielectric film having a perovskite structure, and is mainly a (Ba _1-x Sr _x ) TiO ₃ (0 ≦ x ≦ 1) film or BiZrO ₃ (0 ≦ x ≦ 1). ) A film or the like. Here, in the (Ba _1-x Sr _x ) TiO ₃ (0 ≦ x ≦ 1) film, when x = 0, it means the BaTiO ₃ composition, and when x = 1, it means the SrTiO ₃ composition. It will be a thing. Then, as the intermediate _composition, there are _{(Ba 0.7} Sr 0.3) TiO ₃ or the like.

  The dielectric layer formed by the oxide dielectric layer forming method according to the present invention preferably has a thickness of 20 nm to 1 μm. The thinner the dielectric layer, the higher the electric capacity. Therefore, the thinner the dielectric layer, the better. However, when the thickness of the dielectric layer is less than 20 nm, even if the above-described manganese, silicon, or the like is added to the dielectric layer, the effect of reducing the leakage current is lost, and dielectric breakdown occurs at an early stage, thus extending the life. I can't. On the other hand, if the electric capacity may be small, the thickness of the dielectric film may be large. However, when considering the required value such as the electric capacity of the capacitor circuit required in the market, the thickness of about 1 μm is considered as the upper limit.

  Furthermore, as an additive component in the dielectric layer, the oxide dielectric film contains one or more selected from manganese, silicon, nickel, aluminum, lanthanum, niobium, magnesium, tin, and segregates at the grain boundaries. Therefore, it is also preferable to block the leakage current flow path. Among these, it is preferable to use manganese. This manganese is considered to exist as manganese oxide inside the dielectric film, and it is assumed that it segregates at the grain boundary of the oxide dielectric film obtained by the sol-gel method, etc. The road blocking efficiency is increased. At this time, the amount of manganese contained in the oxide dielectric film is preferably 0.01 mol% to 5.00 mol%. When the amount of manganese is less than 0.01 mol%, the segregation of manganese on the crystal grain boundary of the obtained oxide dielectric film is insufficient, and a good leakage current reduction effect cannot be obtained. On the other hand, when the amount of manganese exceeds 5.00 mol%, manganese segregation to the crystal grain boundary of the obtained oxide dielectric film becomes excessive, the dielectric film becomes brittle and toughness is lost. Problems such as dielectric layer breakdown easily occur due to an etchant shower or the like when processing the electrode shape or the like. Further, when the amount of manganese is excessive, the growth of the oxide crystal structure in the production method described below tends to be suppressed. Therefore, by adopting a composition containing manganese in the above-described range, the leakage current as a capacitor is further reduced, and a long life is achieved. More preferably, the amount of manganese contained in the oxide dielectric film is 0.25 mol% to 1.50 mol%. This is to ensure the quality of the oxide dielectric film more reliably. The oxide dielectric film is a dielectric film having a perovskite structure, and does not contain manganese oxide unless explicitly stated that the oxide dielectric film contains a manganese oxide component.

  It is also assumed that manganese is substituted in the oxide crystal lattice. In general, an oxide dielectric film causes oxygen deficiency due to crystallization under a low oxygen partial pressure. For this reason, the valence of titanium is reduced from tetravalent to trivalent, and the insulating property is reduced by electron hopping between titanium atoms having different valences. However, when a suitable amount of manganese is substituted and dissolved in the oxide crystal, it can take a divalent to trivalent valence configuration, compensate for oxygen deficiency, and reduce the titanium without causing insulation. The improvement effect can be expected.

  In addition, when the oxide dielectric film formed by any one of the sol-gel method, MOCVD method, and sputtering deposition method is used as a dielectric layer, leakage current may flow through the crystal grain boundaries and structural defects of the oxide dielectric film. Is expensive. That is, the leakage current increases when the structure of the oxide dielectric film is fine and there are many crystal grain boundaries. On the other hand, the structure of the oxide dielectric film is coarsened to a certain range, the leakage current is small in a state where there are few crystal grain boundaries, and a high-capacity dielectric layer is obtained. In particular, an oxide dielectric film formed by a sol-gel method, MOCVD method, or sputtering deposition method under normal conditions has many structural defects in its crystal structure, and the structure of the oxide dielectric film is constant. It is difficult to create a state in which the crystal grain boundaries are small and the grain boundary is small. Therefore, it is preferable to bury a structural defect serving as a leakage current flow path by impregnating a resin component into an oxide dielectric film formed by any of the sol-gel method, the MOCVD method, and the sputtering deposition method.

  As the resin component used for embedding, a resin composition using an epoxy resin as a main agent is preferably used. Among them, the epoxy resin contains 40 wt% to 70 wt% of epoxy resin, 20 wt% to 50 wt% of polyvinyl acetal resin, and 0.1 wt% to 20 wt% of melamine resin or urethane resin with respect to the total resin component, It is preferable to use a resin composition in which 5% by weight to 80% by weight is a rubber-modified epoxy resin.

  As an epoxy resin used here, if it is marketed for the shaping | molding of a laminated board etc. or an electronic component, it can be especially used without a restriction | limiting. Specific examples include bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolac type epoxy resin, o-cresol novolac type epoxy resin, triglycidyl isocyanurate, glycidylamine compounds such as N, N-diglycidylaniline, Examples thereof include glycidyl ester compounds such as tetrahydrophthalic acid diglycidyl ester and brominated epoxy resins such as tetrabromobisphenol A diglycidyl ether. These epoxy resins are preferably used alone or in combination. Moreover, the polymerization degree and epoxy equivalent as an epoxy resin are not specifically limited.

  The “curing agent” of the epoxy resin includes dicyandiamide, organic hydrazide, imidazoles, amines such as aromatic amines, phenols such as bisphenol A and brominated bisphenol A, phenol novolac resins and cresol novolac resins. And novolaks and acid anhydrides such as phthalic anhydride. Moreover, a hardening | curing agent may be used individually by 1 type, or 2 or more types may be mixed and used for it. Since the addition amount of the curing agent with respect to the epoxy resin is naturally derived from the respective equivalents, it is considered that there is no need to specify the mixing ratio strictly strictly. Therefore, in this invention, the addition amount of a hardening | curing agent is not specifically limited.

  In addition, there is a curing accelerator to be added in an appropriate amount as necessary. As the curing accelerator, tertiary amine, imidazole-based, urea-based curing accelerator or the like can be used. In the present invention, the mixing ratio of the curing accelerator is not particularly limited. This is because the amount of the hardening accelerator can be arbitrarily determined by the manufacturer in consideration of the production conditions in the manufacturing process of the dielectric layer.

  It is preferable that the compounding quantity of the epoxy resin mix | blended with this resin composition is 40 to 70 weight% of the resin component total amount. If the blending amount is less than 40% by weight, the insulating properties and heat resistance as electrical characteristics deteriorate. On the other hand, if it exceeds 70% by weight, the resin flow during curing becomes too large, and the resin component tends to be unevenly distributed in the dielectric layer.

  And it is preferable to use a rubber-modified epoxy resin as a part of the epoxy resin composition. The rubber-modified epoxy resin can be used without particular limitation as long as it is a product marketed for adhesives or paints. For example, “EPICLON TSR-960” (trade name, manufactured by Dainippon Ink & Co.), “EPOTOOHTO YR-102” (trade name, manufactured by Toto Kasei), “Sumiepoxy ESC-500” (trade name) , Manufactured by Sumitomo Chemical Co., Ltd.) and “EPOMIK VSR 3531” (trade name, manufactured by Mitsui Petrochemical Co., Ltd.). These rubber-modified epoxy resins may be used alone or in combination of two or more. The blending amount of the rubber-modified epoxy resin here is 5% by weight to 80% by weight of the total amount of the epoxy resin. Use of a rubber-modified epoxy resin facilitates the fixing of the resin component in the dielectric layer. Therefore, when the compounding amount of the rubber-modified epoxy resin is less than 5% by weight, the effect of promoting fixing in the dielectric layer cannot be obtained. On the other hand, if the amount of the rubber-modified epoxy resin is more than 80% by weight, the heat resistance as a cured resin is lowered.

  And the polyvinyl acetal resin used for the said epoxy resin composition is synthesize | combined by reaction of polyvinyl alcohol and aldehydes. At present, as a polyvinyl acetal resin, a reaction product of polyvinyl alcohol having various degrees of polymerization and one or more aldehydes is commercially available for coatings and adhesives. In the present invention, the types of aldehydes and acetals are used. The degree of conversion can be used without any particular limitation. The polymerization degree of the raw material polyvinyl alcohol is not particularly limited, but considering the heat resistance as a cured resin and the solubility in a solvent, it is desirable to use a product synthesized from polyvinyl alcohol having a polymerization degree of 2000 to 3500. Further, a modified polyvinyl acetal resin having a carboxyl group or the like introduced in the molecule is also commercially available, but can be used without particular limitation as long as there is no problem in compatibility with the combined epoxy resin. The amount of the polyvinyl acetal resin blended in the insulating layer is 20% by weight to 50% by weight of the total amount of the resin composition. If the blending amount is less than 20% by weight, the effect of improving the fluidity as a resin cannot be obtained. On the other hand, if the blending amount exceeds 50% by weight, the water absorption rate of the insulating layer after curing becomes high, which makes it extremely undesirable as a constituent material for the dielectric layer.

  In addition to the above components, the resin composition used in the present invention preferably contains a melamine resin or a urethane resin as a crosslinking agent for the polyvinyl acetal resin. As the melamine resin used here, an alkylated melamine resin commercially available for coating can be used. Specific examples include methylated melamine resins, n-butylated melamine resins, iso-butylated melamine resins, and mixed alkylated melamine resins thereof. The molecular weight and alkylation degree as a melamine resin are not particularly limited.

  As the urethane resin, a resin containing an isocyanate group in a molecule marketed for an adhesive or a paint can be used. Specific examples include reaction products of polyisocyanate compounds such as tolylene diisocyanate, diphenylmethane diisocyanate, polymethylene polyphenyl polyisocyanate and polyols such as trimethylolpropane, polyether polyol, and polyester polyol. Since these compounds are highly reactive as resins and may be polymerized by moisture in the atmosphere, in the present invention, these resins are blocked with phenols or oximes so as not to cause this problem. The use of a urethane resin called isocyanate is preferred.

  The compounding quantity of the melamine resin or urethane resin added to the resin composition in this invention is 0.1 weight%-20 weight% of the resin composition total amount. When the blending amount is less than 0.1% by weight, the crosslinking effect of the polyvinyl acetal resin is insufficient, the heat resistance of the insulating layer is lowered, and when the blending amount exceeds 20% by weight, the fixing property in the dielectric layer is deteriorated. .

  In addition to the above essential components, additives such as inorganic fillers typified by talc and aluminum hydroxide, antifoaming agents, leveling agents, coupling agents and the like can also be used in this resin composition as desired. These improve the permeability of the resin component to the dielectric layer, and are effective in improving flame retardancy and reducing costs.

  The resin composition described above is a dilute resin having a solid content of 0.1 wt% to 1.0 wt% in which the solid content is controlled within a certain range using a solvent so that the dielectric layer can be easily impregnated. Used as a varnish. The dilute resin varnish is preferably applied to the surface of the dielectric layer by a spin coating method and allowed to penetrate from the viewpoint of maintaining the coating uniformity.

  Further, when the dielectric layer 4 is to be formed by the sol-gel method, the following steps (I) to (III) are generally performed.

(I) A solution preparation step for preparing a sol-gel solution for producing a desired oxide dielectric film. (II) The sol-gel solution is applied to the substrate surface, dried in an oxygen-containing atmosphere at 120 ° C. to 250 ° C. for 30 seconds to 10 minutes, and 450 ° C. to 550 ° C. in an oxygen-containing atmosphere. A coating process for adjusting the film thickness by repeating the process of thermal decomposition under conditions of 5 to 30 minutes. Then, the step (II) is repeated a plurality of times to adjust to a desired film thickness.
(III) Next, as a final firing, a firing step in which a dielectric layer is formed by firing in an inert gas replacement atmosphere or vacuum at 550 ° C. to 800 ° C. for 5 minutes to 60 minutes. Through the above steps, a dielectric layer which is an oxide dielectric film is formed.

  However, when using the sol-gel method, it is preferable to form an oxide dielectric film through the following steps (a) to (c).

(A) A solution preparation step for preparing a sol-gel solution for producing a desired oxide dielectric film.
(B) The sol-gel solution is applied to the surface of a metal substrate, dried in an oxygen-containing atmosphere at 120 ° C. to 250 ° C. for 30 seconds to 10 minutes, and then in an oxygen-containing atmosphere at 270 ° C. to 390 A series of steps of performing thermal decomposition under the conditions of 5 ° C. to 30 ° C. is defined as one unit step, and when repeating this one unit step a plurality of times, it is arbitrarily between 550 ° C. and 800 ° between one unit step and one unit step. Coating process for adjusting the film thickness by providing inert gas replacement at 2 ° C. to 60 ° C. or pre-baking treatment in vacuum.
(C) A firing step in which the dielectric layer is finally formed by performing an inert gas replacement at 550 ° C. to 800 ° C. × 5 minutes to 60 minutes or firing in vacuum.

  The former dielectric layer, which is an oxide dielectric film using the sol-gel method (conventional method), is fired only once in the final stage. On the other hand, in the latter sol-gel method, an oxide dielectric film used as a dielectric layer is manufactured by providing at least one preliminary firing in the middle of one unit process. Hereinafter, the steps (a) to (c) in the latter sol-gel method will be described.

(A) Process: This process is a solution preparation process for preparing a sol-gel solution for producing a desired oxide dielectric film. There is no special restriction regarding this step, and a commercially available preparation agent may be used or it may be blended by itself. As a result, any one of the above oxide films may be obtained as the desired oxide dielectric film.

(B) Step: In this step, the sol-gel solution is applied to the surface of the metal substrate (hereinafter, referred to as a unit “coating”), and 120 ° C. to 250 ° C. in an oxygen-containing atmosphere. × Dry for 30 seconds to 10 minutes (referred to as “drying” in the following explanation), and pyrolyze in an oxygen-containing atmosphere under conditions of 270 ° C. to 390 ° C. × 5 minutes to 30 minutes ( In the following description, the unit is referred to as “pyrolysis.”) When a series of steps is defined as one unit step and this one unit step is repeated a plurality of times, at least one 550 between one unit step and one unit step is performed. It is a coating process in which the film thickness is adjusted by providing an inert gas replacement or a pre-baking treatment in vacuum at a temperature of from 800C to 800C for 2 to 60 minutes.

  That is, in this step, a series of steps of coating → drying → pyrolysis is referred to as one unit step. In the conventional method, this single unit process is simply repeated a plurality of times and finally fired. On the other hand, in the present invention, at least one preliminary firing step is provided in the middle of repeating one unit step a plurality of times. Therefore, for example, if one unit process is repeated six times, if one pre-baking step is provided, one unit step (first time) → pre-firing step → one unit step (second time) → 1 unit For example, the process of the process (third time) → one unit process (fourth time) → one unit process (fifth time) → one unit process (sixth time) is adopted. If two firing steps are provided, one unit process (first time) → preliminary firing step → one unit process (second time) → one unit process (third time) → preliminary firing step → one unit process (4 1st process (5th time) → 1 unit process (6th time), etc. Furthermore, if a firing process is provided between all 1 unit processes, 1 unit process (first time) → preliminary firing process → 1 unit process (second time) → preliminary firing process → 1 unit process (third time) → preliminary A process of firing step → one unit step (fourth) → pre-baking step → one unit step (fifth) → pre-baking step → one unit step (sixth) is adopted.

  The crystal state of the oxide dielectric film obtained by the conventional sol-gel method is a fine crystal from the observation image when the cross section of the dielectric layer is processed with a focused ion beam and observed with a transmission electron microscope at 1,000,000 times magnification. Grains exist, and many voids can be confirmed in the crystal grains. This is considered to be because the organic component contained in the sol-gel liquid is evaporated during firing. When wet etching is performed in such a state, the etching solution easily penetrates into the dielectric layer. Therefore, when the upper electrode is patterned by etching, the substrate (the constituent material of the lower electrode) is eroded by the etching solution that has passed through the dielectric layer, and the dielectric film at the erosion site is lost and disappears. On the other hand, by adopting this step (b), the structure of the oxide dielectric film becomes dense with a high film density and with few structural defects in the crystal grains. Therefore, even if the upper electrode is patterned by the wet etching method as described above, the penetration of the etchant into the dielectric layer hardly occurs. Therefore, the dielectric film is exposed to the portion where the dielectric film is to be exposed after the upper electrode is patterned by etching. Is reliably observed, and etching elution of the substrate (the constituent material of the lower electrode) can be prevented. As a result, a leakage current is small and a capacitor circuit having a high-capacity dielectric layer can be obtained.

  Here, coating in one unit process will be described. There is no particular limitation on the coating means for applying the sol-gel solution to the surface of the metal substrate. However, it is preferable to use a spin coater as long as the uniformity of the film thickness and the characteristics of the sol-gel solution are taken into consideration.

  Next, drying in one unit process will be described. When the coating of the sol-gel solution is completed, the coating is dried in an oxygen-containing atmosphere at 120 ° C. to 250 ° C. for 30 seconds to 10 minutes, and then in an oxygen-containing atmosphere at 270 ° C. to 390 ° C. for 5 minutes to 30 minutes. Pyrolysis is performed under conditions. The drying conditions at this time are 120 ° C. to 250 ° C. × 30 seconds to 10 minutes. If this condition is not satisfied, the drying may be insufficient and the surface of the dielectric film after thermal decomposition may become rough. If the drying is excessive, the subsequent thermal decomposition reaction becomes non-uniform, and the local quality variation of the dielectric film is likely to occur. When performing this drying and thermal decomposition, it is performed in an oxygen-containing atmosphere. In other words, the decomposition of organic substances is not promoted when carried out in a reducing atmosphere.

  Further, the thermal decomposition of one unit process will be described. When the drying is completed, thermal decomposition is performed in an oxygen-containing atmosphere at 270 ° C. to 390 ° C. × 5 minutes to 30 minutes. Here, the employed pyrolysis temperature is very characteristic. A temperature range of 450 ° C. to 550 ° C. has been adopted as the conventional pyrolysis temperature. On the other hand, in the manufacturing method according to the present invention, a thermal decomposition temperature in a low temperature range of 270 ° C. to 390 ° C. is employed in order to prevent excessive oxidation of the metal substrate. Here, when the thermal decomposition temperature is less than 270 ° C., no matter how long the heating is continued, good thermal decomposition is difficult to occur, productivity is lacking, and good capacitor characteristics cannot be obtained. On the other hand, the dielectric film is formed on the surface of the metal substrate. When heating at a temperature exceeding 390 ° C., oxidation of the surface of the metal substrate is remarkable at the interface between the dielectric film and the metal substrate. To be seen. However, in consideration of process variations and quality safety in mass production, it is preferable to set an upper limit of about 370 ° C., which is a lower temperature. The heating time is determined by the decomposition temperature employed and the properties of the sol-gel solution, but sufficient heat decomposition can be achieved with heating for less than 5 minutes on the assumption that the above heating temperature range is employed. Absent. Further, when the heating time exceeds 30 minutes, the oxidation of the surface of the metal substrate proceeds even in the above temperature range.

  And the preliminary baking process provided between the 1 unit process mentioned above and 1 unit process performs the 550 degreeC-800 degreeC x 2 minute-60 minute inert gas substitution, or the baking process in a vacuum. Since this condition is almost the same as the step (c) described below, the critical significance of the numerical value will be described in the description.

(C) Process: This process is a baking process which finally makes a dielectric layer by performing an inert gas substitution at 550 ° C. to 800 ° C. × 5 minutes to 60 minutes or a baking treatment in a vacuum. This firing step is a so-called main firing step, and after this firing, a final dielectric layer is obtained. In this firing step, heating is performed in an inert gas replacement atmosphere or vacuum in order to prevent oxidative deterioration of the base material that is a metal material. The heating temperature at this time is 550 ° C to 800 ° C x 5 minutes to 60 minutes. When the heating is less than this temperature condition, firing is difficult, the adhesiveness with the base material is excellent, and a dielectric film having an appropriate density and a crystal structure with an appropriate particle size cannot be obtained. When excessive heating exceeding this temperature condition is performed, the deterioration of the dielectric film and the physical strength of the base material proceed, and the high electric capacity and long life as capacitor characteristics cannot be achieved.

Further, when it is desired to avoid a high-temperature process such as the above sol-gel method, it is preferable to form a dielectric layer using an aerosol deposition method. This aerosol deposition method is an inorganic oxide such as PZT, BiZrO _{3 and the} like that can be used as a dielectric material, and fine particles having a diameter of 0.02 μm to 2.0 μm are mixed with a gas to form an aerosol. In this method, the dielectric layer 4 is formed by causing particles to collide with the lower electrode forming layer 3 through a nozzle (opening diameter: 1 mm or less) in a reduced pressure atmosphere of about 1 kPa at a spray forming speed accelerated to several hundreds m / sec. The film is characterized in that good film density and adhesion can be obtained, and that it exhibits excellent insulation as a dielectric layer. In order to avoid duplication of the aerosol deposition method, the case of forming the lower electrode formation layer and the upper electrode formation layer by the method is also described. That is, by using 0.02 μm to 2.0 μm fine particles of copper powder, nickel powder, nickel alloy powder, gold powder, etc. as a predetermined metal material as a raw material used in the aerosol deposition method, An electrode forming layer can be formed.

  When the dielectric layer 4 is formed on the surface of the lower electrode forming layer 3 as described above, an electrochemical method such as attaching a metal foil to the surface of the dielectric layer 4 or plating (including electroless plating). The upper electrode forming layer 5 is provided by using a sputtering vapor deposition method, an aerosol deposition method, or the like. And the thickness of the upper electrode formation layer 5 at this time is changed according to product specifications, and there is no special limitation. Usually, it is about 1.5 μm to 5 μm.

Capacitor circuit forming layer manufacturing method II: Also, in the method of manufacturing a printed wiring board including the capacitor circuit according to the present invention, a three-layer capacitor circuit forming layer (lower electrode forming layer) on the surface of the substrate in the laminating step / Dielectric layer / upper electrode forming layer), as shown in FIG. 4B, the lower electrode forming layer 3 is formed on the surface of the substrate 2, and the dielectric layer 4 is formed on the surface of the lower electrode forming layer 3. It is also preferable to employ a method of forming the upper electrode forming layer 5 (hereinafter referred to as “sequential laminating method”). That is, when such a sequential lamination method is used, it is possible to form a thin capacitor circuit formation layer that cannot be achieved by the capacitor circuit formation material in the case of the capacitor circuit formation layer manufacturing method I. Hereinafter, the steps will be described.

  The concept relating to the “base material” is the same as in the case of the method I for producing a capacitor circuit forming layer. Therefore, the formation of the lower electrode forming layer 3 on the substrate surface will be described. As one method for forming the lower electrode forming layer 3 on the surface of the substrate, a method obtained by bonding the substrate and a metal foil can be used. In such a case, an adhesive layer may be provided at the interface between the base material and the metal foil. Moreover, when using a polyimide resin film or a tape as a flexible base material, what is obtained by casting a polyimide resin on the copper foil surface can be used. Since these are generally widely used by a known technique, a detailed description of the manufacturing method is omitted. Furthermore, it is also possible to form a metal layer serving as the lower electrode formation layer 3 on the polyimide resin surface by using an aerosol deposition method.

  In addition, a seed layer made of either copper, nickel, cobalt, or an alloy thereof is provided on the substrate by sputtering vapor deposition or direct metallization, and then any of copper, nickel, or nickel alloy is deposited and grown by electrolysis. It is also preferable to use what is obtained. This is because the adhesiveness to the substrate is excellent and the film thickness can be easily controlled. In particular, the latter direct metallization method is useful when a polyimide resin substrate is used.

  When a seed layer made of any one of copper, nickel, cobalt, or an alloy thereof is provided on the base material by sputtering vapor deposition, the surface of the base material is subjected to adhesion improving treatment such as plasma treatment, and then copper, nickel The sputtering target made of either cobalt or an alloy thereof is irradiated with argon ions or the like to land the struck particles on the surface of the substrate, thereby forming the seed layer having a thickness of 0.1 μm to 1 μm.

  On the other hand, when the direct metallization method is used, a polyimide resin film or a tape (hereinafter referred to as “polyimide resin film”) is used as a base material, and a region where a seed layer is formed is a potassium hydroxide solution or water. An alkali treatment is performed with a sodium oxide solution to open the imide ring and form a carboxyl group on the surface. This alkali treatment is performed by a technique such as immersing a polyimide resin film in an alkali solution or spraying an alkali solution on the surface of the polyimide resin film. If the surface that does not require ring-opening treatment is coated with a water-resistant film in advance, even when exposed to a solution in the direct metallization process described below, water absorption and moisture absorption from the coated surface are prevented, making it more stable. Thus, a high peeling strength after heating is provided.

  The ring-opened polyimide resin film and the like are washed with water and enter a neutralization step. Ring-opening to form a carboxyl group and neutralizing the strongly alkaline polyimide resin surface using an acid solution. Here, hydrochloric acid is preferably used for the solution used for neutralization. Then, a carboxyl metal salt is formed on the surface of the polyimide resin film by bringing the neutralized carboxyl group into contact with the metal ion-containing solution to adsorb the metal component, washed with water, and then formed on the surface of the polyimide resin film. The salt is reduced using sodium borohydride, hypophosphorous acid, dimethylamine or the like as a reducing agent to form a metal film on the surface of a polyimide resin film or the like. And this adsorption reduction process is repeated a plurality of times, and two layers of an amorphous metal film of 10 nm to 80 nm and a mixed layer of 50 nm to 180 nm in which metal particles and polyimide resin are mixed at the same time are formed.

  Then, a thin film of copper, nickel, cobalt, or an alloy thereof having an average thickness of 50 nm to 700 nm is formed on the two layers, and the seed layer is completed. For the formation of this thin film, it is preferable to employ an electrolytic method using the following plating solution.

When forming a copper thin film, the solution which can be used as copper ion supply sources, such as a copper sulfate type solution and a copper pyrophosphate type solution, is used, and it is not specifically limited. For example, in the case of a copper sulfate-based solution, a solution having a concentration of copper of 30 g / l to 100 g / l and sulfuric acid of 50 g / l to 200 g / l is used, with a liquid temperature of 30 ° C. to 80 ° C. and a current density of 1 A / dm ² to a condition of 100A / dm ^2. In the case of a copper pyrophosphate-based solution, a solution having a copper concentration of 10 g / l to 50 g / l and a potassium pyrophosphate of 100 g / l to 700 g / l, a liquid temperature of 30 ° C. to 60 ° C., a pH of 8 to 12 and a current density. The condition is 1 A / dm ^{2 to} 10 A / dm ² .

When a pure nickel-based thin film is formed, a solution used as a nickel plating solution can be widely used. For example, i) nickel sulfate 240 g / l, nickel chloride 45 g / l, boric acid 30 g / l, liquid temperature 55 ° C., pH 5, current density 0.2 A / dm ² watt bath conditions, ii) nickel sulfamate 400 g / l , Boric acid 30 g / l, liquid temperature 55 ° C., pH 4.5, current density 0.2 A / dm ² sulfamic acid bath condition, iii) nickel concentration using nickel sulfate 5 g / l to 30 g / l, potassium pyrophosphate The conditions are 50 g / l to 500 g / l, liquid temperature 20 ° C. to 50 ° C., pH 8 to pH 11, and current density 0.2 A / dm ^{2 to} 10 A / dm ² . The pure nickel thin film is used in the sense that no intentional alloying element is added, and is not used in the sense of complete 100% purity excluding inevitable impurities. Keep it.

In the case of forming a zinc-nickel alloy thin film, for example, nickel sulfate is used and the nickel concentration is 1 g / l to 2.5 g / l, and zinc pyrophosphate is used and the zinc concentration is 0.1 g / l to 1 g / l. Conditions such as potassium acid 50 g / l to 500 g / l, liquid temperature 20 ° C. to 50 ° C., pH 8 to pH 11 and current density 0.2 A / dm ^{2 to} 10 A / dm ² are adopted.

In the case of forming a nickel-cobalt alloy thin film, for example, cobalt sulfate 80 g / l to 180 g / l, nickel sulfate 80 g / l to 120 g / l, boric acid 20 g / l to 40 g / l, potassium chloride 10 g / l to 15 g. / L, sodium dihydrogen phosphate 0.1 g / l to 15 g / l, liquid temperature 30 ° C. to 50 ° C., pH 3.5 to pH 4.5, current density 0.2 A / dm ^{2 to} 10 A / dm ² , etc. Is adopted.

Further, nickel-phosphorus alloy plating can be used by using a phosphoric acid-based solution. In this case, nickel sulfate 120 g / l to 180 g / l, nickel chloride 35 g / l to 55 g / l, H ₃ PO ₄ 30 g / l to 50 g / l, H ₃ PO ₃ 20 g / l to 40 g / l, liquid temperature 70 ℃ ~95 ℃, pH0.5~pH1.5, is to employ the conditions of a current density of ^{0.2A / dm 2 ~10A / dm 2} .

  Then, a copper layer for forming a circuit is formed on the surface of the seed layer formed by the sputtering vapor deposition method or the direct metallization method as described above using an electrochemical method. Here, “using an electrochemical method” may be performed by electroless copper plating using a difference in ionization tendency, electrolytic copper plating, or a combination of electroless copper plating and electrolytic copper plating. As a result, it is meant that a desired metal component is deposited and grown to increase the thickness so that it can function as a lower electrode formation layer. The electroless copper plating bath used here, the composition of the electrolytic copper plating bath, and other plating conditions are not particularly limited. Any condition can be selected and used. At this stage, the lower electrode forming layer 3 is formed on the surface of the substrate 2.

Next, the dielectric layer 4 is formed on the surface of the lower electrode formation layer 3. However, since the lower electrode forming layer 3 is already formed on the surface of the organic material, a dielectric layer forming method that requires a high temperature process such as a sol-gel method cannot be adopted, and the process can be manufactured at a low temperature. Is preferably adopted. That is, a technique capable of forming a dielectric layer on the surface of the lower electrode formation layer 3 at a low temperature such as a coating method in which a resin containing dielectric powder is applied, a sputtering deposition method, an aerosol deposition method, or the like is employed. The dielectric layer here is the same as described above, and is an inorganic oxide layer such as PZT or BiZrO ₃ having a perovskite structure that can be used as a dielectric material. Also, the aerosol deposition method referred to here is the same as described above.

  Further, an upper electrode forming layer 5 is formed on the dielectric layer 4 using an electrochemical method such as plating (including electroless plating), a sputtering vapor deposition method, an aerosol deposition method, etc. The circuit forming layer (lower electrode forming layer / dielectric layer / upper electrode forming layer) is completed. In addition, the concept regarding the material and thickness which comprise the upper electrode formation layer 5 is as above-mentioned.

Step B: As shown in FIG. 1B, the first etching resist pattern forming step is a step for forming an upper electrode shape by forming an etching resist layer on the upper electrode forming layer 5 located on the outer layer. One etching resist pattern 8 is formed. In this case, it is preferable to use a liquid resist, a dry film, or the like for the etching resist layer. When an etching resist layer is formed on the upper electrode formation layer 5, exposure and development are performed to form a first etching resist pattern 8. In particular, considering a first dielectric layer removing step described later, it is preferable to use a dry film having a thickness of 10 μm or more. This is because it is effective as a cushion material for blast particles.

Step C: In this upper electrode formation step, after forming the first etching resist pattern, the upper electrode formation layer 5 is etched, and as shown in FIG. 1C, the upper electrode circuit 9 and other circuit portions The dielectric layer 4 in a region other than (not shown in FIG. 1C) is exposed. For the etching process at this time, it is possible to use wet etching in which unnecessary portions are dissolved using an etching solution.

Step D: In this first dielectric layer removing step, the exposed dielectric layer 4 is exposed as shown in FIG. 2D while the etching resist pattern 8 remains on the surfaces of the upper electrode circuit 9 and other circuit portions. However, no treatment is required until the dielectric layer is completely removed at this stage. This is because if the dielectric layer is completely removed by the physical method described below, even if an etching resist layer is present on the surface of the upper electrode circuit, the surface of the upper electrode circuit 9 is easily damaged. Therefore, it is preferable that defects such as cracks are introduced into the dielectric layer 4 to leave most of the dielectric layer. Here, there are two methods for physically removing the dielectric layer. One is preferably a method using buffing, and the other is preferably a blast treatment (particularly wet blast treatment).

  The buffing used for removing the dielectric layer is preferably performed using a fine buff of # 600 or more. If a buff coarser than # 600 is used, the projecting portion such as the upper electrode circuit is caught and damaged, and the circuit quality cannot be maintained. By using buffing in this way, defects such as cracks can be easily introduced into the dielectric layer 4. If buffing is used, the end portion of the upper electrode circuit is not damaged at all, and a short circuit between the upper electrode circuit and the lower electrode forming layer does not occur, and the upper electrode adjustment step described later is almost unnecessary. Furthermore, the buffing pressure during buffing may be extremely light because it is sufficient to leave most of the dielectric layer 4. When buff polishing is selected, the etching resist layer may or may not remain. However, an etching resist layer is required in the second dielectric layer removal step performed later.

  The blasting process used to remove the dielectric layer is intended to be both a drive blasting process and a wet blasting process. However, in consideration of the finished state of the polished surface after blasting and the reduction of damage to the circuit surface, it is preferable to employ wet blasting. In this wet blasting treatment, a slurry-like polishing liquid in which an abrasive, which is a fine powder, is dispersed in water is caused to collide with a surface to be polished as a high-speed water flow, thereby enabling polishing of a fine region. This wet blasting process is characterized in that polishing can be performed with a higher density and less damage compared to a blasting process performed in a dry environment. By using this wet blasting process, the dielectric layer exposed in the inter-circuit gap or the like is polished and removed, thereby removing the unnecessary dielectric layer. The blast treatment is preferably performed in a state where an etching resist layer exists on the surface of the upper electrode in order to prevent damage to the circuit portion due to collision of the abrasive. That is, after the etching of the upper electrode circuit 9 is completed, the blasting process is performed using the etching resist pattern 8 without being peeled off. In this way, the etching resist layer becomes a buffer layer of blast particles that collide, and damage to the circuit can be reduced.

  Further, if the dielectric layer 4 is physically removed as described above, the etching resist pattern 8 (etching resist layer) on the surface of the upper electrode circuit 9 may be damaged. In such a case, considering the presence of the second dielectric layer removal step, which is the next step, and an upper electrode adjustment step described below, a step of providing an etching resist layer on the surface of the upper electrode circuit 9 again. It is preferable to add.

  Furthermore, when the removal of the dielectric layer as described above is completed, particularly when blasting is used, the dielectric at the end of the upper electrode circuit is damaged, and the end of the upper electrode circuit and the lower electrode forming layer are short-circuited. It is easy to do. Therefore, although the area of the upper electrode is reduced, it is preferable to provide an upper electrode adjusting step for removing a short-circuit portion by etching away a small region around the upper electrode circuit. For this etching, dry etching such as sputtering can be used. However, it is preferable to form a photosensitive etching resist layer and process using an etching solution. This upper electrode adjustment step can be performed simultaneously with the etching of the lower electrode described below.

Step E: In this second dielectric layer removing step, the dielectric that remains even after the exposed dielectric layer in the region other than the upper electrode circuit and other circuit portions is physically removed by the first dielectric layer removing step. The layer is removed by etching to obtain the state shown in FIG. For the etching at this time, an etching solution capable of dissolving the lower electrode formation layer 3 is used to penetrate the etching solution from defects such as cracks introduced into the dielectric layer 4 in the first dielectric layer removal step. Then, the surface of the lower electrode formation layer 3 is slightly dissolved, and the remaining dielectric layer is removed by etching. Therefore, this etching is extremely light etching.

Step F: In the first etching resist layer peeling step, the etching resist layer 8 remaining on the surfaces of the upper electrode circuit 9 and other circuit portions is peeled, and the state shown in FIG. Regarding the peeling method, the etching resist component is usually swollen and peeled off using an alkaline solution.

Step G: In this second etching resist pattern forming step, an etching resist layer for forming a lower electrode circuit shape is formed, exposed and developed, and then a second etching resist pattern 10 as shown in FIG. Form. At this time, the second etching resist pattern 10 does not need to function as a buffer material for physical removal of the dielectric layer, and thus there is no particular limitation on the thickness, type, and the like.

Step H: In the second etching step, the second etching resist pattern 10 is formed and then etched to form the lower electrode circuit 11, and the second etching resist pattern 10 is peeled off to provide a capacitor circuit. The printed wiring board 1 is assumed. Etching at this time can be patterned using a known etching method, photolithography method, sputtering method, etc. similar to the formation of the upper electrode circuit, but processing using an etching solution is an economical point of view. To preferred.

<Printed wiring board with capacitor circuit>
The printed wiring board obtained by the method of manufacturing a printed wiring board having the above capacitor circuit has no dielectric layer in the extra part, and there is no residual dielectric in the part from which the dielectric layer is removed. It becomes a board. In addition, the printed wiring board said to this invention is a rigid board | substrate, such as a glass-epoxy base material and a glass-polyimide base material, a flexible substrate which used a polyimide resin film, PET film etc. as a base material, and a polyimide resin tape, PET It is described as a concept including all TAB and COF products using a tape or the like as a film carrier tape.

<Multilayer printed wiring board with built-in capacitor circuit>
The printed circuit board including the capacitor circuit according to the present invention is used as an inner layer core material in a normal multilayer printed wiring board manufacturing process, and the signal circuit is formed in the same plane or in an adjacent plane when the capacitor circuit is formed. Even if it is formed, the parasitic capacitance that obstructs the transmission of high-frequency signal signals is small, and it is possible to embed other circuit elements such as inductors. A multilayer printed wiring board comprising: In this method of manufacturing a multilayer printed wiring board, all known methods can be used, and it is considered that no special explanation is required.

  The manufacturing method of a printed wiring board provided with the capacitor circuit according to the present invention can reliably remove the dielectric layer at an unnecessary portion without damaging the upper electrode circuit shape or the like. Moreover, the manufacturing method is basically based on the conventional printed wiring board manufacturing process, and does not require a large capital investment. And the printed wiring board provided with the capacitor circuit obtained by the manufacturing method is subjected to the removal of the dielectric layer of unnecessary portions, and becomes a high-quality product that can be used in various ways. In particular, when the printed wiring board is used as an inner layer core material of a multilayer printed wiring board, even if a signal circuit is formed in the same plane as the capacitor circuit or in an adjacent plane, it is an obstacle to transmission of a high-frequency signal signal. Since the parasitic capacitance is small, it is possible to embed other circuit elements such as an inductor, and it is possible to greatly relax the constraint conditions of the circuit design. Therefore, the multilayer printed wiring board can greatly contribute to thinning and miniaturization.

The cross-sectional schematic diagram showing the manufacture flow of a printed wiring board provided with a capacitor circuit. The cross-sectional schematic diagram showing the manufacture flow of a printed wiring board provided with a capacitor circuit. The cross-sectional schematic diagram showing the manufacture flow of a printed wiring board provided with a capacitor circuit. The cross-sectional schematic diagram showing the manufacturing flow of a capacitor layer forming material. The schematic diagram showing the manufacture flow of the multilayer printed wiring board which incorporates a capacitor circuit (conventional method). The schematic diagram showing the manufacture flow of the multilayer printed wiring board which incorporates a capacitor circuit (conventional method). The schematic diagram showing the manufacture flow of the multilayer printed wiring board which incorporates a capacitor circuit (conventional method).

Explanation of symbols

1 Printed wiring board 1 having a capacitor circuit
2 Substrate 3 Lower electrode forming layer 4 Dielectric layer 5 Upper electrode forming layer 6 Capacitor layer forming material 7 Adhesive layer 8 First etching resist pattern (etching resist layer)
9 Upper electrode circuit 10 Second etching resist pattern (etching resist layer)
11 Lower electrode circuit 20 Inner layer core material 21 Prepreg 22 Metal foil 23 Outer layer circuit 24 Plating layer 25 Via hole 30 Multilayer printed wiring board with built-in capacitor circuit

Claims (11)

A method of manufacturing a printed wiring board comprising a capacitor circuit,
The manufacturing method of a printed wiring board provided with the capacitor circuit characterized by including the following processes A-H.
Step A: Lamination step of providing a capacitor circuit forming layer having a three-layer structure of lower electrode forming layer / dielectric layer / upper electrode forming layer on the surface of the substrate.
Step B: A first etching resist pattern forming step in which an etching resist layer is formed on the upper electrode forming layer located in the outer layer to form a first etching resist pattern.
Step C: An upper electrode formation step of forming a first etching resist pattern and then etching to expose a dielectric layer in a region other than the upper electrode circuit and other circuit portions.
Step D: A first dielectric layer removing step of physically removing the exposed dielectric layer while leaving the etching resist layer on the surfaces of the upper electrode circuit and other circuit portions.
Step E: a second dielectric layer that removes the dielectric layer that remains even if the exposed dielectric layer in regions other than the upper electrode circuit and other circuit portions is physically removed by the first dielectric layer removing step. Removal process.
Step F: A first etching resist layer peeling step for peeling off the etching resist layer left on the surfaces of the upper electrode circuit and other circuit portions.
Step G: A second etching resist pattern forming step of forming an etching resist layer for forming a lower electrode shape and forming a second etching resist pattern.
Step H: A second etching step of forming a second etching resist pattern and then performing an etching process to form a lower electrode circuit to obtain a printed wiring board including a capacitor circuit. Formation of a capacitor circuit forming layer (lower electrode forming layer / dielectric layer / upper electrode forming layer) having a three-layer structure on the surface of the base material in the laminating step
2. A printed wiring board having a capacitor circuit according to claim 1, wherein a lower electrode forming layer of a capacitor layer forming material having a three-layer structure (lower electrode forming layer / dielectric layer / upper electrode forming layer) is bonded to a substrate. Manufacturing method. Formation of a capacitor circuit forming layer (lower electrode forming layer / dielectric layer / upper electrode forming layer) having a three-layer structure on the surface of the base material in the laminating step
2. A printed wiring board comprising a capacitor circuit according to claim 1, wherein a lower electrode forming layer is formed on the surface of the substrate, a dielectric layer is formed on the surface of the lower electrode forming layer, and further an upper electrode forming layer is formed. Production method. The method for producing a printed wiring board having a capacitor circuit according to claim 3, wherein the lower electrode formation layer is obtained by forming a metal layer on a polyimide resin by an aerosol deposition method. The lower electrode formation layer is formed by providing a seed layer made of any one of copper, nickel, cobalt, or an alloy thereof on a substrate by sputtering vapor deposition, and then depositing and growing either copper, nickel, or a nickel alloy by an electrolytic method. A method for producing a printed wiring board comprising the capacitor circuit according to claim 3. The lower electrode forming layer is provided with a seed layer made of any of copper, nickel, cobalt, or an alloy thereof by a direct metallization method on a polyimide resin base material, and then any of copper, nickel, nickel alloy by an electrolytic method. A method for manufacturing a printed wiring board comprising the capacitor circuit according to claim 3, wherein the printed circuit board is obtained by depositing and growing the above. The printed circuit board having a capacitor circuit according to claim 3, wherein the lower electrode forming layer is obtained by casting a polyimide resin as a base material on the surface of the metal foil and having the lower electrode forming layer on the surface of the base material. A method for manufacturing a wiring board. The method for manufacturing a printed wiring board having a capacitor circuit according to claim 3, wherein the dielectric layer uses any one of a sputtering vapor deposition method and an aerosol deposition method. The method for producing a printed wiring board having a capacitor circuit according to any one of claims 3 to 8, wherein the upper electrode forming layer uses any one of a sputtering vapor deposition method and an aerosol deposition method. . The printed wiring board obtained by the manufacturing method of a printed wiring board provided with the capacitor circuit in any one of Claims 1-9. A multilayer printed wiring board comprising a built-in capacitor circuit obtained using the printed wiring board according to claim 10.

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