JP2006339273A - リードフレームの製造方法及びそれを用いた半導体装置の製造方法 - Google Patents

リードフレームの製造方法及びそれを用いた半導体装置の製造方法 Download PDF

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Publication number
JP2006339273A
JP2006339273A JP2005159982A JP2005159982A JP2006339273A JP 2006339273 A JP2006339273 A JP 2006339273A JP 2005159982 A JP2005159982 A JP 2005159982A JP 2005159982 A JP2005159982 A JP 2005159982A JP 2006339273 A JP2006339273 A JP 2006339273A
Authority
JP
Japan
Prior art keywords
lead frame
hole
manufacturing
pilot hole
envelope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005159982A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006339273A5 (enrdf_load_stackoverflow
Inventor
Hiroshi Sanada
広志 真田
Yukifumi Nishio
幸史 西尾
Kazuaki Muraoka
和晃 村岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2005159982A priority Critical patent/JP2006339273A/ja
Publication of JP2006339273A publication Critical patent/JP2006339273A/ja
Publication of JP2006339273A5 publication Critical patent/JP2006339273A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Led Device Packages (AREA)
JP2005159982A 2005-05-31 2005-05-31 リードフレームの製造方法及びそれを用いた半導体装置の製造方法 Pending JP2006339273A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005159982A JP2006339273A (ja) 2005-05-31 2005-05-31 リードフレームの製造方法及びそれを用いた半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005159982A JP2006339273A (ja) 2005-05-31 2005-05-31 リードフレームの製造方法及びそれを用いた半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2006339273A true JP2006339273A (ja) 2006-12-14
JP2006339273A5 JP2006339273A5 (enrdf_load_stackoverflow) 2007-03-22

Family

ID=37559598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005159982A Pending JP2006339273A (ja) 2005-05-31 2005-05-31 リードフレームの製造方法及びそれを用いた半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP2006339273A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7560278B2 (ja) 2020-06-25 2024-10-02 株式会社三井ハイテック リードフレーム及びその製造方法、並びにリードフレームパッケージの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7560278B2 (ja) 2020-06-25 2024-10-02 株式会社三井ハイテック リードフレーム及びその製造方法、並びにリードフレームパッケージの製造方法

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