JP2006294181A5 - - Google Patents
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- Publication number
- JP2006294181A5 JP2006294181A5 JP2005116612A JP2005116612A JP2006294181A5 JP 2006294181 A5 JP2006294181 A5 JP 2006294181A5 JP 2005116612 A JP2005116612 A JP 2005116612A JP 2005116612 A JP2005116612 A JP 2005116612A JP 2006294181 A5 JP2006294181 A5 JP 2006294181A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005116612A JP4668668B2 (ja) | 2005-04-14 | 2005-04-14 | 半導体装置 |
| TW094145274A TWI431761B (zh) | 2005-02-10 | 2005-12-20 | 半導體積體電路裝置 |
| KR1020060006515A KR101158490B1 (ko) | 2005-02-10 | 2006-01-20 | 반도체집적회로 장치 |
| CN200610006409XA CN1819059B (zh) | 2005-02-10 | 2006-01-20 | 半导体存储装置 |
| US11/341,385 US7443721B2 (en) | 2005-02-10 | 2006-01-30 | Semiconductor integrated device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005116612A JP4668668B2 (ja) | 2005-04-14 | 2005-04-14 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006294181A JP2006294181A (ja) | 2006-10-26 |
| JP2006294181A5 true JP2006294181A5 (enExample) | 2008-05-15 |
| JP4668668B2 JP4668668B2 (ja) | 2011-04-13 |
Family
ID=37414572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005116612A Expired - Fee Related JP4668668B2 (ja) | 2005-02-10 | 2005-04-14 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4668668B2 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080101110A1 (en) * | 2006-10-25 | 2008-05-01 | Thomas Happ | Combined read/write circuit for memory |
| JP5490357B2 (ja) | 2007-04-04 | 2014-05-14 | ピーエスフォー ルクスコ エスエイアールエル | 半導体記憶装置及びその制御方法 |
| JP5474313B2 (ja) | 2008-04-25 | 2014-04-16 | ピーエスフォー ルクスコ エスエイアールエル | 半導体記憶装置及びその制御方法 |
| JP4720912B2 (ja) | 2009-01-22 | 2011-07-13 | ソニー株式会社 | 抵抗変化型メモリデバイス |
| KR101810376B1 (ko) | 2011-09-09 | 2017-12-20 | 인텔 코포레이션 | 메모리 장치에서의 경로 분리 |
| CN115762599A (zh) * | 2017-01-20 | 2023-03-07 | 合肥睿科微电子有限公司 | 阻变式随机存取存储器电路及其操作方法 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4134637B2 (ja) * | 2002-08-27 | 2008-08-20 | 株式会社日立製作所 | 半導体装置 |
| DE102004016408B4 (de) * | 2003-03-27 | 2008-08-07 | Samsung Electronics Co., Ltd., Suwon | Phasenwechselspeicherbaustein und zugehöriges Programmierverfahren |
| TW200527656A (en) * | 2004-02-05 | 2005-08-16 | Renesas Tech Corp | Semiconductor device |
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2005
- 2005-04-14 JP JP2005116612A patent/JP4668668B2/ja not_active Expired - Fee Related