JP2006278780A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To sharply suppress the reflection loss of a high frequency signal in a connection between a wiring board and a packaging substrate, and to improve the operability of a semiconductor device. <P>SOLUTION: The semiconductor device is provided with the wiring board 1 having a ground wiring layer and/or a power supply wiring layer 4 in its inside, and forming a connecting electrode 7 on the main surface; a semiconductor device 5 mounted on the wiring board 1; and the packaging substrate 10 mounting the wiring board on the principal surface and having an input/output signal wire 11 electrically connected to the connecting electrode 7, and arranged on the principal surface and a ground layer 12 arranged on the same surface of the input/output signal wire 11 through a prescribed distance. The line width of the input/output signal wire 11 on a portion 14 superposed to the ground wiring layer and/or power supply wiring layer in plane view is narrower than the line width of other portions. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a wiring substrate for mounting a semiconductor element and a mounting substrate for mounting the wiring substrate.

  In the conventional semiconductor device, for example, as shown in FIG. 3, a connection electrode 37 b is formed on the main surface of the wiring substrate 31, and a signal wiring group 33, a ground wiring layer and / or a power supply wiring is formed inside the wiring substrate 31. Layer 34, signal through conductor 38, ground through conductor and / or power through conductor 39 are formed. Further, input / output signal wirings 311 and a ground layer 312 are formed on the main surface of the mounting substrate 310 on which the wiring substrate is mounted.

  The semiconductor element 35 and the wiring board 31 are electrically connected via a semiconductor element connecting electrode 37a, and a signal is transmitted using the signal wiring group 33 and the signal through conductor 38 in the wiring board 31. The signal wiring group 33 and the signal through conductor 38 are designed to match impedances in order to transmit signals. The ground wiring layer and / or the power supply wiring layer 34 has a function of supplying charges necessary for driving the semiconductor element 35.

  The input / output signal wiring 311 between the wiring board 31 and the mounting board 310 is electrically connected via the connection electrodes 37b and the conductor bumps 36b, and signals are transmitted between the wiring board 31 and the mounting board 310. . The input / output signal wiring 311 is designed to match impedance in the same manner as the wiring board 31 in order to transmit signals.

  Further, as shown in FIG. 4, the input / output signal wiring 311 connected to the wiring board 31 is overlapped with the input / output signal wiring 311 and the ground wiring layer and / or the power supply wiring layer 34b in a plan view. Site 314 is present.

  Further, a grounding layer 312a is formed around the input / output signal wiring 311 so as to surround the input / output signal wiring 311 at a certain distance and on the same plane as the input / output signal wiring 311.

  In the ground wiring layer and / or the power supply wiring layer 34b, a conductor non-forming portion 315 is formed to insulate the ground wiring layer and / or the power supply wiring layer 34b from the signal through conductor 38.

In FIG. 4, 32 is an insulating layer, and 37b is a connection electrode.
JP-A-7-137352

  However, the conventional semiconductor device described above, for example, by electrically connecting a part of the input / output signal wiring of the mounting substrate to an electric circuit substrate constituting an electronic device such as an information communication device or a portable device. In order to cope with the reduction in size and height of semiconductor devices accompanying the downsizing of equipment, the wiring board 31 is thinned and the wiring board 31 is mounted on the mounting board 310. There is a demand for reducing the diameter of the conductor bump 36 used in the process.

  At this time, the input / output signal wiring 311 formed on the mounting substrate 310 and the ground wiring layer 34b formed on the wiring substrate 31 overlap with each other in a plan view, and the ground wiring layer 34b and the input / output signal wiring 311 Therefore, the ground wiring layer 34 b and the input / output signal wiring 311 are electromagnetically coupled, and a parasitic capacitance is generated between the ground wiring layer 34 b and the input / output signal wiring 311. The parasitic capacitance causes an increase in reflection loss due to impedance mismatch due to a decrease in impedance of the input / output signal wiring 311 at a portion 314 where the input / output signal wiring 311 and the ground wiring layer 34b overlap in plan view.

  Due to this increase in reflection loss, transmission characteristics are deteriorated, and as a result, malfunction of an electronic device in which a semiconductor element or a semiconductor device is mounted is caused. In particular, recently, injection of underfill (increase in relative dielectric constant) to reinforce the decrease in mounting reliability due to the closer distance between the ground layer and the input / output signal wiring due to the above-described reduction in height and downsizing. Due to factors such as higher signal frequency, this problem has become more prominent.

  The present invention has been devised in view of the above-described problems, and its object is to reduce the thickness of a wiring board or to provide a conductor between a wiring board and a mounting board in order to cope with the reduction in size and height of a semiconductor device. An object of the present invention is to provide a semiconductor device capable of effectively preventing malfunction of a semiconductor element or the like even when a bump is downsized.

  The semiconductor device of the present invention includes a wiring board having a ground wiring layer and / or a power supply wiring layer inside, a connection electrode formed on the main surface, a semiconductor element mounted on the wiring board, The wiring board is mounted on a surface, and the input / output signal wiring electrically connected to the connection electrode and the input / output signal wiring are arranged on the same surface at a predetermined distance on the main surface. In the semiconductor device comprising the mounting substrate having the grounding layer, the input / output signal wiring has a line width in a portion overlapping with the grounding wiring layer and / or the power wiring layer in a plan view. It is characterized by being narrower than the line width.

  In the semiconductor device of the present invention, the connection electrode is provided on the outer peripheral portion of the main surface of the wiring board, the region facing the connection electrode, the input / output signal wiring, the ground wiring layer, and / or Alternatively, the ground wiring layer and / or the non-formation portion of the power supply wiring layer is formed in a portion where the power supply wiring layers overlap with each other when seen in a plan view.

  In the semiconductor device of the present invention, the wavelength of a signal transmitted through the input / output signal wiring from the outer periphery of the ground wiring layer and / or the power wiring layer is not formed inside the wiring board. A plurality of grounding through conductors are arranged at a position within a distance corresponding to the following length at a pitch corresponding to a length equal to or less than ¼ of the wavelength along the outer periphery of the non-forming portion. To do.

  Further, in the semiconductor device of the present invention, the input / output signal wiring corresponds to 1/4 or less of the wavelength of the signal transmitted through the input / output signal wiring from the portion where the line width is narrowed to the outside. The line width gradually increases within the length range.

  Further, the semiconductor device of the present invention corresponds to a length equal to or less than ¼ of the wavelength of the signal transmitted through the input / output signal wiring from the center line of the input / output signal wiring inside the mounting substrate. A plurality of ground through conductors electrically connected to the ground layer at a pitch within a distance corresponding to a length equal to or less than ¼ of the wavelength so as to surround the input / output signal wiring. It is characterized by being arranged.

  According to the semiconductor device of the present invention, a wiring board having a ground wiring layer and / or a power supply wiring layer inside and having a connection electrode formed on the main surface, a semiconductor element mounted on the wiring board, A wiring board is mounted on the main surface, an input / output signal wiring electrically connected to the connection electrode on the main surface, and a ground layer disposed on the same surface with a predetermined distance from the input / output signal wiring. In the semiconductor device including the mounting substrate, the input / output signal wiring has a narrower line width in a portion overlapping with the ground wiring layer and / or the power wiring layer than in other portions when seen in a plan view. Therefore, it is possible to suppress a decrease in impedance due to an increase in the inductive component of the input / output signal wiring at a portion where the input / output signal wiring and the ground wiring layer and / or the power supply wiring layer overlap with each other in a plan view. As a result, reflection loss due to impedance mismatch can be suppressed at a portion where the input / output signal wiring overlaps with the ground wiring layer and / or the power wiring layer in a plan view, and is small (particularly thin) and has a small signal. Thus, a semiconductor device having excellent transmission characteristics and the like and excellent reliability of operation of the semiconductor element can be obtained.

  Further, according to the semiconductor device of the present invention, the connection electrode is provided on the outer peripheral portion of the main surface of the wiring board, the region facing the connection electrode, the input / output signal wiring, the ground wiring layer, and / or the power supply wiring. By forming the ground wiring layer and / or the power wiring layer non-forming portion in a portion where the layers overlap when seen through the plane, the input / output signal wiring and the ground wiring layer and / or the power wiring layer can be seen through the plane. Impedance mismatch due to lowering of impedance due to reduction of parasitic capacitance caused by plane I / O signal wiring and ground wiring layer and / or power supply wiring layer overlapping. As a result, the input / output signal wiring and ground wiring layer and / or power supply wiring layer overlap with each other when seen through the plane. It can be further suppressed.

  Furthermore, according to the semiconductor device of the present invention, in the above configuration, the wavelength of the signal transmitted through the input / output signal wiring from the outer periphery of the ground wiring layer and / or the power wiring layer is not formed inside the wiring board. At a position within a distance corresponding to a length equal to or less than ¼, a plurality of ground through conductors are ¼ of the wavelength of a signal transmitted along the outer periphery of the non-formed portion of the ground wiring layer and / or the power wiring layer. By arranging at a pitch corresponding to the following length, a signal component having a length of 1/4 or more of the wavelength of the signal transmitted through the input / output signal wiring is shielded by the ground through conductor. It is possible to suppress leakage of a signal transmitted through the inside, and to further suppress transmission loss.

  Furthermore, according to the semiconductor device of the present invention, in the above-described configuration, the wavelength of the signal transmitted through the input / output signal line from the portion where the line width of the input / output signal line is narrowed to the outside is reduced to 1 By gradually widening the line width within a length range corresponding to / 4 or less, impedance fluctuations and signal reflection loss due to abrupt changes in the line width of the input / output signal wiring can be better suppressed.

  Furthermore, according to the semiconductor device of the present invention, in the above-described configuration, the wavelength of the signal transmitted through the input / output signal wiring from the center line of the input / output signal wiring is 1/4 or less within the mounting substrate. A length equal to or less than ¼ of the wavelength of a signal transmitted by surrounding a plurality of ground through conductors electrically connected to the ground layer so as to surround the input / output signal wiring at a position within a distance corresponding to the length Since the signal component having a length of 1/4 or more of the wavelength of the signal transmitted through the input / output signal wiring is shielded by the grounding through conductor by arranging at a pitch corresponding to the mounting board, the mounting substrate It is possible to suppress the leakage of the signal transmitted on the top, and to further suppress the transmission loss.

  Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor device of the present invention, and FIG. 2 is an enlarged plan perspective view of a main part of a peripheral portion of a connection portion between a wiring board and a mounting board in the semiconductor device of FIG.

  In this embodiment, the semiconductor device is a wiring in which a ground wiring layer and / or power wiring layers 4a and 4b and a connection electrode 7b are provided on an insulating substrate 2 formed with a plurality of insulating layers 2a to 2d. A substrate 1 and a mounting substrate 10 on which the wiring substrate 1 is mounted are provided.

  The insulating layers 2a to 2d constituting the insulating substrate 2 of the wiring substrate 1 may be made of different materials or the same material. However, in consideration of productivity, mechanical strength, etc., it is basically better to form them with the same material.

  A signal wiring group 3 is formed on the insulating layer 2c, and a ground wiring layer and / or power wiring layers 4a and 4b having a large area are formed on the insulating layers 2b and 2d so as to face the signal wiring group 3. The signal wiring group 3 has a stripline structure. The ground wiring layer and / or the power supply wiring layers 4 a and 4 b may be replaced and arranged according to the specifications of the wiring board 1.

  Further, by setting the wiring width of each signal wiring of the signal wiring group 3 and the thickness of the insulating layers 2b and 2c interposed between the signal wiring group 3 and the ground wiring layer and / or the power wiring layers 4a and 4b, Since the characteristic impedance of the signal wiring group 3 can be set to an arbitrary value, the signal wiring group 3 having good transmission characteristics can be formed. The characteristic impedance of the signal wiring group 3 is set to 50Ω, for example.

  In addition to the microstrip line structure formed by forming a ground wiring layer and / or a power supply wiring layer so as to face the signal wiring group 3, the signal wiring group 3 has a ground wiring layer and / or Alternatively, it may be a strip line structure formed by forming a power supply wiring layer, or a coplanar line structure formed by forming the same plane ground wiring layer and / or the power supply wiring layer adjacent to the signal wiring group 3 at a predetermined interval.

  In the example of the embodiment shown in FIG. 1, on the upper surface of the wiring substrate 1, a semiconductor integrated circuit element such as an IC or LSI that operates at high speed, an optical semiconductor element such as a semiconductor laser (LD), or a photodiode (PD), etc. A semiconductor element 5 and an electronic component are mounted, and a conductor bump 6 made of solder such as tin-lead (Sn-Pb) alloy, gold (Au), or the like, and a semiconductor element connection electrode 7a for connecting the semiconductor element 5 are connected. Are electrically connected to the wiring board 1. On the lower surface of the wiring substrate 1, connection electrodes 7 b for inputting / outputting signals and supplying electric charges to the semiconductor element 5 are formed.

  The signal wiring group 3 is electrically connected to the semiconductor element connection electrode 7a via the signal through conductor 8 in order to input / output signals to / from the outside. The semiconductor element connection electrode 7a is made of tin- The electrodes are electrically connected to the electrodes of the semiconductor element 5 via conductor bumps 6 made of solder such as lead (Sn—Pb) alloy or gold (Au).

  Further, the wiring substrate 1 is connected to the mounting substrate 10 via conductor bumps 6b made of a tin-lead (Sn—Pb) alloy or the like, and a signal wiring 11 (signal for input / output) formed on the mounting substrate 10. Signals are transmitted between the wiring board 1 and the mounting board 10 via wiring (hereinafter also referred to as input / output signal wiring).

  The insulating layers 2e and 2f constituting the insulating substrate 2 of the mounting substrate 10 may be made of different materials or the same material, but are formed of insulating materials having the same relative dielectric constant in consideration of productivity and mechanical strength. Is preferable.

  The input / output signal wiring 11 is a high-frequency signal transmitted between a semiconductor device including the wiring substrate 1 and a mounting substrate 10 on which the wiring substrate 1 is mounted, and an electronic device on which the semiconductor device is mounted. And the like.

  In addition, a ground layer 12 is disposed on the same surface of the mounting substrate 10 as the input / output signal wiring 11 is disposed at a predetermined distance from the input / output signal wiring 11.

  The input / output signal wiring 11 forms a so-called coplanar transmission line together with the ground layer 12 on the same surface.

  In addition to the microstrip line structure in which a ground layer is formed opposite to the input / output signal wiring 11, the input / output signal wiring 11 has a ground layer or a power supply layer above and below the input / output signal wiring 11. It may be a strip line structure formed, or a coplanar line structure formed by forming the same surface ground layer at a predetermined interval adjacent to the input / output signal wiring 11.

  Moreover, a chip resistor, a thin film resistor, a coil inductor, a cross inductor, a chip capacitor, an electrolytic capacitor, or the like may be mounted on the wiring board 1 to constitute an electronic circuit module or the like.

  On the other hand, the planar view shape of each of the insulating layers 2a to 2f may be a diamond shape, a hexagonal shape, an octagonal shape or the like in addition to a square shape or a rectangular shape. Also, the insulating layers 2a to 2d on the wiring board 1 side and the insulating layers 2e and 2f on the mounting board 10 side may have different shapes and dimensions.

  A wiring board 1 used in such a semiconductor device includes an electronic component storage package such as a semiconductor element storage package, an electronic component mounting substrate, a so-called multichip module or multichip package on which a large number of semiconductor elements are mounted. Or used as a motherboard.

  Next, the structure around the connection portion between the wiring board 1 and the mounting board 10 in the semiconductor device of the present invention will be described in detail with reference to FIG. FIG. 2 is an enlarged plan perspective view showing the main part of FIG. 1. The same components as those in FIG.

  In the semiconductor device shown in the figure, the input / output signal wiring 11 is formed so that the line width of the input / output signal wiring 11 is narrower than the line width in other parts at a part 14 overlapping the ground wiring layer and 4b in a plan view. Has been.

  In this case, since the input / output signal wiring 11 overlaps with the ground wiring layer and / or the power supply wiring layer in a plan view, the input / output signal wiring 11 is narrower than the line width in other parts. Impedance reduction of the input / output signal wiring 11 can be suppressed by increasing the inductive component of the input / output signal wiring 11 at a portion where the signal wiring 11 and the ground wiring layer and / or the power supply wiring layer overlap each other in a plan view. As a result, reflection loss due to impedance mismatch due to a change in the line structure of the input / output signal wiring 11 is suppressed at a portion where the input / output signal wiring 11 overlaps with the ground wiring layer and / or the power supply wiring layer in plan view. It becomes possible. The line width of the input / output signal wiring 11 at the portion where the input / output signal wiring and the ground wiring layer overlap with each other in plan view is as follows: the input / output wiring and the ground wiring layer 4b of the wiring board 1, the insulating layer 2d, and the mounting board 10; The line width of the input / output signal wiring may be set so that the impedance of the transmission line formed by the ground layer 12b, the ground layer 12a of the same layer as the input / output wiring, and the insulating layer 2e is 50 ohms.

  Thus, a highly reliable semiconductor device that is small and thin and has good signal transmission characteristics can be obtained.

  Further, in the semiconductor device described above, the connection electrode is provided on the outer peripheral portion of the main surface of the wiring board, the region facing the connection electrode, the input / output signal wiring 11, the ground wiring layer, and / or the power wiring layer. It is preferable to form a non-formation part of the ground wiring layer and / or the power wiring layer in a portion where they are overlapped in a plan view.

  In this case, the area where the input / output signal wiring 11 and the ground wiring layer and / or the power supply wiring layer overlap with each other in plan view is reduced, and the input / output signal wiring 11 and the ground wiring layer and / or the power supply wiring layer 34b are reduced. The impedance mismatch itself due to the reduction in impedance is suppressed due to the reduction of the parasitic capacitance caused by the overlapping of the two in perspective, so that the input / output signal wiring 11 and the ground wiring layer and / or the power supply wiring layer are suppressed. It is possible to better suppress the reflection loss due to impedance mismatch at a portion where the two overlap with each other in a plan view.

  Further, in the ground wiring layer and / or the power supply wiring layer 4b, a non-formation portion 15 of the ground wiring layer and / or the power supply wiring layer is formed in a portion 14 that overlaps with the ground wiring layer and / or the power supply wiring layer 4b in a plan view. The plurality of grounding through conductors 9c are not disposed at positions within a distance corresponding to a length equal to or less than ¼ of the wavelength of the signal transmitted through the input / output signal wiring 11 from the outer periphery of the non-forming portion 15. It is preferable to form the input / output signal wiring 11 along the outer periphery of the forming portion 15 at a pitch corresponding to a length of 13 or less of the wavelength of the transmitted signal.

  In this case, since the signal component having a length of 1/4 or more of the wavelength of the signal transmitted through the input / output signal wiring 11 is shielded by the ground through conductor, leakage of the signal transmitted through the wiring board is suppressed. And transmission loss can be suppressed more effectively.

  Furthermore, the input / output signal wiring 11 is seen from the plan view, and the input / output signal wiring 11 is directed outward from a portion 14 (a portion having a reduced line width) overlapping the ground wiring layer and / or the power supply wiring layer 4b. It is preferable to form a portion 13 whose line width gradually increases within a length range corresponding to ¼ or less of the wavelength of the signal transmitted.

  In this case, it is possible to better suppress impedance variation and signal reflection loss due to a sudden change in the line width of the input / output signal wiring 11.

  Further, a ground layer 12 is formed on the mounting substrate 10 so as to surround the input / output signal wiring 11, and the wavelength of the signal transmitted through the input / output signal wiring 11 from the center line of the input / output signal wiring 11 is 1 A plurality of ground through conductors 9b that are electrically connected to the ground layer are disposed within a distance corresponding to a length equal to or less than / 4 so that the input / output signal wirings 11 surround the input / output signal wirings 11. It is preferable to form with a pitch corresponding to a length equal to or less than ¼ of the wavelength of the transmitted signal.

  In this case, since the signal component having a length of 1/4 or more of the wavelength of the signal transmitted through the input / output signal wiring is shielded by the ground through conductor, the leakage of the signal transmitted on the mounting board is suppressed. And transmission loss can be better suppressed.

  Next, examples of materials and manufacturing methods for forming each part of the semiconductor device described above will be described.

  In the wiring substrate 1 and the mounting substrate 10 used in the semiconductor device of the present embodiment described above, the insulating layers 2a to 2f are formed by, for example, a ceramic green sheet lamination method. In this case, the insulating layers 2a to 2f are made of an inorganic insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a mullite sintered body, or a glass ceramic. Made of material. The insulating layers 2a to 2f are formed by bonding an organic insulating material such as polyimide, epoxy resin, fluororesin, polynorbornene or benzocyclobutene, or inorganic insulating powder such as ceramic powder with a thermosetting resin such as epoxy resin. It may be made of an electrically insulating material such as a composite insulating material.

  When the insulating layers 2a to 2d on the wiring board 1 side and the insulating layers 2e and 2f on the mounting board 10 side are made of an aluminum oxide sintered body, these insulating layers 2a to 2f are first made of aluminum oxide, silicon oxide, A ceramic green sheet is obtained by adding a suitable organic binder, a solvent, or the like to a raw material powder such as calcium oxide or magnesium oxide to form a slurry, which is formed into a sheet using a doctor blade method or the like. Then, a signal paste group 3 and a metal paste that forms each conductor layer are printed and applied in a predetermined pattern on the ceramic green sheet, and these are laminated vertically, and finally, laminated layers composed of insulating layers 2a to 2d on the wiring substrate 1 side. The laminated body composed of the body and the insulating layers 2e and 2f on the mounting substrate 10 side is individually fired at a temperature of about 1500 ° C. in a reducing atmosphere.

  Further, when the insulating layers 2a to 2d on the wiring board 1 side and the insulating layers 2e and 2f on the mounting board 10 side are made of an epoxy resin, first, a thermosetting epoxy resin in which ceramics made of an aluminum oxide sintered body is mixed. Alternatively, an organic resin precursor is deposited on the upper surface of an insulating layer made of glass epoxy resin or the like by impregnating an epoxy resin into a glass cloth base material woven with glass fibers by spin coating or curtain coating. Is thermally cured to form an insulating layer. This insulating layer and a thin film wiring conductor layer formed by adopting a copper layer by adopting a thin film forming technique such as electroless plating or vapor deposition and a photolithography technique are alternately laminated to insulate the wiring substrate 1 side. The laminated body composed of the layers 2a to 2d and the laminated body composed of the insulating layers 2e and 2f on the mounting substrate 10 side are individually heated and cured at a temperature of about 170 ° C., respectively.

  The thicknesses of these insulating layers 2a to 2f are set so as to satisfy the conditions such as mechanical strength and electrical characteristics corresponding to the required specifications according to the characteristics of the materials used.

  The insulating layers 2a to 2d on the wiring board 1 side and the insulating layers 2e and 2f on the mounting board 10 side may be formed of different materials.

  The signal wiring group 3, the ground wiring layer and / or the power supply wiring layer 4, and the ground layer 12 are, for example, tungsten (W), molybdenum (Mo), molybdenum-manganese (Mo-Mn), copper (Cu), silver. Metal powder metallization such as (Ag) or silver-palladium (Ag-Pd), or copper (Cu), silver (Ag), nickel (Ni), chromium (Cr), titanium (Ti), gold (Au) or niobium (Nb) or a thin film of a metal material such as an alloy thereof, metallization, or the like.

  Specifically, when the signal wiring group 3 and the ground wiring layer and / or the power wiring layer 4 are formed of W metal powder metallization, a metal obtained by adding and mixing an appropriate organic binder, solvent, etc. to the W powder. The paste is printed and applied in a predetermined pattern on ceramic green sheets to be the insulating layers 2a to 2d on the wiring substrate 1 side, and this is fired together with a laminate of ceramic green sheets.

  Further, when the input / output signal wiring 11 and the ground layer 12 are formed of copper metallization, a copper foil is pasted on the resin layers to be the insulating layers 2e and 2f to form a metal metallization, and then input / output by photolithography. It is formed by etching a predetermined wiring pattern such as the signal wiring 11. Further, the line width of the portion 14 where the input / output signal wiring and the ground wiring layer and / or the power supply wiring layer overlap with each other in a plan view is determined based on the input / output signal wiring and ground wiring layer and / or the mask plate used in photolithography. It is formed by narrowing the line width of the portion where it overlaps with the power supply wiring layer in plan view.

  Further, when the input / output signal wiring 11 and the ground layer 12 are formed of a metal thin film, the metal thin film is formed on the resin layers to be the insulating layers 2e and 2f by, for example, a sputtering method, a vacuum evaporation method, or a plating method. It is formed by etching a predetermined wiring pattern such as the input / output signal wiring 11 by a lithography method.

  Note that the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the present invention. For example, the signal wiring group 3 may be formed on the main surface of the wiring board 1. Further, underfill or the like may be injected into the connection portion between the wiring board 1 and the mounting board 10.

  A wiring board 1 according to the semiconductor device of the present invention having the configuration shown in FIG. 1 was produced as follows. Insulating layers 2a to 2d each having a thickness of 0.2 mm made of an aluminum oxide sintered body are formed on an insulating substrate made of an aluminum oxide sintered body by using a known ceramic wiring board manufacturing method. The signal wiring group, the inner layer ground conductor, the signal through conductor, and the ground through conductor were formed. The signal wiring group 3 has a line width of 75 μm, the inner layer ground conductor 4b has a conductor thickness of 10 μm, and the signal through conductor 8 and the ground through conductor 9c have a diameter of 75 μm. The connection electrodes 7b were formed with a diameter of 0.5 mm and intervals of 0.8 mm, and the conductor bumps 6b were solder balls with a diameter of 0.3 mm. In addition, an underfill having a dielectric constant of 3.8 is injected into the connection portion between the wiring board 1 and the mounting board 10 in order to improve mounting reliability.

  Next, a mounting substrate 10 according to the semiconductor device of the present invention having the configuration shown in FIG. 1 was produced as follows. Using a conventionally known method for manufacturing a mounting substrate made of an organic insulator, the thickness of each of the insulating layers 2e and 2f is 0.2 mm, and the input / output signal wiring 11, the grounding layer 12 and the grounding through conductor 9b are made of Cu. The mounting board | substrate which has was created. Here, the input / output signal wiring 11 is formed with a line width of 400 μm and a conductor thickness of 35 μm, and the ground through conductor 9b is formed with a diameter of 200 μm, and the input / output signal wiring 11 and the ground wiring layer and / or the power supply wiring layer 4b. Is formed with a length of 450 μm.

  In this case, as shown in FIG. 2, the line width of the input / output signal wiring 11 is 250 μm at a portion 14 where the input / output signal wiring 11 and the ground wiring layer and / or the power supply wiring layer 4 b overlap in plan view. Formed with.

  Further, the ground wiring layer and / or the power supply wiring facing the input / output signal wiring 11 of the wiring board 1 at a portion 14 where the input / output signal wiring 11 and the ground wiring layer and / or the power wiring layer 4b overlap with each other in a plan view. A conductor non-formation part was formed in the layer with a width of 550 μm and a length of 450 μm.

  Further, ground through conductors 9c having a diameter of 75 μm were formed at intervals of 300 μm at a distance of 325 μm from the center of the conductor non-forming portion 15 formed in the inner ground wiring layer and / or the power wiring layer 4b of the wiring board 1.

  Furthermore, the input / output signal wiring 11 was formed so that the wiring width gradually increased to a length of 50 μm from the narrowed portion of the input / output signal wiring 11.

  Furthermore, the ground through conductors 9b were formed in the ground layer 12 on the mounting substrate at a distance of 500 μm from the center of the input / output signal wiring 11 at an interval of 500 μm.

  In the semiconductor device having the above configuration, when a high frequency signal of 30 GHz is input to the input / output signal wiring group 3, the discontinuity of the transmission line at the connection portion between the wiring substrate 1 and the mounting substrate 10 can be reduced, and the high frequency signal can be reduced. Signal reflection loss can be suppressed. That is, the reflection loss of the high frequency signal at the connection portion between the wiring board 1 and the mounting board 10 is about −17.6 dB, which is an extremely small value.

  In Comparative Example 1, the input / output signal wiring 11 and the ground wiring layer and / or the power supply wiring layer 4b overlap each other in a plan view, and the input / output signal wiring 11 has a line width of 400 μm. In the substrate, the reflection level of the high-frequency signal at the connection portion between the wiring substrate 1 and the mounting substrate 10 was as high as about −12.2 dB.

It is sectional drawing which shows an example of embodiment of the semiconductor device of this invention. It is a principal part expansion plane perspective view which shows an example of embodiment of the semiconductor device of this invention. It is sectional drawing which shows an example of embodiment of the conventional semiconductor device. It is a partial expansion plane perspective view which shows an example of embodiment of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Wiring board 2 ... Insulating board 2a-2d ... Insulating layer 2e-2f ... Insulating layer of mounting board 3 ... Signal wiring group 4 ... Ground wiring layer and / or Or power supply wiring layer 4a ... power supply wiring layer 4b ... ground wiring layer 5 ... semiconductor element 6 ... conductor bump 7 ... connection electrode 7a ... semiconductor element connection electrode 8 ... Signal through conductor 9 ... Ground through conductor and / or power through conductor 9a ... Power through conductor on wiring board 9b ... Ground through conductor on mounting board 9c ... Ground through conductor on wiring board 10 ... Mounting board 11... Signal wiring 12... Ground layer 12 a... Ground layer on the same plane as input / output signal wiring 13... ..I / O signal distribution and ground wiring layer and / or power supply wiring layer are flat Part to be seen through and overlapping 15 ... Non-formed part of ground wiring layer and / or power wiring layer

Claims (5)

A wiring board having a ground wiring layer and / or a power supply wiring layer inside and having a connection electrode formed on the main surface, a semiconductor element mounted on the wiring substrate, and the wiring board mounted on the main surface The main surface includes a signal wiring electrically connected to the connection electrode, and a mounting substrate having a ground layer disposed on the same surface at a predetermined distance from the signal wiring. In the semiconductor device, the signal wiring has a line width in a portion overlapping with the ground wiring layer and / or the power supply wiring layer as seen in a plan view, which is narrower than a line width in other portions. . The connection electrode is provided on the outer peripheral portion of the main surface of the wiring board, and the region facing the connection electrode overlaps the signal wiring, the ground wiring layer, and / or the power wiring layer in a plan view The semiconductor device according to claim 1, wherein a non-formation portion of the ground wiring layer and / or the power wiring layer is formed. Inside the wiring board, at a position within a distance corresponding to a length equal to or less than ¼ of the wavelength of the signal transmitted through the signal wiring from the outer periphery of the non-formed portion of the ground wiring layer and / or the power wiring layer. 3. The semiconductor device according to claim 2, wherein a plurality of ground through conductors are arranged at a pitch corresponding to a length equal to or less than ¼ of the wavelength along the outer periphery of the non-formed portion. The line width of the signal wiring is gradually widened from a portion where the line width is narrowed toward the outside in a length range corresponding to 1/4 or less of the wavelength of the signal transmitted through the signal wiring. The semiconductor device according to claim 1. Inside the mounting board, electrically connected to the ground layer at a position within a distance corresponding to ¼ or less of the wavelength of the signal transmitted through the signal wiring from the center line of the signal wiring. 6. The plurality of ground through conductors to be arranged are arranged at a pitch corresponding to a length equal to or less than ¼ of the wavelength so as to surround the signal wiring. A semiconductor device according to 1.

Images