JP2006270201A - Data reading apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data reading apparatus capable of preventing the erroneous logical determination of reception data, when a reception signal waveform is distorted due to the influence of noise, or the like. <P>SOLUTION: Two determination sections output two signals for determination that become active, when the level of an analog signal demodulated by receiving a response signal from an IC card is high and low. An HL determination/non-determination signal generation section outputs an HL determination signal for each prescribed determination period, and outputs an indefinite determination signal, when both the two signals for determination become inactive. When the indefinite determination signal is outputted, logic determining section performs correction, by estimating the indefinite level to be either a high or low level for determining the logic of received data, based on the data level determined at a period, immediately prior to or after the determination period. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data reader that reads data stored in a data carrier by performing wireless communication with the data carrier.

For example, a reader / writer that performs wireless communication with a data carrier such as an IC card or an RFID tag and reads or writes data demodulates the received signal when receiving a response signal from the data carrier, and sets the level of the demodulated signal to two. Value (high, low). Then, based on the binarized signal or its signal change, data logic judgment (1, 0) is performed.
For example, Patent Document 1 discloses an example of the conventional technique as described above.
JP 2000-307465 A

However, the signal received by the data reader may be distorted due to the presence of external noise and the waveform amplitude may change or the timing at which the signal changes may be shifted. If such distortion occurs in the signal waveform, it may be possible to make a mistake in the determination of the high or low level at the stage of binarizing the signal level. An error also occurs in the logic judgment.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data reader capable of preventing erroneous determination of received data logic when the received signal waveform is distorted due to the influence of noise or the like. It is in.

  According to the data reader of claim 1, the first and second signal output means are active when the data level is high and low for the analog signal demodulated by receiving the response signal from the data carrier. The high / low level determination signal is output, and the data level determination means determines the binary data level used for the logical determination of the received data based on the high / low level determination signal for each predetermined determination cycle. The indeterminate level determining unit determines that the data level is indefinite when the data level determining unit cannot determine the binary data level in any one of the determination cycles. If it is determined, the indefinite level is estimated to be one of the binary levels based on the determined data level and corrected in the determination period immediately before or after the determination period. The logic determination unit determines the logic of the received data based on the determination result of the data level determination unit and the correction result of the level correction unit.

  That is, the response signal from the data carrier is premised on that one logical data value (1, 0) is encoded by one or more binary level (high, low) changes. Even if the received data level determination result in is “indeterminate”, whether the indefinite level originally indicates high or low due to the relationship with the data level determined in the preceding and subsequent periods It can be estimated and corrected. If the indeterminate level can be corrected, the logic determination means can correctly determine the logic of the received data, so that it is possible to prevent erroneous determination of the logic of the received data when the received signal waveform is distorted due to the influence of noise or the like. .

  According to the data reading device of the second aspect, either one of the first and second signal output means generates its own determination signal by inverting the level of the other determination signal. For example, if the level of the high level determination signal that is active when the data level is high is inverted, a low level determination signal that is active when the data level is low is generated. The same can be said for the opposite case. Therefore, if comprised in this way, a 1st and 2nd signal output means can be comprised easily.

According to the data reader of claim 3, any one of the first and second signal output means delays the phase of the other determination signal by a half period of the signal modulation period in the data carrier. A determination signal is generated. That is, the response signal from the data carrier encodes one logical data value with one or more binary level changes. Therefore, for example, in a pattern in which high and low levels continue alternately, a signal obtained by delaying the phase of one determination signal by a half cycle of the signal modulation period becomes the other determination signal.
Further, in the case where the same level determination continues due to the logical change of data, the original signal level and the signal level of the half-cycle phase lag are the same, and the indefinite level determination means even when the demodulated signal waveform is not distorted There are cases where it is determined as “indefinite”. However, even in such a case, the data level can be correctly corrected by the action of the level correction means, so that the first and second signal output means can be configured easily.

According to the data reader of claim 4, since the high-side first and second AND gates take the logical product of the high-level determination signal and the first and second synchronization signals, the output signal is It becomes high when the high level determination signal shows high level in the first half cycle and second half cycle, respectively. Further, since the low-side first and second AND gates take the logical product of the low-level determination signal and the first and second synchronization signals, the low-level determination signal is output in the first half cycle and the second half cycle, respectively. A high level is indicated when a high level is indicated.
Since the first OR gate takes the logical sum of the output signals of the high-side first AND gate and the low-side second AND gate, the high-level is obtained when the demodulated signal waveform is a pattern alternately showing high and low levels. Continue to output, and continue to output low level when the pattern is replaced. The second OR gate outputs a signal obtained by inverting the output signal of the first OR gate.

The data level determination means performs level determination based on the output signal of the first or second OR gate. For example, if the output signal of the first OR gate is high and the output signal of the second OR gate is low, the binary data level for reception data logic determination is determined as “high”, and conversely, If the output signal of the first OR gate is low and the output signal of the second OR gate is high, the binary data level is determined to be “low”.
If the level of the demodulated signal waveform is “undefined”, the high and low level determination signals are both inactive, and the output signals of the first and second OR gates may be low. At this time, the level determination in the data level determination means may be any. That is, the indeterminate level determination means compares the signal output states of the first and second OR gates and, for example, activates the indeterminate level determination signal if any of the output signals is at a low level. Regardless of the level determination result in the means, the data level is corrected by the level correction means. Therefore, the data level determination means can be configured using a logic gate.

  According to the data reader of the fifth aspect, the response signal from the data carrier is a signal obtained by modulating a carrier wave using any one of a Manchester encoded signal, a BPSK modulated signal, and a subcarrier Manchester signal. That is, since these signals are signals that encode one logical data value by one or more binary level changes, the present invention is effectively applied to a data carrier that uses these as modulation signals. Can do.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 8 is a functional block diagram showing an electrical configuration of a reader / writer that reads and writes data from and on an IC card using radio signals. A reader / writer (data reader) 1 is controlled by a control circuit 2 constituted by a microcomputer. The control circuit 2 controls the reader / writer 1 according to a control program stored in an internal memory. Transmission data output by the control circuit 2 is encoded by the encoding circuit 3 and output to the modulation circuit 4.

A carrier wave signal output from the oscillator 5 is supplied to the modulation circuit 4. The modulation circuit 4 performs ASK (Amplitude Shift Keying) modulation by multiplying the carrier signal and the encoded transmission signal (modulation signal) output from the encoding circuit 3, and supplies the modulated signal to the amplifier circuit 6. The amplifier circuit 6 amplifies the signal and outputs it to the antenna 7. Then, a radio signal is transmitted from the antenna 7 to the outside.
An input terminal of a demodulation circuit 8 is connected to the antenna 7, and a radio wave signal received by the antenna 7 is input to the demodulation circuit 8. The signal demodulated by the demodulation circuit 8 is output to the decoding processing circuit 9. The decoding processing circuit 9 processes the analog reception signal demodulated by the demodulation circuit 8 to decode the reception data, and outputs the decoded data to the control circuit 2 as digital data.

FIG. 9 shows an electrical configuration of the IC card (data carrier) 11. The IC card 11 includes an antenna 12, a power supply circuit 13, a demodulation circuit 14, a control circuit 15, a memory 16, a load modulation circuit 17, and the like. A capacitor 18 is connected to the antenna 12 in parallel. When the RF tag 11 receives the carrier wave signal transmitted from the reader / writer 1 via the antenna 12, the power supply circuit 13 rectifies the carrier wave signal to generate an operating power source, and a control circuit 15 configured by a microcomputer and Supply to other components.
The transmission data from the reader / writer 1 superimposed on the carrier wave signal is demodulated by the demodulation circuit 14 and output to the control circuit 15. When the operation circuit is supplied with power and activated, the control circuit 15 receives transmission data from the reader / writer 1 and reads data stored in the memory 16, and writes data when a write command is transmitted. A series circuit of a resistor and a switch constituting the load modulation circuit 17 is connected to the antenna 12 in parallel. The load modulation circuit 17 performs load modulation on the carrier wave signal with the data output from the control circuit 15.

FIG. 3A shows a modulation signal used by the IC card 11 to modulate a carrier wave signal. This modulation signal uses a Manchester code, and encodes a data logical value “0” at a rising edge where the data level changes from low (L) to high (H), and conversely, the data level changes from high to low. The data logical value “1” is encoded with the falling edge that changes.
When the IC card 11 returns a response signal to the reader / writer 1 side, first, a preamble that makes the dummy data value “1” continue for a predetermined period is transmitted. Since the start bit of valid data starts from “0”, the reader / writer 1 recognizes the start bit by a change (phase change) from the data value “1” to “0”. If the first phase change is detected, the division of the data modulation period can be determined based on the change time point.

  In FIG. 3B, the waveforms of the data logical values “0” and “1” are independently extracted and shown. If the data level of the first half of the modulation period is low, the second half is high, and the first half is high. In the second half, there is only one pattern of low. Therefore, as shown in FIG. 3C, if the first half level is “undefined” and the second half level is high, the first half level can be corrected to be low.

  Next, the outline of the present invention will be described in principle. FIG. 2 shows an example of signal processing performed by the reader / writer 1 in the demodulation processing circuit 9. FIG. 2A shows a modulation signal (Manchester code) on the IC card 11 side, and FIG. 2B is obtained by the reader / writer 1 receiving and demodulating a response signal from the IC card 11. An analog signal waveform is shown. In the present invention, a threshold value for determining a high level and a threshold value for determining a low level are individually set for the analog reception signal. That is, the former is set to a potential higher than the center potential of the analog signal amplitude, and the latter is set to a potential lower than the center potential.

In the present invention, by making a determination based on two threshold values of high and low levels, as shown in FIG. 2E, the binarized signal can be determined as three states of high, low, and indefinite. That is, “indefinite” indicates a state in which the received signal level is not determined to be high or low. Then, from the binarized signal shown in FIG. 2 (e), a signal for determining the logic of the received data (duty 50%) is generated with a phase delay of ½ of the signal modulation period on the IC card 11 side. Based on the logic determination signal (level correction signal), the received data is logically determined (see FIG. 2G).
2 (c) and 2 (d) show level determination states that have been conventionally performed for comparison. That is, conventionally, only one threshold value (for example, a potential corresponding to the high level threshold value of the present invention) is set for an analog reception signal to perform binarization determination. Since FIG. 2 shows a case where the received signal waveform is normal, the patterns of the conventional logic determination signal (d) and the level correction signal (f) of the present invention match.

  On the other hand, FIG. 1 shows a case where distortion occurs in the received signal waveform (b). At this time, in the conventional binarized signal (c), the low level is determined at the timing when the high level should be determined originally, so that an error occurs in the logic determination signal in (d). On the other hand, in the case of the present invention, the binarized signal (e) indicates “undefined” unless it is determined to be a high or low level due to the occurrence of distortion in the received signal waveform (b). Then, based on the characteristics of the Manchester code, the waveform level at the timing when the binarized signal (e) indicates “indefinite” is set to “high” from the relationship with the level “low” at the previous determination timing. It can be corrected.

  FIG. 4A shows a schematic configuration for performing level correction as shown in FIG. The analog reception signal is given to a high level determination unit (first signal output unit) 21H and a low level determination unit (second signal output unit) 21L. In each of the determination units 21H and 21L, a high level threshold value and a low level threshold value are set. Compare. These determination units 21 may be configured by a comparator. Then, the comparison result of the determination units 21H and 21L is given to the binarized signal generation unit (data level determination means, indeterminate level determination means) 22 and synthesized, so that the binarized signal as shown in FIG. Is generated. The binarized signal is given to a level correction determination unit (level correction means, logic determination means) 23, and the level correction shown in FIG. 1 (f) and the logic determination shown in FIG. 1 (g) are performed.

FIG. 4B shows the internal configuration of the binarized signal generator 22. The binarized signal generator 22 includes counters 22a and 22b and a comparator 22c. The counters 22a and 22b count the number of times that the high level is sampled at the timing when the sampling signal is applied during the period in which the high level determination signal and the low level determination signal output by the determination units 21H and 21L are active. (See FIG. 5). The sampling signal is obtained by dividing the clock signal oscillated and output from the external clock oscillator 24 by the frequency dividing circuit 25. The frequency dividing ratio in the frequency dividing circuit 25 is controlled by the control circuit 2. The counter values CH and CL of the counters 22a and 22b are compared at a timing designated by the control circuit 2 by a comparator 22c formed of a magnitude comparator.
In the comparator 22c, a comparison operation is performed every half of the signal modulation period, and a high level is determined if CH> CL and a low level is determined if CH <CL. When CH = CL, it is determined that the level is “undefined”.

FIG. 4C also shows the internal configuration of the level correction determination unit 23. One of the binarized signals given to the level correction determination unit 23 is output to the level correction unit 23b via the half cycle delay unit 23a as it is. The half-cycle delay unit 23a delays the phase of the binarized signal by ½ of the signal modulation cycle on the IC card 11 side, and outputs the delayed signal to the level correction unit 23b. Then, the level correction unit 23b performs level correction based on these signals, and outputs the correction result to the logic determination unit 23c.
FIG. 6A shows an example of correction processing in the level correction unit 23b. The level correction unit 23b is based on the result of sampling and comparing the level indicated by the binarized signal in the second half of one signal period and the level indicated by the binarized signal before the first half period (first half). , Correct the level.

FIG. 7 is a table showing a pattern for correcting an indefinite level for a Manchester code and a pattern for making a logical determination according to the determined binarized data. If the binarization level before the current and half cycle is determined, the logical value is determined without correction. Further, when the binarization levels at the current time and the half cycle before are the same or “undefined”, this indicates a logical value “0” or an “idle” state in which the data carrier side does not transmit a response signal. If the current level is “undefined” and the level before the half cycle is high or low, the current level is corrected to low or high, and the logical determination values based on the corrected levels are “1” and “high”, respectively. 0 ". If the current level is high or low and the level before the half cycle is “undefined”, the level before the half cycle is corrected to low or high, and the logical determination values based on the corrected levels are “0”, respectively. , “1”.
Then, based on the table of FIG. 7, correction and logic determination are performed as shown in FIG. 6B for the determination timings (1) to (4) shown in FIG. In the case of the determination timing (3), the present is corrected to the high level, and the half cycle before is corrected from “undefined” to the low level, and as a result, the logical determination is “0”.

  Next, a more specific embodiment of the present invention based on the above-described principle will be described with reference to FIGS. FIG. 10 is a functional block diagram showing an electrical configuration of the demodulation processing circuit 30. The output signals of the determination units 21H and 21L configured in the same manner as in FIG. 4 are given to a determination signal generation unit (data level determination unit, indefinite level determination unit) 26. The determination signal generation unit 26 is based on them. Then, the HL determination signal and the indeterminate determination signal are generated and output to the logic determination unit (level correction unit, logic determination unit) 27. The output signal of the high level determination unit 21H is given to the AND gates 31 and 32 (high side first and second AND gates) and the synchronization signal generation unit (first synchronization signal output means) 33, and the low level determination The output signal of the unit 21L is supplied to the AND gates 34 and 35 (row side first and second AND gates) and the synchronization signal generation unit 33.

  The synchronization signal generation unit 33 generates and outputs a synchronization signal A that is at a high level in synchronization with a period in which the analog reception signal waveform is at a high level, based on the high / low level determination signal. The generation process will be described with reference to FIG. When the IC card 11 starts returning a response signal, the synchronization signal generation unit 33 performs synchronization processing in the preamble period. That is, since data of logic “1” is continuously output in the preamble period, high and low level determination signals are alternately output. The signal modulation period is measured from the output interval of the determination signal. Then, a 50% duty synchronization signal A is generated with a period of ½ period from the phase shifted by ¼ period from the center (peak, ie, the center of the determination signal pulse) of the analog reception waveform. .

The synchronization signal A is given to the AND gates 31 and 34 and the synchronization signal inversion generation unit (second synchronization signal output means) 36. The synchronization signal inversion generation unit 36 inverts the synchronization signal A to synchronize. Signal B is generated and output. The synchronization signal B is given to AND gates 32 and 35.
The output terminals of the AND gates 31 and 34 are connected to one input terminals of OR gates 37 and 38 (first and second OR gates), respectively, and the output terminals of the AND gates 35 and 32 are OR gates 37. , 38 are respectively connected to the other input terminals. The output terminals of the OR gates 37 and 38 are respectively connected to the input terminals of the HL determination / indeterminate determination signal generator 39. The HL determination / indeterminate determination signal generator 39 receives the HL determination signal and the indeterminate determination signal. The data is output to the logic determination unit 27.

Next, the operation of the configuration shown in FIG. 10 will be described with reference to FIGS. FIG. 12 shows a case where the determination signals output from the high level determination unit 21H and the low level determination unit 21L are 50% duty pulse signals, and the analog reception signal waveform is not distorted.
The output signals of the AND gate 31 (_H1) of (5) and the AND gate 35 (_L2) of (6) are high level in synchronization with the first half and the second half of the modulation period, respectively, when the Manchester code indicates data “1”. Thus, when the Manchester code indicates data “0”, both indicate low level. On the other hand, the output signals of the AND gate 32 (_H2) of (7) and the AND gate 35 (_L1) of (8) both output a low level when the Manchester code indicates data “1”, and the Manchester code is data. When “0” is indicated, it becomes high level in synchronization with the latter half and the first half of the modulation period, respectively. The OR gate 37 (_1) of (9) is at a high level when the Manchester code indicates data “1”, and is at a low level when the Manchester code indicates data “0”. The OR gate 38 (_2) of (10) outputs an inverted signal of the OR gate 37.

The HL determination / indeterminate determination signal generation unit 39 generates and outputs an HL determination signal and an indeterminate determination signal with a delay of a half period of the signal modulation period (this is defined as one section) based on the output signals of the OR gates 37 and 38. . That is, if the binarization level determination of the analog reception signal is normally performed, the output signals of the OR gates 37 and 38 indicate mutually exclusive levels. Accordingly, the (11) HL determination signal may be output as it is when the exclusive OR of (9) and (10) is established. The indefinite determination signal (12) is inactive when the exclusive OR of (9) and (10) is established.
And in the logic determination part 27, if an indefinite determination signal is inactive, a logic determination will be performed based on the level pattern of the HL determination signal of 2 areas. In this case, the determination table shown in FIG. 14 is followed. That is, if both the HL determination signals in the first and second half sections are high (H), the logic “1” is determined, and if both are low (L), the logic “0” is determined.

  FIG. 13 shows a case where the determination signals output from the high level determination unit 21H and the low level determination unit 21L are 25% duty pulse signals, and the analog reception signal waveform is distorted. When the Manchester code is switched from logic “1” to logic “0”, the phase of the analog reception signal waveform is modulated, but the pulse width of the low level determination signal in (2) is slightly narrowed in that case. ing. However, even in this case, there is no influence on the HL determination and the logic determination.

When the analog reception signal waveform is distorted, the output levels of the OR gates 37 and 38 in (9) and (10) are both low, and the exclusive OR is not established. In response to this state, the HL determination / indeterminate determination signal generation unit 39 sets the indeterminate determination signal to active (high) in the next section. Then, since the data level of the previous section is low (L), the logic determination unit 27 directly connects the data level of the undefined section to the logic determination in this case according to the determination table shown in FIG. To be determined as logic “0”.
In addition, according to the determination table shown in FIG. 14, if the first half section is high and the second half section is “undefined”, the logic is corrected to “1”, and if the first half section is “undefined”, the second half section is high or low. If there are, corrections are made to logic "1" and "0", respectively.

  In the above, the case of the Manchester code is taken as an example. However, since the Manchester code is a kind of phase modulation signal, the case of the BPSK (Binary Phase Shift Keying) modulation signal shown in FIG. The determination table can be applied similarly. In this case, for example, the data level and the indeterminate determination are performed every subcarrier period that is 8 periods for one logical bit. Then, if the logic of all 8 cycles is “0”, it is determined as logic “0”, and if the logic of all 8 cycles is “1”, it is determined as logic “1”.

  Also in the case of the subcarrier Manchester signal shown in FIG. 15B, the data level and the indeterminate determination are performed every subcarrier period that is eight periods for one logical bit. Then, the logical determination in FIG. 16 indicates “1” when there is a subcarrier and “0” when there is no subcarrier, according to the table shown in FIG. The final logic value of the data value is “1” if the first four cycles of the eight cycles are “1”, “0” if the last four cycles are “0”, and “0” if the reverse pattern. Is determined.

  As described above, according to the present embodiment, the high level determination unit 21H and the low level determination unit 21L receive the response signal from the IC card 11 and demodulate the analog signal when the data level is high and low, respectively. An active high / low level determination signal is output, and the HL determination / indeterminate determination signal generation unit 39 outputs an HL determination signal used for logical determination of received data based on the high / low level determination signal for each predetermined determination cycle. At the same time, if the high and low level determination signals are both inactive and the binarized data level cannot be determined as high or low at the determination timing, an indefinite determination signal is output. When the indeterminate determination signal is output, the logic determination unit 27 sets the indeterminate level to either a high level or a low level based on the data level determined in the cycle immediately before or after the determination cycle. Correct the received data to determine the logic.

  That is, the Manchester code used for the response signal from the IC card 11 encodes one logical data value (1, 0) by a binary level (high, low) change. Even if the determination result of the data level is “undefined”, the original level can be estimated and corrected from the relationship with the data level determined in the previous and subsequent cycles. If the indefinite level can be corrected, the logic of the received data can be correctly determined. Therefore, it is possible to prevent erroneous determination of the logic of the received data when the received signal waveform is distorted due to the influence of noise or the like.

  Further, the determination signal generator 26 ANDs the high level determination signal and the synchronization signals A and B by the AND gates 31 and 32, and the low level determination signal and the synchronization signals A and B by the AND gates 34 and 35. Take AND. The OR gates 37 and 38 OR the output signals of the AND gates 31 and 35, 32 and 34, respectively, and the HL determination / indeterminate determination signal generation unit 39 performs exclusive logic on the output signals of the OR gates 37 and 38. The output data of the OR gate 37 is output as the HL determination signal when the sum is established, and the indeterminate determination signal is output when the exclusive OR is not established. Therefore, the determination signal generation unit 26 can be configured using a logic gate.

(Second embodiment)
18 and 19 show a second embodiment of the present invention. FIG. 18 is a diagram corresponding to FIG. In the second embodiment, the low level determination unit 21L is not used to generate the low level determination signal, but the high level determination signal is inverted by the NOT gate (second signal output means) 41. That is, as shown in FIG. 19, inversion of a signal that is active when it is at a high level can become a signal that becomes active when at a low level. With this configuration, two determination signals can be generated more easily. can do.

(Third embodiment)
20 and 21 show a third embodiment of the present invention. Also in the third embodiment, the low level determination unit 21L is not used to generate the low level determination signal, and the high level determination signal is generated by the delay circuit (second signal output means) 42 by a half period (= 1). It is generated by being delayed by (interval) (see FIG. 20). That is, as shown in FIG. 21, if the phase of a signal that is active when it is high is delayed by one section, if the received signal is a pattern that alternately outputs high and low, the signal that becomes active at low level Become.
However, in the case of a pattern in which the high level is continuous for two sections, a section in which high and low are simultaneously active and determined as “undefined” occurs in the latter half of the cycle. Since the current level is “L”, there is no problem because the level before the half cycle is corrected to “H”. Therefore, also in the third embodiment, two determination signals can be easily generated.

(Fourth embodiment)
22 and 23 show a fourth embodiment of the present invention. For example, in the timing chart shown in FIG. 13 in the first embodiment, the fourth embodiment assumes a case where both a high level determination signal and a low level determination signal may be active in one determination section. . FIG. 22 shows only one section corresponding to the signal waveforms (9) and (10) in FIG. In the fourth embodiment, as shown in FIG. 22, even when there is no period in which the high and low level determination signals are both active at the same time, determination of high, low, and indefinite is possible.

For example, in FIG. 23A, the carrier frequency in the response signal of the IC card 11 is 13.56 MHz, and the subcarrier frequency (in the case of Manchester code, the frequency corresponding to the transmission speed of logical data) is 1/16. In the case of 847 kHz, the sampling number is set to “8” for one section of the subcarrier period. Then, the number of times that the output signals (9) and (10) of the OR gates 37 and 38 become active is sampled.
In this case, if the number of times (9) becomes active is “2” or more and the number of times (10) becomes active is “0”, the level determination is made high. Even if the number of active times in (10) is other than “0”, the level determination is also made high when the difference from the number of active times in (9) is “3” or more. When the level determination is low, the relations (9) and (10) are reversed.

When either one of the active counts (9) and (10) is “0” and the other is “1” or less, either one is other than “0” and the difference from the other is “2” or less. In some cases (for example, corresponding to the case shown in FIG. 22 where (9) is “3” and (10) is “2”), the difference between the two is relatively small and the binarization level is increased. Therefore, it is difficult to determine any one of the rows, so that it is determined as “indefinite” (“indefinite determination” = “1”).
FIG. 23B corresponds to the case where the subcarrier frequency is 1/32, 1/62, 1/128 of 424 kHz, 212 kHz, 106 kHz with respect to the carrier frequency of 13.56 MHz. The case where the sampling number is set to “16” for one section of the carrier cycle is shown.
Also in the above cases, the binarized data levels “high”, “low”, and “undefined” level can be appropriately determined.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications are possible.
The present invention is not limited to the reader / writer 1 and may be applied to a data reading device having at least a data reading function.
The data carrier is not limited to an IC card and may be an RFID tag.
The data level determination means may be configured by software.
The modulation signal of the data carrier is not limited to a Manchester encoded signal, a BPSK modulated signal, and a subcarrier Manchester signal, and any signal that encodes one logical data value by one or more binary level changes should be applied. Can do.
The numerical comparison examples for determining the subcarrier frequency and the number of samples and “high”, “low”, and “indefinite” in the fourth embodiment are merely examples, and are appropriate according to individual designs. Set it.

FIG. 2 is a diagram corresponding to FIG. 2 in the first embodiment of the present invention, in which distortion occurs in the received signal waveform demodulated by the reader / writer. The figure which shows an example of the signal processing which a reader / writer performs in a demodulation processing circuit (A) is a diagram showing a modulated signal by a Manchester encoded signal, (b) is a diagram showing data logic values “0” and “1” taken out independently, and (c) is judged to be “undefined” in level. Of correction example when (A) is a functional block diagram showing a schematic configuration for performing the level correction shown in FIG. 1, (b) is a diagram showing an internal configuration of the binarized signal generation unit, (c) is a level correction determination unit Diagram showing internal configuration Timing chart explaining operation of binarized signal generator (A) is a figure which shows the example of a correction process in a level correction | amendment part, (b) is a figure which shows the correction process of (a) by a list. The figure which shows the table for performing a logic determination according to the case which corrects an indefinite level about Manchester code | cord | chord, and the confirmed binarization data Functional block diagram showing the electrical configuration of a reader / writer that reads and writes data from and to an IC card The figure which shows the electric constitution of the IC card Functional block diagram showing the electrical configuration of the demodulation processing circuit according to a specific embodiment The figure explaining operation | movement of a synchronous signal generation process Timing chart showing circuit operation when the high-level and low-level determination signals are 50% duty pulse signals and the analog reception signal waveform is not distorted FIG. 12 equivalent diagram in the case where the determination signal is a 25% duty pulse signal and the analog reception signal waveform is distorted The figure which shows the table for logic determination corresponding to the structure shown in FIG. (A) is a BPSK modulation signal waveform, (b) is a figure which shows a subcarrier Manchester signal waveform. FIG. 12 equivalent diagram corresponding to the subcarrier Manchester signal FIG. 14 equivalent diagram corresponding to the subcarrier Manchester signal FIG. 4 (a) equivalent view showing the second embodiment of the present invention. The figure which shows the signal waveform for high level and low level judgment FIG. 4 (a) equivalent view showing the third embodiment of the present invention. 19 equivalent figure FIG. 10 is a diagram showing a fourth embodiment of the present invention and corresponding to the signal waveforms (9) and (10) in FIG. 13 for only one section. 14 equivalent diagram

Explanation of symbols

In the drawing, 1 is a reader / writer (data reader), 11 is an IC card (data carrier), 21H is a high level determination unit (first signal output unit), 21L is a low level determination unit (second signal output unit), 22 Is a binarized signal generator (data level determination means, undefined level determination means), 23 is a level correction determination section (level correction means, logic determination means), and 26 is a determination signal generation section (data level determination means, undefined level determination means). Means), 27 is a logic determination unit (level correction means, logic determination unit), 31 and 32 are AND gates (high side first and second AND gates), 33 is a synchronization signal generation unit (first synchronization signal output means) , 34 and 35 are AND gates (low-side first and second AND gates), 36 is a synchronizing signal inversion generating unit (second synchronizing signal output means), and 37 and 38 are OR gates (first and second logic gates). Sum G), 41 a NOT gate (second signal output means), 42 denotes a delay circuit (second signal output means).

Claims (5)

In a data reader that reads data stored in the data carrier by performing wireless communication with the data carrier,
When an analog signal demodulated by receiving a response signal from the data carrier encodes one logical data value (1, 0) by one or more binary level (high, low) changes,
First signal output means for outputting a high level determination signal that becomes active when the data level of the demodulated signal is high;
Second signal output means for outputting a low level determination signal that becomes active when the data level of the demodulated signal is low;
Data level determination means for determining a binary data level to be used for logical determination of received data based on the high / low level determination signal for each predetermined determination period;
If the data level determination means cannot determine the binary data level in any of the determination cycles, the data level determination means determines whether the data level is indefinite,
When the indefinite level determination means determines that the data level is indefinite, the indefinite level is set to a binary level based on the data level determined by the data level determination means in the determination period immediately before or after the determination period. Level correction means for estimating and correcting to either,
A data reading apparatus comprising: logic determination means for determining the logic of received data based on the determination result of the data level determination means and the correction result of the level correction means.   2. The data reading apparatus according to claim 1, wherein either one of the first and second signal output means generates its own determination signal by inverting the level of the other determination signal.   One of the first and second signal output means generates its own determination signal by delaying the phase of the other determination signal by a half period of the signal modulation period in the data carrier. The data reader according to claim 1. The data level determination means includes
First synchronization signal output means for outputting a first synchronization signal that becomes high level in synchronization with the first half of the binary level change period in the demodulated signal;
Second synchronization signal output means for outputting a second synchronization signal that becomes high level in synchronization with the latter half of the change period;
A high-side first and second AND gate that takes a logical product of the high-level determination signal and the first and second synchronization signals;
A low-side first and second AND gate that takes a logical product of the low-level determination signal and the first and second synchronization signals;
A first OR gate that takes an OR of output signals of the high-side first AND gate and the low-side second AND gate;
A second logical sum gate that takes a logical sum of the output signals of the high-side second logical AND gate and the low-side first logical AND gate, and has a level based on the output signal of the first or second logical sum gate. Make a decision,
4. The indeterminate level determination means outputs an indeterminate level determination signal based on a result of comparing signal output states of the first and second OR gates. Data reader.   The response signal from the data carrier is a signal obtained by modulating a carrier wave using any one of a Manchester encoded signal, a BPSK modulated signal, and a subcarrier Manchester signal. Data reader.

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