JP2004328174A - Code decision apparatus, method thereof, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a code decision apparatus, a method thereof, and a program capable of extending a decision margin of a duty ratio to the utmost even when the duty ratio is greatly fluctuated in the case of deciding split phase coded data. <P>SOLUTION: The code decision apparatus carries out multi-point sampling for a bit period, respectively counts the number of prescribed logical values (e.g., '1') of sampling data for a first half and a second half of the bit period, takes majority decision to the counts of the first and second halves, and decides the data for the bit period on the basis of a result of the majority decision. Thus, even when the duty ratio is greatly fluctuated, the data can very simply and accurately be decided and the data decision margin can be extended. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a code determination device, a method thereof, and a program, and more particularly to a code determination method of a split-phase code encoded so that a logical value changes in a first half and a second half of a 1-bit period of a digital signal.
[0002]
[Prior art]
As shown in the example of FIG. 5, the encoded data by the split phase code divides a bit period for transmitting a 1-bit signal into two periods of a first half and a second half, and these two periods have different logics. This signal transmits a value code and identifies one piece of binary data by a combination of the codes of the two periods. In the example of FIG. 5, when the encoded data (decoded data) as the original data is “1”, the first half of the bit period is “1”, the second half is “0”, and When the original data is “0”, the first half of the bit period is “0” and the second half is “1”.
[0003]
In the split phase signal encoded in this way, a transition point (edge) of “1” → “0” or “0” → “1” necessarily exists at the center of the bit period, and the clock This is encoded data that enables continuous reproduction of components and is also effective in removing the DC component of the signal.
[0004]
As a conventional example of such a split-phase signal decoding method, as shown in FIG. 6, a data change point (edge) at the center of a bit period of the split-phase signal is detected, and 3/4 bits are detected from this edge. (For example, 24 clocks when sampling is performed with a 32 times clock), there is a device that determines whether it is “0” or “1” at a later timing. That is, data determination is performed only at the 24th clock sampling point (1 sampling point).
[0005]
FIG. 7 is a schematic block diagram of a code determination device in this case. The encoded data is input to the edge detection unit 11 and the determination unit 13. The edge detection unit 11 detects an edge at the center of each bit in the input encoded data, for example, in a repetition (known data pattern) of a pattern of “10” in a preamble section at the beginning of the data, and thereafter, Generates an edge detection timing pulse for each bit period corresponding to the edge detection timing.
[0006]
At this edge, a detection timing pulse is input to the determination pulse generator 12. In the determination pulse generator 12, a determination pulse having a timing of the center of the first half of each bit, that is, the timing of 3/4 bit later, based on this pulse, is generated. Generated. The determination unit 13 determines the logical value of the input coded data at the timing of the determination pulse, and outputs the decoded data according to the determination result.
[0007]
As other examples of the decoding method, there are techniques disclosed in Patent Documents 1 and 2. In Patent Document 1, for the purpose of eliminating the influence of waveform distortion due to noise or the like, data obtained by logically ANDing a reproduced clock having a period of one time slot (corresponding to one bit period) and an input split phase signal is described. The count value of the multi-point sampled data in one time slot is compared with a predetermined threshold value. If the count value exceeds a predetermined value, it is determined to be one logical value. If the count value is less than the predetermined value, it is determined to be another logical value. The technique to do is shown.
[0008]
In Patent Literature 2, the logic of the section in which the difference between the logic “1” and the logic “0” of the multipoint sampling is clear between the first half and the second half of the bit period is defined as the logic of the input bit. The technology to be adopted is shown. For example, the sum of the number of logic "1" or "0" in the first half and the number of logic "0" or "1" in the second half is obtained and compared with a predetermined value for determination. However, the purpose is to eliminate the influence of waveform distortion due to noise or the like.
[0009]
[Patent Document 1]
JP-A-59-139571 (pages 2, 3; FIGS. 2 to 4)
[0010]
[Patent Document 2]
JP-A-4-297166 (pages 2 to 4, FIGS. 1 to 5)
[0011]
[Problems to be solved by the invention]
In the prior art described with reference to FIGS. 6 and 7, when distortion occurs in received data due to noise on a transmission line, level fluctuation, imperfections in a transceiver or a modulator / demodulator, etc., particularly, “1” and “1” of data are received. When the duty ratio of “0” is largely changed, the determination may not be performed correctly because the determination timing is only one point. FIG. 8 shows an example of this. When the duty ratio of input data (encoded data) greatly changes from the waveform shown by the solid line to the one-dot chain line due to distortion due to noise or the like, the input data (encoded data) is originally "0". There is a drawback that it is mistaken for "1".
[0012]
In Patent Documents 1 and 2, although the above-mentioned disadvantage that the determination timing is only one point is solved, since the data determination is performed by comparing the count result of the multipoint sampling value with a predetermined threshold, the threshold is determined. May be erroneously determined in the case where the duty ratio is largely changed, and it is difficult to select the threshold.
[0013]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a code judging device capable of expanding a judging margin as much as possible with respect to noise, level fluctuation, and deterioration of a duty ratio caused by imperfections of a transceiver and a modem in a digital data transmission path. And its method and program.
[0014]
It is another object of the present invention to provide a code determination device, a method and a program thereof which do not require the use of a threshold value for data determination which is difficult to select.
[0015]
[Problems to be solved by the invention]
A sign judging device according to the present invention is a sign judging device for coded data coded so that a logical value changes between a first half and a second half of a 1-bit period of a digital signal, wherein each bit of the coded data is Sampling means for performing multi-point sampling of a period; counting means for counting predetermined logical values of the sampling data of the first half and the second half by the sampling means; and majority decision of the count values of the first half and the second half. Determining means for determining data in the bit period in accordance with the result of the majority decision.
[0016]
A code determination method according to the present invention is a code determination method for coded data that has been coded so that a logical value changes between the first half and the second half of a one-bit period of a digital signal, wherein each bit of the coded data is A sampling step of performing multi-point sampling of a period; a counting step of counting predetermined logical values of the sampling data of the first half and the second half of the sampling step; and a majority decision of the count values of the first half and the second half. A determining step of determining the data of the bit period in accordance with the result of the majority decision.
[0017]
A program according to the present invention is a program for causing a computer to execute a code determination method of coded data coded so that a logical value changes between a first half and a second half of a 1-bit period of a digital signal, A sampling step of performing multi-point sampling of each bit period of the encoded data; a counting step of counting predetermined logical values of the sampling data of the first half and the second half by the sampling step, respectively; A decision step of taking a majority decision of the count value and making a data decision of the bit period in accordance with the majority decision result.
[0018]
The operation of the present invention will be described. The multi-point sampling of the bit period is performed, the number of predetermined logical values (for example, “1”) of the sampling data of the first half and the second half of the bit period is counted, respectively, and the majority of the counted values of the first half and the second half are determined. Then, the data in the bit period is determined based on the result of the majority decision. By doing so, data determination can be performed very easily and accurately even if the duty ratio greatly changes, without using a threshold value that is difficult to set, and the data determination margin can be expanded.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. Prior to the description of the embodiment, in order to facilitate understanding of the present invention, first, the principle of the present invention will be described with reference to FIG. As shown in FIG. 2, first, a data change point (edge) at the center of the bit period of the split phase code to be decoded is detected. If it is assumed that the data of the bit period is sampled at multiple points, the sampling value is obtained for a half bit period (second half: for example, a period corresponding to 16 clocks when sampling is performed with a 32 times clock) from the edge detection timing. Are counted. Then, the number of “1” of the sampling value is counted for the first half １ ／ -bit period.
[0020]
The majority of the count values of the first half and the second half with respect to the edge obtained in this way is determined. If "1" is larger in the first half, the data in the bit period is "1" and vice versa. For example, it is determined to be "0". The edge is detected by using a repetition pattern (known pattern) of "10" of the preamble at the head of the data, and thereafter, the edge detection in each bit period is performed based on the detected edge timing. A timing pulse is generated.
[0021]
FIG. 1 is a functional block diagram of one embodiment for realizing the present invention according to the above principle. Referring to FIG. 1, input encoded data is supplied to a shift register 1 and an edge detection unit 2. The shift register 1 takes in data of one bit period with, for example, a 32 times clock, and takes in sampling data for 32 clocks.
[0022]
As described with reference to FIG. 2, the edge detection unit 2 uses the repetition pattern of “10” of the preamble of the data at the beginning of the input coded data to change the data change point (edge ) Is detected, and thereafter, an edge detection timing pulse for each bit period is generated based on the detected edge timing.
[0023]
The comparison timing generation unit 3 completes counting the sampling value of 1 bit in the first half and the second half of the bit period with reference to the edge detection timing pulse from the edge detection unit 2, that is, 1/2. At a timing after a bit (for example, equivalent to 16 clocks), a comparison timing for comparing (counting majority) the count values of the first half and the second half is generated.
[0024]
The CPU 4 responds to the edge detection timing pulse from the edge detection section 2 to count the number of “1” of the 32 sampling data in the 1-bit period taken in the shift register 1 between the second half and the first half. In addition to counting in each section, in response to the comparison timing from the comparison timing generation unit 3, a majority decision is made between the first half and the second half, and based on the result of the majority decision, the value of the bit period of the coded data in the corresponding bit period is determined. Is "1" or "0".
[0025]
The memory 5 is a memory in which the operation control procedure of the CPU 4 is stored in advance as a program, and also functions as a work memory. The data converter 6 has a function of outputting decoded data based on the result of the determination by the CPU 4.
[0026]
FIG. 3 is a flowchart showing the operation of the CPU 4. Referring to FIG. 3, when a pulse indicating an edge detection timing is input from the edge detection unit 2 (step S1), at that timing, the output of the first stage of the shift register 1 outputs the second half of the bit period 1 /. The sampling data of 2 bits (16 pieces) is sequentially derived, and the number of "1" is counted (step S2).
[0027]
When the pulse of the edge detection timing is generated, 16 pieces of sampling data corresponding to the first half of the bit period are taken into the shift register 1, and the sampling data of the second half is shifted from the next clock timing. Since the data is sequentially taken into the first stage of the register 1, the output of the first stage of the shift register is used as the sampling data of the second half.
[0028]
At the same time, the first sample data of the bit period is stored in the 16th stage of the shift register 1, so that the 16 sampled data in the first half is sequentially output using the 16th stage output of the shift register 1. It is taken into the CPU 4 and the number of "1" is counted (step S3).
[0029]
When the counting of "1" in each of the 16 sampling data of the first half and the second half is completed, the comparison timing is generated from the comparison timing generation unit 3, and in response to this, the first half bit and the second half 1 are calculated. The majority of the 2-bit count value is determined. Therefore, the two count values are compared (step S5), and if the count value of the first half bit is smaller than the count value of the second half bit (step S6), the data of the bit period becomes “0”. (Step S7). Otherwise, it is determined to be "1" (step S8). This determination result is output to the data conversion unit 6 (Step S9).
[0030]
FIG. 4 is a diagram for explaining the effect of the present invention. FIG. 4A shows a waveform of encoded data without distortion. FIG. 4B shows coded data having distortion. However, in the conventional method using only one decision timing A shown in FIG. It is an example of (small). In FIG. 4B, according to the method of the present invention, the count value of “1” in the first half is “7”, the count value of “1” in the second half is “16”,
Since the first half count value is smaller than the second half count value, the determination result is "0", and a correct determination is made.
[0031]
FIG. 4C shows an example of distortion (large) in which an erroneous determination is made in the conventional method, but a correct determination is made in the method of the present invention. In FIG. 4C, according to the method of the present invention, the count value of “1” in the first half is “9” and the count value of “1” in the second half is “16”.
Since the first half count value <the second half count value, the determination result is “0”, which is a correct determination.
[0032]
In the above embodiment, an example in which software processing is performed using the CPU has been described. Instead of the CPU, the first half counter and the second half counter for counting the output of the shift register are compared with the outputs of these counters. It may be constituted only by hardware using a comparator. If the counter is an up / down counter and the difference between the count value of the first half and the count value of the second half is obtained using this up / down counter, there is an advantage that a comparator is not required.
[0033]
Further, 32 sample data may be stored in the memory, and the number of "1" may be counted at a time, and various changes are possible.
[0034]
Although the sampling clock is 32 times, that is, the number of divisions (the number of samplings) of the bit period is set to 32, the present invention is not limited to this. If the number is 8 or more, good results can be obtained. Larger is better.
[0035]
As the encoded data, a split-phase code is assumed. However, the present invention is not limited to this. An encoding method in which the logical value changes between the first half and the second half of a digital signal during one bit period of the digital signal If the data is, the same can be applied.
[0036]
【The invention's effect】
As described above, according to the present invention, even when the duty ratio fluctuates greatly due to noise or the like, correct data determination can be performed, and thus there is an effect that the determination margin is expanded. Further, since it is not necessary to use a threshold value that is difficult to select, there is an effect that the design becomes easy.
[Brief description of the drawings]
FIG. 1 is a functional block diagram of an embodiment of the present invention.
FIG. 2 is a diagram for explaining the principle of the present invention.
FIG. 3 is a flowchart illustrating an operation of a CPU in FIG. 1;
FIG. 4 is a diagram for explaining the effect of the present invention in comparison with a conventional example.
FIG. 5 is a diagram illustrating split-phase encoded data.
FIG. 6 is a diagram illustrating a conventional data determination method for decoding split-phase encoded data.
FIG. 7 is a functional block diagram for conventional decoding.
FIG. 8 is a diagram illustrating a problem in the conventional example of FIG. 7;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Shift register 2 Edge detection part 3 Comparison timing generation part 4 CPU
5 Memory 6 Data conversion unit

Claims (9)

What is claimed is: 1. A code judging device for coded data coded so that a logical value changes between a first half and a second half of a 1-bit period of a digital signal,
Sampling means for performing multipoint sampling for each bit period of the encoded data,
Counting means for counting a predetermined logical value of the sampling data of the first half and the second half by the sampling means,
Determining means for taking a majority decision of the count values of the first half and the second half, and making data determination of the bit period according to the majority decision result;
A code determination device comprising: 2. The code judging device according to claim 1, wherein said judging means includes means for comparing the count values of the first half and the second half, and means for making the data judgment according to the comparison result. Means for detecting a change timing of a logical value in the one-bit period from a known data pattern in a predetermined period of the encoded data, and determining timing of a first half and a second half of each subsequent bit period, 3. The code judging device according to claim 1, wherein said counting means counts predetermined logical values of the sampling data of the second half and the first half in response to the timing. The code judging device according to any one of claims 1 to 3, wherein the encoded data is split phase code data. What is claimed is: 1. A method for judging the sign of encoded data encoded such that a logical value changes between a first half and a second half of a 1-bit period of a digital signal,
A sampling step of performing multipoint sampling for each bit period of the encoded data,
A counting step of counting a predetermined logical value of the sampling data of the first half and the second half by the sampling step,
A determination step of taking a majority decision of the count values of the first half and the second half, and making a data determination of the bit period according to the majority decision result;
A code determination method comprising: 5. The code determination method according to claim 4, wherein the determination step includes a step of comparing the count values of the first half and the second half, and a step of making the data determination according to the comparison result. Detecting a change timing of a logical value in the one-bit period from a known data pattern in a predetermined period of the encoded data, and determining a timing of a former half and a latter half of each subsequent bit period, 7. The code judging method according to claim 5, wherein said counting step includes counting predetermined logical values of the sampling data of the second half and the first half in response to the timing. 8. The code judging method according to claim 5, wherein said encoded data is split phase code data. A program for causing a computer to execute a code determination method of coded data coded so that a logical value changes between a first half and a second half of a 1-bit period of a digital signal,
A sampling step of performing multipoint sampling for each bit period of the encoded data,
A counting step of counting a predetermined logical value of the sampling data of the first half and the second half by the sampling step,
A determination step of taking a majority decision of the count values of the first half and the second half, and making a data determination of the bit period according to the majority decision result;
A computer-readable program characterized by comprising:

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