JP2009239842A - Radio communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To exclude a communication error caused by a null point in radio communication. <P>SOLUTION: A radio communication system comprises: an analog unit (11) for processing a received RF signal; a waveform shaping unit (16) for waveform-shaping an output signal from the analog unit; and a digital unit (12) for performing digital processing upon an output signal from the waveform shaping unit. The analog unit comprises an amplitude detection circuit (17) for performing amplitude detection upon the RF signal, and a phase detection circuit (18) for performing phase detection upon the RF signal. The digital unit comprises an output circuit for selectively transferring, to subsequent circuits, a detection result of the amplitude detection circuit and a detection result of the phase detection circuit in accordance with a receiving status of the RF signal. A null point in radio communications is avoided. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a wireless communication system, and more particularly to a wireless communication system that enables packet communication performed by dividing data into a plurality of packets.

  A load modulation method used in a non-contact (contactless) IC card reader / writer and a wireless communication system for NFC (Near Field Communication) is a kind of amplitude modulation, and the first device and the second device. When the carrier is transmitted from the first device to the second device in a state of being opposed to each other, the carrier is modulated with data to be transmitted by the second device, and is received by the first device. With this, data communication is possible. However, depending on the distance between the first device and the second device, there may be no amplitude difference component between modulation and non-modulation of the RF signal (Radio Frequency) received by the first device, so that data cannot be received. . This is called a null point (Communication Hole), and it is known that a communication error occurs due to the null point (see, for example, Patent Document 1).

JP 2003-36418 A

  The inventor of the present application has studied an amplitude demodulation circuit using an IQ detection method, which is a method of detecting a received RF signal using two detection clocks each having a phase difference of 90 degrees.

  3 and 4 (A) and 4 (B) show an IQ detection operation concept when the phase difference between the input and the clock is changed by 0 to 180 degrees. FIG. 3 is a waveform diagram showing the relationship between the multiplication result of the input signal and the clock signal and the detection efficiency (rectangular wave input example). FIG. 4A is a vector diagram of IQ detection operation, and FIG. 4B is an explanatory diagram of the relationship between detection efficiency and phase (SIN wave input).

  In the IQ detection method, the detection gain differs depending on the phase relationship between the phase of the input RF signal and the detection clock. If there is only one channel, the maximum gain is obtained with a phase difference of 0 degrees and 180 degrees, and the phase difference of 90 degrees and 270 degrees is not obtained. Gain is lowest (detection impossible). The total detection gain of the two IQ channels is minimum for a sine (SIN) wave, and is 70% of the maximum gain = −3 dB (corresponding to a 45-degree phase difference).

  Even in the case of a simple RF signal change in the amplitude direction with no phase change, the IQ detection method assumes that the detection efficiency can handle either IQ detection output as output compared to envelope detection, at least. It falls to 3dB. When IQ detection is realized by a multiplication circuit, the amplitude of the RF signal varies depending on the position of the card, making it difficult to design with a low voltage operation and ensuring the dynamic range of the multiplication circuit. When performing combined detection of amplitude and phase with the IQ detection method, a null point may occur because of the combined detection, and the method of combining cannot be determined uniquely. This corresponds to the case where the detection efficiency of either the I system or the Q system is 0 in FIG. IQ detection further reduces the detection efficiency of an RF signal having a waveform that is smaller than that of SIN. This corresponds to the rectangular wave in FIG. 3, and the detection efficiency is 50% at the maximum.

  An object of the present invention is to provide a technique for eliminating a communication error caused by a null point in wireless communication.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A representative one of the inventions disclosed in the present application will be briefly described as follows.

  That is, an analog unit that processes the received RF signal, a waveform shaping unit that shapes the output signal of the analog unit, and a digital unit that digitally processes the output signal of the waveform shaping unit are provided. The analog unit is provided with an amplitude detection circuit for amplitude detection of the RF signal and a phase detection circuit for phase detection of the RF signal. The digital unit is provided with an output circuit for selectively transmitting the detection result of the amplitude detection circuit and the detection result of the phase detection circuit to a subsequent circuit according to the reception state of the RF signal. Thereby, a null point in wireless communication is avoided.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to eliminate a communication error due to a null point in wireless communication.

1. Representative Embodiment First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A radio communication system according to a representative embodiment of the present invention includes an analog unit (11) that processes a received RF signal, and a waveform shaping unit (for shaping the output signal of the analog unit) 16) and a digital unit (12) for digitally processing the output signal of the waveform shaping unit. The analog unit includes an amplitude detection circuit (17) for detecting the amplitude of the RF signal and a phase detection circuit (18) for detecting the phase of the RF signal. The digital unit includes an output circuit (52) for selectively transmitting the detection result of the amplitude detection circuit and the detection result of the phase detection circuit to a subsequent circuit according to the reception state of the RF signal. .

  [2] Another wireless communication system according to a typical embodiment of the present invention includes an analog unit (11) that processes a received RF signal and a waveform that performs waveform shaping of an output signal of the analog unit. It includes a shaping unit (16) and a digital unit (12) that digitally processes the output signal of the waveform shaping unit, and enables packet communication performed by dividing data into a plurality of packets. At this time, the analog unit includes an amplitude detection circuit (17) for detecting the amplitude of the RF signal and a phase detection circuit (18) for detecting the phase of the RF signal. The waveform shaping unit includes a first waveform shaping unit (AD1) that shapes the output signal of the amplitude detection circuit, and a second waveform shaping unit (AD2) that shapes the output signal of the phase detection circuit. The digital unit includes a first decoder (DEC1) for decoding the output of the first waveform shaping unit, a second decoder (DEC2) for decoding the output of the second waveform shaping unit, and when the RF signal is not modulated. And an output circuit (52) for selectively transmitting the output of the first decoder and the output of the second decoder to a subsequent circuit in accordance with the amplitude difference between the first and the second modulation.

  [3] One packet in the packet communication includes a preamble, a sync code, and subsequent data. The digital unit includes a first preamble detection circuit (PD1) that detects the preamble from the output signal of the first decoder, and a first sync code detection circuit (SD1) that detects the sync code from the output signal of the first decoder. ). Further, the digital unit includes a second preamble detection circuit (PD2) for detecting the preamble from the output signal of the second decoder, and a second sync code detection circuit (for detecting the sync code from the output signal of the second decoder). SD2), a determination circuit (51) capable of controlling the selection operation of the output circuit based on the detection result of the first and second preamble detection circuits and the detection result of the first and second sync code detection circuits. including.

  [4] The amplitude detection circuit can be configured to perform envelope detection after nonlinearly amplifying the RF signal with a nonlinear amplifier having a peak hold function.

  [5] The phase detection circuit may be configured to detect a phase variation by shaping the RF signal and then comparing the phase with a reference clock signal.

  [6] In the determination circuit, determination of a preamble or sync code for the output of the first decoder, and determination of a preamble or sync code for the output of the second decoder are delayed with respect to the determination. . When it is determined that the preamble or the sync code at the output of the first decoder is good, the output of the first decoder is selectively transmitted to the subsequent circuit by the output circuit. In addition, when the preamble or the sync code determination result at the output of the first decoder is not good and the preamble or the sync code at the output of the second decoder is determined to be good, the output circuit The output of the second decoder is selectively transmitted to the subsequent circuit.

  [7] The digital unit is a delay circuit (DLY1) for delaying the determination of the preamble or the sync code at the output of the second decoder rather than the determination of the preamble or the sync code at the output of the first decoder. Can be included. At this time, the delay time in the delay circuit can be set to one packet or shorter.

2. DESCRIPTION OF EMBODIMENT <Embodiment 1>
Next, the embodiment will be described in more detail.

  FIG. 1 shows a non-contact IC card system (sometimes referred to as a non-contact IC card microcomputer or an IC card microcontroller) as an example of a wireless communication system according to the present invention. The non-contact IC card system shown in FIG. 1 includes a reader / writer 100 and a non-contact IC card 200. The reader / writer 100 enables reading / writing of the non-contact IC card 200, and is not particularly limited, but includes a loop antenna 10, an analog unit 11, a digital unit 12, a data detection unit 13, and a waveform shaping circuit 16. Wireless communication with the non-contact IC card 200 is enabled. In this wireless communication, packet communication is performed by dividing data into a plurality of packets. One packet includes a preamble (PREAMBLE), a sync (SYNC) code, and subsequent data. The preamble is a kind of data provided for measuring transmission / reception timing in packet communication. The preamble is all [00h] in hexadecimal code. The sync code is a 2-byte code following the preamble. The sync code (SYNC) is used as a timing reference to enable data detection after the sync code (SYNC). Data following the sync code includes data for controlling communication between the reader / writer 100 and the IC card 200, user data, and an error check code.

  The analog unit 11 includes a transmission circuit 11 that transmits an RF signal via the loop antenna 10 and a reception circuit 14 that receives the RF signal via the loop antenna 10. The reception circuit 14 includes an amplitude detection circuit 17 that performs amplitude detection of the reception signal and a phase detection circuit 18 that performs phase detection of the reception signal. The detection result in the amplitude detection circuit 17 and the detection result in the phase detection circuit 18 are converted into a digital signal by the waveform shaping circuit 16 and then transmitted to the digital unit 12, where the data detection unit 13 processes the digital signal there. To detect data.

  Although not particularly limited, the analog unit 11, the digital unit 12, the data detection unit 13, and the waveform shaping circuit 16 of the reader / writer 100 are formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. Is done. Further, although not shown in the figure, the semiconductor integrated circuit formed on the semiconductor substrate can be connected to another semiconductor integrated circuit and can input / output data signals processed by the digital unit 12. .

  The reader / writer 100 generates a carrier signal (carrier wave) having a predetermined frequency and emits the carrier signal from the loop antenna 10 as a radio wave. At this time, in the non-contact IC card 200, when the own loop antenna 201 is within a range that causes electromagnetic induction with the loop antenna 10 of the reader / writer 100, a carrier signal is induced in the loop antenna 201. This induced voltage is used as an operation power source for the circuit in the non-contact IC card 200. In addition, the carrier is modulated by data to be transmitted in the non-contact IC card 200 and is received by the reader / writer 100 to enable data communication. However, depending on the distance between the reader / writer 100 and the non-contact IC card 200, modulation / non-modulation amplitude difference components of the reception signal (RF signal) of the reader / writer 100 may be lost, and data cannot be received. It is a so-called null point (Communication Hole), and a communication error occurs due to this.

  FIG. 2 shows a null point and an RF signal waveform other than the null point.

  As shown in FIG. 2, at the null point, a phase difference between non-modulation and modulation occurs instead of an amplitude difference between non-modulation and modulation. If this phase difference is detected and data detection is performed using the detection result, a communication error at the null point is avoided even though there is no amplitude difference component between modulation and non-modulation of the RF signal. can do. Therefore, in the configuration shown in FIG. 1, a phase detection circuit 18 is provided in the reception circuit 14 in addition to the amplitude detection circuit 17, and the detection result of the amplitude detection circuit 17 and the phase detection circuit according to the reception status of the RF signal. By selectively transmitting the 18 detection results to the subsequent circuit, a communication error due to the null point is eliminated.

  FIG. 5 shows a configuration example of a main part of the reader / writer 100 shown in FIG.

  The amplitude detection circuit (DET1) 17 includes a peak hold circuit PH1 that holds a peak of a signal input via the input terminal IN1, a non-linear amplifier NLA1 that amplifies the output signal of the peak hold circuit PH1, and amplitude shift keying ( ASK (amplitude shift keying) includes an envelope detection circuit EDET1 that enables envelope detection. The phase detection circuit (DET2) 18 compares the waveform shaping circuit MOD1 for shaping the waveform of the signal input via the input terminal IN1, and compares the output signal of the waveform shaping circuit MOD1 with the reference clock CLK1 to obtain the phase difference. A multiplication circuit MIX1 for detection is included.

  The waveform shaping circuit 16 includes a waveform shaping circuit AD1 and a second waveform shaping circuit AD2. The waveform shaping circuit AD1 performs waveform shaping by converting the output signal of the envelope detection circuit EDET1 into a digital signal. The waveform shaping circuit AD2 performs waveform shaping by converting the output signal of the output signal DOUT2 of the multiplication circuit MIX1 into a digital signal. The output (DOUT1) of the waveform shaping circuit AD1 and the output (DOUT2) of the waveform shaping circuit AD2 are taken into the digital circuit 12.

  The digital circuit 12 includes a first decoder DEC1, a second decoder DEC2, a delay circuit DLY1, preamble detection circuits PD1 and PD2, sync code detection circuits SD1 and SD2, a determination circuit 51, and an output circuit (Y1) 52. The first decoder DEC1 decodes the output signal DOUT1 of the waveform shaping circuit AD1. The delay circuit DLY1 delays the output signal DOUT2 of the waveform shaping circuit AD2 by a predetermined time. The second decoder DEC2 decodes the output signal of the delay circuit DLY1. The rumble preamble detection circuit PD1 detects the preamble from the output signal of the first decoding circuit DEC1. The rumble preamble detection circuit PD2 detects the preamble from the output signal of the first decoding circuit DEC1. The sync code detection circuit SD1 detects a sync code from the output signal of the first decoding circuit DEC1. The sync code detection circuit SD2 detects a sync code from the output signal of the second decoding circuit DEC2. The determination circuit 51 controls the selection operation of the output circuit 52 based on the detection results of the preamble detection circuits PD1 and PD2 and the sync code detection circuits SD1 and SD2.

  Preamble or sync code determination for the output of the first decoder, and preamble or sync code determination for the output of the second decoder are performed with a time lag behind the determination, and the output of the first decoder If it is determined that the preamble or the sync code is good, the output of the first decoder is selectively transmitted to the subsequent circuit by the output circuit. In addition, when the preamble or the sync code determination result at the output of the first decoder is not good and the preamble or the sync code at the output of the second decoder is determined to be good, the output circuit The output of the second decoder is selectively transmitted to the subsequent circuit.

  FIG. 6 shows an operation example of the reader / writer 100 shown in FIGS. 1 and 5.

  The operation state of the reader / writer 100 includes a first state to a fourth state. In the first state, the preamble and sync code can be detected for both the amplitude modulation component and the phase modulation component (near the null point). In the second state, a preamble or sync code cannot be detected in the amplitude modulation component, and a preamble or sync code can be detected in the phase modulation component (null point). In the third state, the preamble and sync code can be detected for both the amplitude modulation component and the phase modulation component (near the null point). In the fourth state, a preamble and sync code can be detected in the amplitude modulation component, and a preamble and sync code cannot be detected in the phase modulation component (other than the null point).

  The signals obtained by detecting the amplitude modulation component from the surface portion of the input terminal IN1 and digitally converting the phase modulation component from the center portion are DOUT1 and DOUT2, respectively. In DOUT1, a preamble SPA1 and a sync code SSC1 are present at the head of each packet, and in DOUT2, a preamble SPA2 and a sync code SSC2 are present at the head. A delay time for one packet is set in the delay circuit DLY1. For this reason, the output data of DOUT2 is delayed by one packet compared to the output data of DOUT1. In the second state, a preamble or sync code cannot be detected in the amplitude modulation component, but a preamble or sync code can be detected in the phase modulation component, which is used for data detection in the data detection circuit (Z1) 13. That is, even if SPA1 or SSC1 of DOUT1 is not logically detected, SPA2 and SSC2 of delayed DOUT2 are detected and selected by the output circuit 52, so that the data output from the output circuit Y1 always exists. Will do. Thereby, the null point in radio | wireless communication can be avoided.

  FIG. 7 shows an example in which the delay time in the delay circuit DLY1 is changed. That is, in the operation example shown in FIG. 6, the delay time for one packet is set in the delay circuit DLY1, whereas in the operation example shown in FIG. 7, the delay time in the delay circuit DLY1 is one packet. Is shorter. Specifically, the total time of the preamble period, the sync code period, and the time required for decoding by the first decoder DEC1 or the second decoder DEC2 is set in the delay circuit DLY1. Thus, even when the time set in the delay circuit DLY1 is shorter than one packet, the output circuit 52 can switch between the output of the first decoder DEC1 and the output of the second decoder DEC2, and the output circuit Y1. Since the output data from always exists, a null point in wireless communication can be avoided.

  According to the above example, the following effects can be obtained.

  (1) Even if SPA1 or SSC1 of DOUT1 is not logically detected, SPA2 and SSC2 of delayed DOUT2 are detected and selected by the output circuit 52, so that the data output from the output circuit Y1 is always Will exist. Thereby, the null point in radio | wireless communication can be avoided and the communication error resulting from a null point in radio | wireless communication can be excluded.

  (2) Since the null point in the wireless communication can be avoided by the effect of the above (1), the detection performance of the receiving circuit is improved, and the communication reliability is improved in the NFC wireless communication system. Can do.

<Embodiment 2>
FIG. 8 shows another configuration example of the main part of the reader / writer 100 shown in FIG.

  The reader / writer 100 shown in FIG. 8 is greatly different from that shown in FIG. 5 in that the first band-pass filter BPF1, the first amplifier circuit AMP1, and the first Schmitt circuit SHMT1 are provided on the output side of the amplitude detection circuit 17. Similarly, the second band-pass filter BPF2, the second amplifier circuit AMP2, and the second Schmitt circuit SHMT2 are provided on the output side of the phase detection circuit 18. The output signal of the amplitude detection circuit 17 is transmitted to the first amplifier circuit AMP1 through the first bandpass filter BPF1, amplified there, and then transmitted to the first Schmitt circuit SHMT1, where it is converted into a binary signal. The signal is transmitted to the first decoder DEC1. Similarly, the output signal of the phase detection circuit 18 is transmitted to the second amplifier circuit AMP2 via the second bandpass filter BPF2, amplified there, and then transmitted to the second Schmitt circuit SHMT2, where it is converted into a binary signal. Then, it is transmitted to the second decoder DEC2. According to such a configuration, the communication band can be selected by the first band filter BPF1 and the second band filter BPF2, and the first Schmitt circuit SHMT1 and the second amplifier circuit AMP2 can be selected. Since the signal can be amplified to a level that matches the threshold value in the second Schmitt circuit SHMT2, the waveform quality of DOUT1 and DOUT2 can be improved.

<Embodiment 3>
FIG. 9 shows another configuration example of the main part of the reader / writer 100 shown in FIG.

  The reader / writer 100 shown in FIG. 9 is largely different from that shown in FIG. 5 in that the delay circuit DLY1 is arranged at the subsequent stage of the second decoder DEC2. According to such a configuration, since the signal after being decoded by the second decoder DEC2 is delayed by the delay circuit DLY1, there is an advantage that the delay in the delay circuit DLY1 is hardly affected by the analog unit 11.

<Embodiment 4>
FIG. 10 shows another configuration example of the main part of the reader / writer 100 shown in FIG.

  The reader / writer 100 shown in FIG. 10 is greatly different from that shown in FIG. 5 in the configuration of the amplitude detection circuit 17. In the reader / writer 100 shown in FIG. 10, the amplitude detection circuit 17 corresponds to a two-phase input, and two sets of peak hold circuits and nonlinear amplifiers are provided. In addition to the input signal from the input terminal IN1, a signal whose logic is inverted from that of the input signal from the input terminal IN1 is taken in from the input terminal IN1_B. An input signal from the input terminal IN1 is input to the first peak hold circuit PH1, amplified by the nonlinear amplifier NLA1, and then input to the envelope detection circuit EDET1. An input signal from the input terminal IN2 is input to the second peak hold circuit PH2, amplified by the nonlinear amplifier NLA2, and then input to the envelope detection circuit EDET1. According to such a configuration, because of the two-phase input, there is an advantage that the amplitude detection efficiency is increased as compared with the case shown in FIG.

<Embodiment 5>
FIG. 11 shows another configuration example of the main part of the reader / writer 100 shown in FIG.

  The reader / writer 100 shown in FIG. 11 is greatly different from that shown in FIG. 5 in that the phase detection circuit 18 is provided with a second waveform shaping circuit MOD2 for shaping the waveform of the reference clock signal CLK1. is there. According to this configuration, since the reference clock signal CLK is waveform-shaped by the second waveform shaping circuit MOD2 and then transmitted to the multiplication circuit MIX1, even when the reference clock signal CLK1 transmitted to the phase detection circuit 18 is dull. High phase detection performance can be demonstrated.

<Embodiment 6>
FIG. 11 shows another configuration example of the main part of the reader / writer 100 shown in FIG.

  The reader / writer 100 shown in FIG. 11 is greatly different from that shown in FIG. 5 in that the delay circuit DLY1 is arranged at the subsequent stage of the waveform shaping circuit AD1. According to such a configuration, the output signal of the waveform shaping circuit AD1 is delayed by a predetermined time by the delay circuit DLY1, and then transmitted to the first decoder DEC1. Even if it does in this way, the effect similar to the case of the said embodiment is exhibited.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  In the above description, the case where the invention made mainly by the present inventor is applied to the non-contact IC card system which is the field of use as the background has been described. However, the present invention is not limited thereto, and the wireless communication system is not limited thereto. Can be widely applied to.

1 is a block diagram illustrating a configuration example of a contactless IC card system as an example of a wireless communication system according to the present invention. It is a wave form diagram which shows RF signals other than a null point and a null point. It is a waveform diagram of the IQ detection operation concept when the phase difference between the input and the clock is changed by 0 to 180 degrees. It is explanatory drawing of IQ detection operation | movement concept at the time of changing the phase difference of an input and a clock 0 to 180 degree | times. FIG. 2 is a block diagram illustrating a configuration example of a main part in the non-contact IC card system illustrated in FIG. 1. It is operation | movement explanatory drawing of the reader / writer in the said non-contact IC card system. It is another operation example explanatory diagram of the reader / writer in the non-contact IC card system. FIG. 5 is a block diagram illustrating another configuration example of a main part in the non-contact IC card system illustrated in FIG. 1. FIG. 5 is a block diagram illustrating another configuration example of a main part in the non-contact IC card system illustrated in FIG. 1. FIG. 5 is a block diagram illustrating another configuration example of a main part in the non-contact IC card system illustrated in FIG. 1. FIG. 5 is a block diagram illustrating another configuration example of a main part in the non-contact IC card system illustrated in FIG. 1. FIG. 5 is a block diagram illustrating another configuration example of a main part in the non-contact IC card system illustrated in FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Loop antenna 11 Analog part 12 Digital part 13 Data detection part 14 Reception circuit 15 Transmission circuit 16 Waveform shaping circuit 17 Amplitude detection circuit 18 Phase detection circuit 51 Judgment circuit 52 Output circuit 100 Reader / writer 200 Non-contact IC card

Claims (8)

An analog unit for processing the received RF signal;
A waveform shaping unit for shaping the waveform of the output signal of the analog unit;
A wireless communication system including a digital unit that digitally processes an output signal of the waveform shaping unit,
The analog unit includes an amplitude detection circuit for amplitude detection of the RF signal, and a phase detection circuit for phase detection of the RF signal,
The digital unit includes an output circuit for selectively transmitting the detection result of the amplitude detection circuit and the detection result of the phase detection circuit to a subsequent circuit according to the reception state of the RF signal. A characteristic wireless communication system. An analog unit for processing the received RF signal;
A waveform shaping unit for shaping the waveform of the output signal of the analog unit;
A wireless communication system that enables packet communication performed by dividing data into a plurality of packets, including a digital unit that digitally processes an output signal of the waveform shaping unit,
The analog unit includes an amplitude detection circuit for amplitude detection of the RF signal, and a phase detection circuit for phase detection of the RF signal,
The waveform shaping unit includes: a first waveform shaping unit that shapes the output signal of the amplitude detection circuit;
A second waveform shaping section for shaping the output signal of the phase detection circuit,
The digital unit includes a first decoder for decoding the output of the first waveform shaping unit;
A second decoder for decoding the output of the second waveform shaping section;
An output circuit for selectively transmitting the output of the first decoder and the output of the second decoder to a subsequent circuit according to an amplitude difference between the non-modulated and modulated RF signals. A wireless communication system. One packet in the packet communication includes a preamble, a sync code, and subsequent data,
The digital unit includes a first preamble detection circuit that detects the preamble from an output signal of the first decoder;
A first sync code detection circuit for detecting the sync code from the output signal of the first decoder;
A second preamble detection circuit for detecting the preamble from an output signal of the second decoder;
A second sync code detection circuit for detecting the sync code from the output signal of the second decoder;
And a determination circuit capable of controlling a selection operation of the output circuit based on a detection result of the first and second preamble detection circuits and a detection result of the first and second sync code detection circuits. Wireless communication system.   3. The radio communication system according to claim 2, wherein the amplitude detection circuit performs envelope detection after nonlinearly amplifying the RF signal by a nonlinear amplifier having a peak hold function.   The wireless communication system according to claim 2, wherein the phase detection circuit detects a phase fluctuation by comparing the phase with a reference clock signal after shaping the waveform of the RF signal. In the determination circuit, a preamble or sync code is determined for the output of the first decoder, and a preamble or sync code is determined for the output of the second decoder with a time delay after the determination,
When it is determined that the preamble or the sync code at the output of the first decoder is good, the output of the first decoder is selectively transmitted to the subsequent circuit by the output circuit,
If the determination result of the preamble or the sync code at the output of the first decoder is not good and the preamble or the sync code at the output of the second decoder is determined to be good, the output circuit causes the 4. The wireless communication system according to claim 3, wherein the output of the two decoders is selectively transmitted to a subsequent circuit. The digital unit includes a delay circuit for delaying the determination of the preamble or the sync code in the output of the second decoder from the determination of the preamble or the sync code in the output of the first decoder;
7. The wireless communication system according to claim 6, wherein the delay time in the delay circuit is set to one packet or shorter.   The wireless communication system according to any one of claims 1 to 6, wherein the analog unit, the waveform shaping unit, and the digital unit are formed on a single semiconductor substrate.

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