JPH09200099A - Write/read control unit for identification system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the same data from being written in plural data carriers by detecting that plural data carriers are in existence in a communication area. SOLUTION: A diameter of a transmission coil L1 is selected smaller than a diameter of a reception coil L2 and arranged behind the reception coil. Furthermore, a Manchester code is used for a communication signal and an inverted two-consecutive error detection circuit 24 detects an inverted two-consecutive error being consecutive logic levels in the same period. Thus, the presence of plural data carriers in the communication area is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write / read control unit used in an identification system, and more particularly to a write / read control unit having a detection function for detecting the presence of a plurality of data carriers in a communication area. .

[0002]

2. Description of the Related Art Conventionally, in order to identify parts and products on an assembly and transportation line and to mechanize transportation and entrance / exit at a gate of a ski resort, an automatic ticket gate, etc., a system for identifying a product and a passing person is required. Becomes Therefore, as shown in Japanese Patent Application Laid-Open No. 1-151831, a memory unit (data carrier) having a memory for an object to be identified is provided, and necessary information is written in such a memory by external data transmission. An identification system has been proposed in which the information is read as needed.

[0003] Such a conventional identification system includes a writing / writing system.
It is composed of a read control unit and a data carrier (not shown). The writing / reading control unit 1 comprises an ID controller and a read / write head as shown in FIG. The write / read control unit 1 intermittently oscillates at a constant frequency and transmits a signal to the data carrier side. When receiving data, the write / read control unit 1 sends out a signal having a constant duty ratio to reverberate through a resonance circuit in the data carrier. Control. In the read / write head, a signal is received by determining the presence or absence of the reverberation using a resonance circuit.

As shown in FIG. 6, the write / read control unit 1 has a transmission processing circuit 11 for transmitting a signal from the host controller 2. Here, a Manchester code is used as the transmission signal, and the transmission data is Manchester encoded and used as an oscillation control signal. The oscillation circuit 12 interrupts oscillation based on this control signal. The oscillation output of the oscillation circuit 12 is transmitted to the transmission coil L1. Also, the receiving coil L2 and the capacitor C are connected to the receiving circuit side, and the receiving circuit 1
3, The detection circuit 15 is connected via the amplifier 14. The receiving circuit 13 outputs a signal at a predetermined timing of the resonance circuit according to the gate signal. The detection circuit 15 detects the reception output to obtain an envelope signal, and its output is connected to the sample hold circuits (S / H circuits) 16 and 17. The sample and hold circuits 16 and 17 are connected in cascade and each hold an input according to a timing signal, and its output is given to a comparator 18. The comparator 18 compares these outputs to compare the levels at the timings of the first half and the second half of each cycle, and generates demodulated data based on the level difference. Since the signal from the data carrier is also Manchester encoded,
As will be described later, "1" is "LH" and "0" within the same surroundings.
Is composed of "HL". Therefore, data can be demodulated based on these differences. This signal is converted into an NRZ signal by the reception signal processing circuit 19 and transmitted to the host controller 2. The timing circuit 20 supplies a timing signal to each part.

FIG. 7 is a time chart showing the operation at the time of receiving a signal, and (a) to (j) show the waveforms of the respective parts a to j in FIG. FIG. 7A shows a signal obtained in the receiving coil L2, and the reverberation level differs depending on the signal from the data carrier. The reverberation part is extracted from the receiving circuit 13 as shown in FIG. 7 (d) by using the timing signals of FIGS. 7 (b) and 7 (c). Then, it is detected by the detection circuit 15 and its level is discriminated at a predetermined timing (FIGS. 7E to 7G). Then, a predetermined level is held. Then, by comparing the level differences at different timings, the signal can be demodulated as shown in FIG. 7 (j).

FIG. 8 is a diagram showing the transmission coil L1 and the reception coil L2 of the write / read control unit and their communication areas. In the conventional write / read control unit, the diameter of the transmission coil L1 is larger than that of the reception coil L2 as shown, and the reception coil L2 is coaxially arranged inside the transmission coil L1.

[0007]

However, in such a conventional identification system, the power is transmitted from the transmission coil L1 to the data carrier, and the area AT capable of transmitting the power and data and the reception coil L2 are used to transmit the power from the data carrier. The area AR that can receive the reply data is different. Therefore, as shown in FIG. 8A, if the data carrier 4 exists only at the position where only power and data can be transmitted and cannot be received, in addition to the data carrier 3 at the normal position, the data carrier 3 at that position can also be transmitted. However, the same content may be written in the data carrier 4 of FIG.

Further, as shown in FIG. 8B, two data carriers 3 and 5 are provided in an area (hereinafter referred to as a communication area) included in both the transmission area AT and the reception area AR capable of transmitting power and data. Even if there is, malfunction may occur. That is, when the data carriers 3 and 5 are individually located, the outputs obtained from the detection circuit 15 are shown in FIG.
It shall be shown in (a) and (b). In this case, since the data carrier 5 is separated from the transmission / reception coils L1 and L2,
The level H ₂ is H when there is reverberation corresponding to FIG.
_Lower than ₁ . Therefore two data carriers 3, 5
If both are present in the areas AT and AR at the same time, the output of the detection circuit 15 is as shown in FIG. 9 (c). Therefore, when this signal is sampled and held by the two sampling and holding circuits 16 and 17 and compared by the comparator 18, the comparison voltage Vc based on the threshold value of the comparator 18 is obtained.
Is smaller, the signal is demodulated as shown in FIG. That is, there is a drawback that only the signal from the data carrier 3 having a high level close to the receiving coil L2 is received and the existence of the other data carrier 5 is ignored.

The present invention has been made in view of the problems of the conventional write / read control unit, and outputs an error signal when a plurality of data carriers are located in the transmission / reception area, and also makes a copy. The purpose is to prevent malfunction due to.

[0010]

SUMMARY OF THE INVENTION The present invention comprises a transmitter coil,
A transmitter circuit for driving the transmitter coil, and a receiver coil,
Demodulation means for demodulating a Manchester-encoded reception signal based on the reception level obtained from the reception coil;
In the writing / reading control unit of the identification system for transmitting a signal to the data carrier and receiving the signal from the data carrier, the diameter of the transmitting coil is made smaller than the diameter of the receiving coil, By arranging it in the back, the transmission area is included in the reception area, and the demodulation means is the same as the demodulation circuit that discriminates and demodulates the reverberation level with a predetermined threshold at the same timing in the first half and the second half of the same period. And an inversion double error detection circuit that detects an inversion double error that becomes a logic level.

According to the present invention having such features,
Since the transmission area is included in the reception area, it is possible to eliminate an area that is included only in the transmission area and in which data is erroneously written. Further, since the Manchester code is used for data transmission, the same logic level does not occur in the first half and the second half timing within the same cycle. Therefore, when such a situation occurs, it can be recognized that a plurality of data carriers exist, and it can be detected that a plurality of data carriers exist in the communication area.

[0012]

1 is a block diagram showing a main part of a write / read control unit according to an embodiment of the present invention. In this figure, the same parts as those of the above-described conventional example are denoted by the same reference numerals, and detailed description is omitted. Also in this embodiment, the circuit configuration on the transmission side is the same, the oscillation circuit 12 is connected to the transmission processing circuit 11, and the oscillation coil 12 drives the transmission coil L1. In addition, the receiving circuit is also the receiving coil L2.
The receiving circuit 13 is connected to the resonance circuit formed by the capacitor C and the output thereof is given to the sample hold circuit 21 through the amplifier 14 and the detection circuit 15. The output of the sample and hold circuit 21 is the first and second comparators 22,
23 is input. The comparators 22 and 23 discriminate the output of the sample hold circuit 21 by the constant threshold values Vref1 and Vref2, respectively. The output of the comparator 22 is the original Manchester code N by the reception signal processing circuit 19.
It is converted into an RZ signal. Further, the comparator 23 has a threshold value Vref2 lower than the threshold value Vref1 of the comparator 22, discriminates the output of the sample hold circuit 21, and the output thereof is input to the inversion double error detection circuit 24. In the case of the Manchester code, the inversion double error detection circuit 24 does not have the same logic level in the first half and the second half timing in the same cycle. Therefore, when this is continuously output, there are a plurality of data carriers in the communication area. It is a circuit for discriminating that it outputs an error signal. This error signal is transmitted to the error display circuit 25 and simultaneously transmitted to the host controller 2.

FIG. 2 is a circuit diagram showing the configuration and connection of the comparators 22 and 23, the received signal processing circuit 19 and the inverted double error detection circuit 24. In this figure, the comparator 2
The output terminal of 2 is connected to the reception signal processing circuit 19. The reception signal processing circuit 19 receives the transmission / reception switching signal TXR from the host controller 2, and when the signal is at the L level, the reception operation is performed. The reception signal processing circuit 19 converts the input signal from the Manchester code into the NRZ signal XLDO and outputs it to the host controller 2 and, at the same time, to the inverted double error detection circuit 24. Further, a clock CLK earlier than this is simultaneously given to the inverted double error detection circuit 24. The inversion double error detection circuit 24 has a comparator 23.
Is input. This input is input to the D-type flip-flop 32 via the inverter 31, and the Q1
The output is input to the D-type flip-flop 33. The clock signal XCLK from the received signal processing circuit 19 is input to the flip-flops 32 and 33 via the inverter 34 or directly to the clock input terminal CK. Inverter 3
Reference numeral 5 denotes a reception signal processing circuit 19 which becomes L level during reception.
Of the D-type flip-flops 32 and 33 are input as clear signals of the D-type flip-flops 32 and 33.
The D-type flip-flop 33 holds the input at the timing of the clock and outputs the output from the exclusive OR (EOR) circuit 3
6 is output. The EOR circuit 36 detects an inverted double error by detecting the exclusive OR of the Q2 output and the demodulation signal XLDO output from the reception signal processing circuit 19. The output of the EOR circuit 36 is the AND circuit 37.
Is input to The clock signal XCLK is input to the other input terminal of the AND circuit 37, and when an error is detected, the error signal is output at a timing of 1 clock. This output is displayed on the display 42 via the monostable multivibrator (MM) 41 of the error display circuit 25.

Next, the shapes and arrangements of the transmitting coil L1 and the receiving coil L2 will be described with reference to FIG. In the present invention, the diameter of the transmission coil L1 is made smaller than that of the reception coil L2 as shown in the figure. The transmission coil L1 and the reception coil L2 are coaxial, and the transmission coil L1 is arranged inside from the surface S of the read / write head. By doing so, as shown in FIG. 3A, the transmission area AT in which electric power is transmitted from the transmission coil L1 and the signal can be transmitted is inside the reception area AR of the reception coil L2, and the transmission area AT can be seen in the reception area AR. It can be lost.

Although there are cases where a plurality of data carriers hold data having the same content, the data carrier has areas each having a different content, and each time the data is read, the data is read at the same time. I will put it out.
In this way, the data read from the plurality of data carriers contain different data. Therefore, when this data is read, a double error occurs as described later,
It can be determined that a plurality of data carriers are in the communication area.

Next, the operation of this embodiment will be described with reference to FIGS.
This will be described with reference to the time chart of FIG. As shown in FIG. 3B, when there are two data carriers 6 and 7 in the communication area where the transmission / reception areas AT and AR overlap, the reception level from the closer data carrier 6 is as shown in FIG.
As shown in FIG. 4A, the level is high, and as shown in FIG. 4B, the reception level from the distant data carrier 7 is low. Therefore, if there are two data carriers 6 and 7, FIG.
A signal obtained by superimposing this signal is obtained from the detection circuit 15 as shown in FIG. In this figure, the thresholds Vref1 and Vref2 of the two comparators 22 and 23 are shown at the same time.
(D), the signal shown in FIG. 4 (e) is obtained from the comparator 23.

5 (a) to 5 (j) are waveform diagrams showing the waveforms of the portions indicated by a to j in FIG. “1011” shown in the upper part of FIG. 5A is the NR transmitted from the data carrier.
FIG. 5 (a) shows the Z signal, and FIG.
4 shows the output that is input to the inverter 4 and inverted by the inverter 31. The hatched portion shown in FIG. 5A is a portion where an inversion double error occurs, and FIG. 5B shows an output waveform of the comparator 22. Then, by the inverted signal of the clock from the reception signal processing circuit 19 shown in FIG. 5C, the value is held by the D flip-flop 32 at the rising edge of the clock as shown in FIG. 5D. By holding this by the clock signal shown in FIG. 5 (e), the output shown in FIG. 5 (f) is obtained from the flip-flop 33. By taking the exclusive OR of this signal and the output of the reception signal processing circuit 19 shown in FIG.
The output is obtained as shown in (h). If there is such an output mismatch, the output of the EOR circuit 36 detects an inverted double error. Therefore, as shown in FIG. 5I, an error signal synchronized with the clock signal is obtained from the AND circuit 37, and the error state can be displayed based on this. If there are two data carriers in the transmittable / receivable area as described above, the state can be detected, so that communication can be reliably performed without writing erroneous data in a plurality of data carriers at the same time.

Therefore, when the identification system is applied to a gate such as a ski resort or an automatic ticket gate, erroneous data or the like is not written into a plurality of data carriers at the same time.
Reliability can be improved.

[0019]

As described in detail above, according to the present invention, since the diameter of the transmission coil is reduced and the transmission coil is provided behind the reception coil, the transmission area does not extend beyond the reception area. Therefore, it is possible to eliminate the area where the data is copied in the transmission area instead of the reception area. Further, even if a plurality of data carriers exist in the transmission / reception area, the presence of a plurality of data carriers can be detected. Therefore, erroneous data is not written to other than the data carrier to be the communication partner, and the effect of improving the communication accuracy can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a write / read control unit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing configurations of an inversion double error detection circuit and peripheral circuits thereof according to the present embodiment.

FIG. 3 is a diagram showing an arrangement of a transmission coil and a reception coil and a communication area according to the present embodiment.

FIG. 4 is a waveform diagram showing waveforms of respective parts when a plurality of data carriers exist in a communication area.

FIG. 5 is a time chart showing the operation of the inversion double error detection circuit of this embodiment.

FIG. 6 is a block diagram showing an example of a conventional write / read control unit.

FIG. 7 is a diagram showing an arrangement of transmission / reception coils of a conventional write / read control unit.

FIG. 8 is a diagram showing an arrangement and a communication area of a transmission coil and a reception coil of a conventional write / read control unit.

FIG. 9 is a waveform diagram showing waveforms of respective parts when a plurality of data carriers exist in a communication area of a conventional identification system.

[Explanation of symbols]

 1 Writing / Reading Control Unit 2 Upper Controller 11 Transmission Processing Circuit 12 Oscillation Circuit 13 Reception Circuit 14 Amplifier 15 Detection Circuit 16, 17, 21 Sample Hold Circuit 18, 20, 22, 23 Comparator 19 Reception Signal Processing Circuit 20 Timing Circuit 24 Inversion double error detection circuit 25 Error display circuit 31, 34, 35 Inverter 32, 33 D flip-flop 36 Exclusive OR circuit L1 transmission coil L2 reception coil

Claims (1)

[Claims] 1. A transmission coil, a transmission circuit for driving the transmission coil, a reception coil, and demodulation means for demodulating a Manchester-encoded reception signal based on a reception level obtained from the reception coil.
In the writing / reading control unit of the identification system for transmitting a signal to a data carrier and receiving a signal from the data carrier, the diameter of the transmitting coil is smaller than the diameter of the receiving coil, and The transmission area is included in the reception area by arranging it in the back, and the demodulation means is the same as the demodulation circuit that discriminates and demodulates the reverberation level with a predetermined threshold at the same timing in the first half and the second half of the same cycle. And an inversion double error detection circuit that detects an inversion double error that becomes a logic level, and a writing / reading control unit of an identification system.