JP2006261609A - Garium nitride based light emitting diode and light emitting device using the same - Google Patents

Garium nitride based light emitting diode and light emitting device using the same Download PDF

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JP2006261609A
JP2006261609A JP2005080606A JP2005080606A JP2006261609A JP 2006261609 A JP2006261609 A JP 2006261609A JP 2005080606 A JP2005080606 A JP 2005080606A JP 2005080606 A JP2005080606 A JP 2005080606A JP 2006261609 A JP2006261609 A JP 2006261609A
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JP4956902B2 (en
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Takahide Shiroichi
隆秀 城市
Hiroaki Okagawa
広明 岡川
Tsuyoshi Takano
剛志 高野
Susumu Hiraoka
晋 平岡
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Mitsubishi Cable Industries Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a GaN based LED provided with a structure reflecting the light moving in the opposite direction from a light extracting direction inside an element more efficiently and having improved efficiency of extracting light. <P>SOLUTION: A GaN-based light emitting diode has: a laminate including an n-type GaN-based semiconductor layer 2, a light emitting layer 3 comprising a GaN based semiconductor, and a p-type GaN based semiconductor layer 4 in this order; a semiconductor electrode layer P2a formed on the surface of the p-type GaN based semiconductor layer 4 and comprising the n-type semiconductor transmitting the light generated in the light emitting layer; a metal electrode P2b formed on the surface of the semiconductor electrode layer partially; a transparent insulating film Ins formed on the surface of the semiconductor electrode layer P2a with the metal electrode P2b in-between, and having a refractive index lower than that of the semiconductor electrode layer P2a; and a metallic reflective film R formed on the surface of the transparent insulating film Ins. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、フリップチップ実装して用いるのに適したGaN系発光ダイオードと、フリップチップ実装されたGaN系発光ダイオードを含む発光装置に関する。   The present invention relates to a GaN-based light-emitting diode suitable for flip-chip mounting and a light-emitting device including a GaN-based light-emitting diode mounted on a flip chip.

GaN系発光ダイオード(以下「GaN系LED」ともいう。)は、GaN系半導体からなる発光層を挟んでp型およびn型のGaN系半導体が接合されてなる、pn接合ダイオード構造を有する半導体発光素子であり、発光層を構成するGaN系半導体の組成を選択することによって、赤色〜紫外に至る光を発光させることが可能である。   A GaN-based light emitting diode (hereinafter also referred to as a “GaN-based LED”) is a semiconductor light emitting device having a pn junction diode structure in which p-type and n-type GaN-based semiconductors are joined with a light-emitting layer made of a GaN-based semiconductor interposed therebetween. By selecting the composition of the GaN-based semiconductor that constitutes the light-emitting layer of the device, light ranging from red to ultraviolet can be emitted.

GaN系半導体は、化学式AlInGa1−a−bN(0≦a≦1、0≦b≦1、0≦a+b≦1)で決定される三族窒化物からなる化合物半導体であって、例えば、GaN、InGaN、AlGaN、AlInGaN、AlN、InNなど、任意の組成のものが例示される。また、上記化学式において、3族元素の一部をホウ素(B)、タリウム(Tl)などで置換したもの、また、N(窒素)の一部をリン(P)、ヒ素(As)、アンチモン(Sb)、ビスマス(Bi)などで置換したものも、GaN系半導体に含まれる。 A GaN-based semiconductor is a compound semiconductor made of a group III nitride determined by the chemical formula Al a In b Ga 1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1). For example, those having an arbitrary composition such as GaN, InGaN, AlGaN, AlInGaN, AlN, and InN are exemplified. In the above chemical formula, a part of the group 3 element is substituted with boron (B), thallium (Tl), or the like, and a part of N (nitrogen) is phosphorus (P), arsenic (As), antimony ( Those substituted with Sb) or bismuth (Bi) are also included in the GaN-based semiconductor.

GaN系LEDは、有機金属化合物気相成長(MOVPE)法、ハイドライド気相成長(HVPE)法、分子ビームエピタキシー(MBE)法等の気相成長法を用いて、サファイア等からなる結晶基板上に、n型GaN系半導体層、発光層、p型GaN系半導体層をこの順に含む積層体を、n型GaN系半導体層側から成長し、その後、n型GaN系半導体層に給電するための電極と、p型GaN系半導体層に給電するための電極とを形成することによって、作製することができる。
なお、本明細書では、GaN系半導体層を気相成長法により製造する際に、結晶基板が下側にあり、その上にGaN系半導体層が積み重ねられるものとみなして、この上下の区別を、素子構造の説明においても適用する。また、上下方向(結晶基板やGaN系半導体層の厚み方向でもある。)と直交する方向を、横方向と呼ぶ。また、p型GaN系半導体層を単にp型層とも呼び、n型GaN系半導体層を単にn型層とも呼ぶ。
A GaN-based LED is formed on a crystal substrate made of sapphire or the like by using a vapor phase growth method such as an organic metal compound vapor phase growth (MOVPE) method, a hydride vapor phase growth (HVPE) method, or a molecular beam epitaxy (MBE) method. An electrode for growing a stacked body including an n-type GaN-based semiconductor layer, a light-emitting layer, and a p-type GaN-based semiconductor layer in this order from the n-type GaN-based semiconductor layer side, and then supplying power to the n-type GaN-based semiconductor layer And an electrode for supplying power to the p-type GaN-based semiconductor layer.
In this specification, when the GaN-based semiconductor layer is manufactured by the vapor deposition method, it is assumed that the crystal substrate is on the lower side and the GaN-based semiconductor layer is stacked thereon, and this upper and lower distinction is made. This also applies to the description of the element structure. A direction perpendicular to the vertical direction (also the thickness direction of the crystal substrate or the GaN-based semiconductor layer) is referred to as a horizontal direction. The p-type GaN-based semiconductor layer is also simply referred to as a p-type layer, and the n-type GaN-based semiconductor layer is also simply referred to as an n-type layer.

図10は、特開2004−179347号公報(特許文献1)に開示された、従来のGaN系LEDの構造を示す模式図である。図10(a)は上面図、図10(b)は、図10(a)のX−Y線における断面図である。図10において、11はサファイアからなる結晶基板、12はSiドープGaNコンタクト層とその上に積層されたSiドープAlGaNクラッド層とからなるn型層、13はInGaNからなるMQW(多重量子井戸)構造の発光層、14はMgドープAlGaNクラッド層とその上に積層されたMgドープGaNコンタクト層とからなるp型層、P11はTi(チタン)とAl(アルミニウム)とを積層してなる下部電極、P12aとP12bは上部電極を構成しており、P12aはITO(酸化インジウム錫)からなる透明層、P12bはAg(銀)、Al、Rh(ロジウム)などからなる反射層である。
図10に示す素子では、発光層13で発生される光が、結晶基板11の下面側から取り出される。そのため、この素子の実装形式としては、実装用基材の表面に設けられた正負のリード電極に対し、下部電極P11と、上部電極の反射層P12aとを、それぞれ、Au−Snハンダなどで接合することにより固定する、フリップチップ実装が適している。
FIG. 10 is a schematic diagram showing the structure of a conventional GaN-based LED disclosed in Japanese Patent Application Laid-Open No. 2004-179347 (Patent Document 1). 10A is a top view, and FIG. 10B is a cross-sectional view taken along line XY in FIG. 10A. In FIG. 10, 11 is a crystal substrate made of sapphire, 12 is an n-type layer made of a Si-doped GaN contact layer and a Si-doped AlGaN cladding layer laminated thereon, and 13 is an MQW (multiple quantum well) structure made of InGaN. A light emitting layer, p is a p-type layer composed of an Mg-doped AlGaN cladding layer and an Mg-doped GaN contact layer laminated thereon, P11 is a lower electrode formed by laminating Ti (titanium) and Al (aluminum), P12a and P12b constitute an upper electrode, P12a is a transparent layer made of ITO (indium tin oxide), and P12b is a reflective layer made of Ag (silver), Al, Rh (rhodium) or the like.
In the element shown in FIG. 10, light generated in the light emitting layer 13 is extracted from the lower surface side of the crystal substrate 11. Therefore, as a mounting form of this element, the lower electrode P11 and the reflective layer P12a of the upper electrode are bonded to the positive and negative lead electrodes provided on the surface of the mounting substrate with Au-Sn solder or the like, respectively. Flip chip mounting, which is fixed by doing so, is suitable.

特開2004−179347号公報JP 2004-179347 A

図10に示すGaN系LEDの発光層13で発生する光には、必ず、素子内部を上方に向かう成分、すなわち、結晶基板11の下面とは逆方向に向かう成分が含まれる。また、最初は素子内部を下方に向かって進んだ光が、素子内部に存在する屈折率界面や、素子内外を隔てる界面で反射されることにより、進行方向を上方に変えることもある。素子内部を上方に向かって進む光が、p型層14の側から、p型層14と透明層P12aとの界面に入射するとき、ITOの屈折率(約2)がGaNの屈折率(約2.5)の約80%であることから、スネルの法則により、入射角が約53度よりも大きな光は該界面で全反射され、入射角がこれよりも小さな光が、透明層P12aの内部に進入する。
図10に示す従来のGaN系LEDでは、この透明層P12aの内部に進入した光を、金属製の反射層P12bによって反射し、結晶基板11の方向に向かわせることにより、光取り出し効率を向上させようとしており、そのために、反射層P12bが、光反射性の良好なAg、Al、Rhなどで形成される。
しかしながら、金属製の反射部材による反射には比較的大きな損失が伴うことから、素子内部で多重反射が発生し易い発光ダイオードにおいて、反射部材を構成する金属材料の選択により光取り出し効率を向上させることには限界がある。
The light generated in the light-emitting layer 13 of the GaN-based LED shown in FIG. 10 always includes a component that goes upward in the element, that is, a component that goes in the direction opposite to the lower surface of the crystal substrate 11. In addition, the light traveling in the downward direction inside the element may be reflected at the refractive index interface existing inside the element or the interface separating the inside and outside of the element, thereby changing the traveling direction upward. When light traveling upward in the device enters the interface between the p-type layer 14 and the transparent layer P12a from the p-type layer 14 side, the refractive index of ITO (about 2) is changed to the refractive index of GaN (about 2.5) is approximately 80%, and according to Snell's law, light having an incident angle larger than approximately 53 degrees is totally reflected at the interface, and light having an incident angle smaller than this is reflected on the transparent layer P12a. Enter inside.
In the conventional GaN-based LED shown in FIG. 10, the light that has entered the transparent layer P12a is reflected by the metal reflective layer P12b and directed toward the crystal substrate 11, thereby improving the light extraction efficiency. For this reason, the reflective layer P12b is formed of Ag, Al, Rh or the like having good light reflectivity.
However, since the reflection by the metal reflecting member involves a relatively large loss, the light extraction efficiency is improved by selecting the metal material constituting the reflecting member in the light-emitting diode in which multiple reflection is likely to occur inside the element. Has its limits.

本発明は、上記従来技術の問題点に鑑みてなされたものであり、素子の内部を、光取り出し方向とは反対の方向に進行する光を、より効率的に反射させる構造を備えた、光取り出し効率の改善されたGaN系LEDを提供することを目的とする。   The present invention has been made in view of the above problems of the prior art, and is provided with a structure that more efficiently reflects light traveling in the direction opposite to the light extraction direction from the inside of the element. An object of the present invention is to provide a GaN-based LED with improved extraction efficiency.

(1)n型GaN系半導体層と、GaN系半導体からなる発光層と、p型GaN系半導体層とをこの順に含む積層体と、前記p型GaN系半導体層の表面に形成された、前記発光層で発生される光を透過するn型半導体からなる半導体電極層と、前記半導体電極層の表面に部分的に形成された金属電極と、前記金属電極を挟んで前記半導体電極層の表面に形成された、前記半導体電極層よりも低屈折率の透明絶縁膜と、前記透明絶縁膜の表面に形成された金属製の反射膜と、を有するGaN系発光ダイオード。
(2)前記半導体電極層が、酸化物半導体からなる、前記(1)に記載のGaN系発光ダイオード。
(3)前記酸化物半導体がITOである、前記(2)に記載のGaN系発光ダイオード。
(4)前記半導体電極層が、GaN系半導体からなる、前記(1)に記載のGaN系発光ダイオード。
(5)前記透明絶縁膜がSiOからなる、前記(1)〜(4)のいずれかに記載のGaN系発光ダイオード。
(6)前記反射膜の、発光層で発生される光を反射する部分が、AgまたはAlからなる、前記(1)〜(5)のいずれかに記載のGaN系発光ダイオード。
(7) 前記金属電極が、発光層で発生される光を反射する、AgまたはAlからなる部分を有する、前記(1)〜(6)のいずれかに記載のGaN系発光ダイオード。
(8)実装用基材と、その表面にフリップチップ実装された、前記(1)〜(7)のいずれかに記載のGaN系発光ダイオードとを含む、発光装置。
(1) A stack including an n-type GaN-based semiconductor layer, a light-emitting layer made of a GaN-based semiconductor, and a p-type GaN-based semiconductor layer in this order, and the surface formed on the surface of the p-type GaN-based semiconductor layer, A semiconductor electrode layer made of an n-type semiconductor that transmits light generated in the light emitting layer, a metal electrode partially formed on the surface of the semiconductor electrode layer, and a surface of the semiconductor electrode layer with the metal electrode interposed therebetween A GaN-based light emitting diode, comprising: a formed transparent insulating film having a refractive index lower than that of the semiconductor electrode layer; and a metal reflective film formed on a surface of the transparent insulating film.
(2) The GaN-based light emitting diode according to (1), wherein the semiconductor electrode layer is made of an oxide semiconductor.
(3) The GaN-based light emitting diode according to (2), wherein the oxide semiconductor is ITO.
(4) The GaN-based light-emitting diode according to (1), wherein the semiconductor electrode layer is made of a GaN-based semiconductor.
(5) The GaN-based light emitting diode according to any one of (1) to (4), wherein the transparent insulating film is made of SiO 2 .
(6) The GaN-based light emitting diode according to any one of (1) to (5), wherein a portion of the reflective film that reflects light generated in the light emitting layer is made of Ag or Al.
(7) The GaN-based light emitting diode according to any one of (1) to (6), wherein the metal electrode has a portion made of Ag or Al that reflects light generated in the light emitting layer.
(8) A light-emitting device comprising a mounting substrate and the GaN-based light-emitting diode according to any one of (1) to (7), which is flip-chip mounted on the surface thereof.

前記(1)に記載のGaN系LEDにおいては、p型GaN系半導体層の表面に形成される半導体電極層の表面に、金属製の反射部材が直接形成されるのではなく、該表面に部分的に形成された金属電極を挟んで、該半導体電極層よりも低屈折率の透明絶縁膜が形成され、その表面に金属製の反射膜が形成される。従って、p型GaN系半導体層側から半導体電極層の内部に進入する光の少なくとも一部は、金属電極や金属製の反射膜により反射されるのではなく、該半導体電極層と該透明絶縁膜との界面で全反射されることになる。絶縁体材料が有する高い光透過率のために、この全反射に伴う損失や、透明絶縁膜の内部に入射する一部の光が、該透明絶縁膜内を伝播する際に受ける損失は小さく、そのために、金属製の反射部材による反射を主に利用していた従来のGaN系LEDに比べて、光取り出し効率が改善される。   In the GaN-based LED described in (1) above, a metal reflecting member is not directly formed on the surface of the semiconductor electrode layer formed on the surface of the p-type GaN-based semiconductor layer, but is partially formed on the surface. A transparent insulating film having a refractive index lower than that of the semiconductor electrode layer is formed with the metal electrode thus formed interposed therebetween, and a metallic reflective film is formed on the surface thereof. Therefore, at least a part of the light entering the semiconductor electrode layer from the p-type GaN-based semiconductor layer side is not reflected by the metal electrode or the metal reflection film, but the semiconductor electrode layer and the transparent insulating film It will be totally reflected at the interface. Due to the high light transmittance of the insulating material, the loss due to this total reflection, and the loss received when a part of the light incident on the transparent insulating film propagates in the transparent insulating film is small. Therefore, the light extraction efficiency is improved as compared with a conventional GaN-based LED that mainly uses reflection by a metallic reflecting member.

以下、図面を参照して本発明を具体的に説明する。
図1は、本発明の実施形態に係るGaN系LEDの構造を示す模式図であり、図1(a)は上面図、図1(b)は図1(a)のX−Y線における断面図である。
図1において、1は結晶基板、2はn型層、3は発光層、4はp型層、P1は下部電極、P2aとP2bは上部電極で、P2aは半導体電極層、P2bは金属電極、Insは透明絶縁膜、Rは反射膜である。図1(a)における破線は、反射膜Rと透明絶縁膜Insの下に隠れている金属電極P2bの輪郭線を示しており、一点鎖線は、反射膜Rの下に隠れている、透明絶縁膜Insに設けられた開口部の輪郭線を表している。
Hereinafter, the present invention will be specifically described with reference to the drawings.
1A and 1B are schematic views showing the structure of a GaN-based LED according to an embodiment of the present invention. FIG. 1A is a top view, and FIG. 1B is a cross section taken along line XY in FIG. FIG.
In FIG. 1, 1 is a crystal substrate, 2 is an n-type layer, 3 is a light emitting layer, 4 is a p-type layer, P1 is a lower electrode, P2a and P2b are upper electrodes, P2a is a semiconductor electrode layer, P2b is a metal electrode, Ins is a transparent insulating film, and R is a reflective film. The broken line in FIG. 1A indicates the outline of the metal electrode P2b hidden under the reflective film R and the transparent insulating film Ins, and the alternate long and short dash line indicates the transparent insulation hidden under the reflective film R. An outline of an opening provided in the film Ins is shown.

図1に示す素子の各部の詳細構成は次の通りである。
結晶基板1はサファイア基板であり、素子分離後の寸法は、例えば、縦横それぞれ約350μm、厚さ100μmである。
n型層2は、Si(ケイ素)を5×1018cm−3の濃度でドープした、膜厚3μmのGaN層である。
発光層3は、膜厚8nmのGaN障壁層と膜厚2nmのInGaN井戸層を、各10層交互に積層してなる、MQW層である。
p型層4は、下層側から順に、Mg(マグネシウム)を5×1018cm−3の濃度でドープした膜厚30nmのp型Al0.1Ga0.9Nクラッド層と、Mgを5×1019cm−3の濃度でドープした膜厚200nmのp型GaNコンタクト層を積層したものである。
下部電極P1は、下層側から順に、膜厚20nmのTi、膜厚100nmのAl、膜厚100nmのPt、膜厚100nmのAu、膜厚100nmのPt、膜厚100nmのAu、膜厚100nmのPt、膜厚400nmのAuを積層し、熱処理したものである。
半導体電極層P2aは、膜厚150nmのITOである。
金属電極P2bは、膜厚100nmのAlである。
透明絶縁膜Insは、膜厚300nmのSiOである。
反射膜Rは、下層側から順に、膜厚100nmのAl、膜厚100nmのPt、膜厚100nmのAuを積層したものである。この反射膜Rは上部電極に対するボンディング用の電極を兼ねている。
The detailed configuration of each part of the element shown in FIG. 1 is as follows.
The crystal substrate 1 is a sapphire substrate, and the dimensions after element separation are, for example, about 350 μm in length and width and 100 μm in thickness.
The n-type layer 2 is a 3 μm-thick GaN layer doped with Si (silicon) at a concentration of 5 × 10 18 cm −3 .
The light emitting layer 3 is an MQW layer formed by alternately stacking 10 GaN barrier layers having a thickness of 8 nm and InGaN well layers having a thickness of 2 nm.
The p-type layer 4 includes, in order from the lower layer side, a p-type Al 0.1 Ga 0.9 N cladding layer having a thickness of 30 nm doped with Mg (magnesium) at a concentration of 5 × 10 18 cm −3 , and 5 Mg. A p-type GaN contact layer with a thickness of 200 nm doped at a concentration of × 10 19 cm −3 is laminated.
The lower electrode P1, in order from the lower layer side, is Ti with a thickness of 20 nm, Al with a thickness of 100 nm, Pt with a thickness of 100 nm, Au with a thickness of 100 nm, Pt with a thickness of 100 nm, Au with a thickness of 100 nm, and 100 nm with a thickness of 100 nm. Pt and Au with a film thickness of 400 nm are laminated and heat-treated.
The semiconductor electrode layer P2a is ITO having a film thickness of 150 nm.
The metal electrode P2b is 100 nm thick Al.
The transparent insulating film Ins is SiO 2 having a film thickness of 300 nm.
The reflective film R is formed by laminating 100 nm thick Al, 100 nm thick Pt, and 100 nm thick Au in order from the lower layer side. The reflective film R also serves as an electrode for bonding to the upper electrode.

図1に示すGaN系LEDは、次の方法で作製することができる。
(結晶成長)
結晶基板1として、直径2インチ、厚さ400μmのc面サファイア基板を用い、その成長面上に、MOVPE法など、公知のGaN系半導体結晶の成長方法を適宜用いて、n型層2、発光層3、p型層4を順次形成する。好ましくは、n型層2を成長する前に、結晶基板1の表面に、n型層2の成長温度よりも低温で、GaN、AlGaNなどからなる低温バッファ層を成長する。結晶成長の終了後、必要に応じて、p型層4に添加したMgを活性化するために、不活性ガス雰囲気中にて熱処理を行う。
The GaN-based LED shown in FIG. 1 can be manufactured by the following method.
(Crystal growth)
A c-plane sapphire substrate having a diameter of 2 inches and a thickness of 400 μm is used as the crystal substrate 1, and an n-type layer 2, light emission is appropriately formed on the growth surface by appropriately using a known GaN-based semiconductor crystal growth method such as the MOVPE method. Layer 3 and p-type layer 4 are formed sequentially. Preferably, before the n-type layer 2 is grown, a low-temperature buffer layer made of GaN, AlGaN or the like is grown on the surface of the crystal substrate 1 at a temperature lower than the growth temperature of the n-type layer 2. After the crystal growth is completed, heat treatment is performed in an inert gas atmosphere in order to activate Mg added to the p-type layer 4 as necessary.

(上部電極の形成)
p型層4の表面全体に、半導体電極層P2aを形成する。ITOからなる半導体電極層P2aの形成には、スパッタリング、真空蒸着、スプレー熱分解、クラスタービーム蒸着、パルスレーザ蒸着、イオンプレーティング、ゾル−ゲル法、レーザアブレーション、その他、公知のITO薄膜の作製法を適宜用いることができる。
図2(a)は、このようにして半導体電極層P2aの形成まで行ったウェハの上面図である。便宜上、ひとつの素子に相当する領域のみを図示しているが、素子分離前の工程はウェハの状態で行われる。図2(b)、図2(c)、図3(d)〜(f)も同様である。
半導体電極層P2aの形成後、その表面に、図2(b)に示すように、Alからなる金属電極P2bを部分的に形成する。金属電極P2bのパターニングは、公知のフォトリソグラフィ技法を用いた、リフトオフ法により行うことができる。リフトオフ法では、まず、半導体電極層P2aの表面全体にフォトレジスト膜を形成する。次に、フォトリソグラフィ技法を用いて、フォトレジスト膜に、形成しようとする金属電極P2bの形状に開口部を形成し、該開口部に半導体電極層P2aの表面を露出させる。次に、このフォトレジスト膜をマスクとして、蒸着、スパッタリング、CVD等、公知の金属薄膜の作製方法を適宜用いて、金属電極P2bの電極膜を形成する。その後、半導体電極層P2aの表面に、前記開口部の形状に形成された電極膜を残して、フォトレジスト膜をリフトオフする。
他の方法として、先に、金属電極P2bの電極膜を半導体電極層P2aの表面に全面的に形成し、その後、フォトリソグラフィ技法により所定形状にパターニングしたフォトレジスト膜をエッチングマスクとして、不要部分をエッチング除去することにより、金属電極P2bを所定の形状に形成することもできる。
なお、透明絶縁膜Ins、反射膜R、下部電極P1、p側ボンディング電極P2cのパターニングも、同様の方法で行うことができる。
(Formation of the upper electrode)
A semiconductor electrode layer P2a is formed on the entire surface of the p-type layer 4. For the formation of the semiconductor electrode layer P2a made of ITO, sputtering, vacuum vapor deposition, spray pyrolysis, cluster beam vapor deposition, pulsed laser vapor deposition, ion plating, sol-gel method, laser ablation, and other known ITO thin film production methods Can be used as appropriate.
FIG. 2A is a top view of the wafer that has been subjected to the formation of the semiconductor electrode layer P2a in this way. For convenience, only a region corresponding to one element is illustrated, but the process before element separation is performed in a wafer state. The same applies to FIGS. 2B, 2C, and 3D to 3F.
After the formation of the semiconductor electrode layer P2a, a metal electrode P2b made of Al is partially formed on the surface as shown in FIG. The patterning of the metal electrode P2b can be performed by a lift-off method using a known photolithography technique. In the lift-off method, first, a photoresist film is formed on the entire surface of the semiconductor electrode layer P2a. Next, using a photolithography technique, an opening is formed in the shape of the metal electrode P2b to be formed in the photoresist film, and the surface of the semiconductor electrode layer P2a is exposed in the opening. Next, using the photoresist film as a mask, an electrode film of the metal electrode P2b is formed by appropriately using a known method for producing a metal thin film such as vapor deposition, sputtering, or CVD. Thereafter, the photoresist film is lifted off leaving the electrode film formed in the shape of the opening on the surface of the semiconductor electrode layer P2a.
As another method, first, an electrode film of the metal electrode P2b is formed on the entire surface of the semiconductor electrode layer P2a, and then an unnecessary portion is formed using a photoresist film patterned in a predetermined shape by a photolithography technique as an etching mask. The metal electrode P2b can be formed into a predetermined shape by etching away.
The patterning of the transparent insulating film Ins, the reflective film R, the lower electrode P1, and the p-side bonding electrode P2c can also be performed by the same method.

(ドライエッチング)
塩素ガスを用いた反応性イオンエッチングにより、半導体電極層P2aの表面側から、半導体電極層P2a、p型層4、発光層3の一部を除去し、図2(c)に示すように、n型層2の表面を露出させる。
(Dry etching)
By reactive ion etching using chlorine gas, the semiconductor electrode layer P2a, the p-type layer 4, and the light emitting layer 3 are partially removed from the surface side of the semiconductor electrode layer P2a, and as shown in FIG. The surface of the n-type layer 2 is exposed.

(透明絶縁膜の形成)
図3(d)示すように、金属電極P2bを間に挟んで、半導体電極層P2aの表面に、SiOからなる透明絶縁膜Insを形成する。図3(d)に示す破線は、透明絶縁膜Insの下に隠れた金属電極P2bの輪郭線であり、図3(e)(f)においても同様である。透明絶縁膜Insの形成には、CVD、スパッタリング、蒸着、ゾル−ゲル法等、公知のSiO薄膜の作製方法を適宜用いることができる。後工程で、反射膜Rを、金属電極P2bと接触するように形成するために、透明絶縁膜Insには金属電極P2bの表面が露出する開口部が設けられる。
(Formation of transparent insulating film)
As shown in FIG. 3D, a transparent insulating film Ins made of SiO 2 is formed on the surface of the semiconductor electrode layer P2a with the metal electrode P2b interposed therebetween. The broken line shown in FIG. 3D is the outline of the metal electrode P2b hidden under the transparent insulating film Ins, and the same applies to FIGS. 3E and 3F. For the formation of the transparent insulating film Ins, a known method for producing a SiO 2 thin film such as CVD, sputtering, vapor deposition, sol-gel method, or the like can be appropriately used. In order to form the reflective film R in contact with the metal electrode P2b in a later step, the transparent insulating film Ins is provided with an opening through which the surface of the metal electrode P2b is exposed.

(反射膜の形成)
透明絶縁膜Insの表面に、蒸着、スパッタリング、CVD等、公知の金属薄膜の作製方法を適宜用いて、図3(e)に示すように、反射膜Rを形成する。反射膜Rは、透明絶縁膜Insに形成された開口部において、金属電極P2bと電気的に接続されるように形成される。図3(e)に示す一点鎖線は、反射膜Rの下に隠れた前記開口部の輪郭線であり、図3(f)においても同様である。
(Formation of reflective film)
As shown in FIG. 3E, a reflective film R is formed on the surface of the transparent insulating film Ins by appropriately using a known method for producing a metal thin film such as vapor deposition, sputtering, or CVD. The reflective film R is formed so as to be electrically connected to the metal electrode P2b in the opening formed in the transparent insulating film Ins. A dash-dot line shown in FIG. 3E is the outline of the opening hidden under the reflective film R, and the same applies to FIG.

(下部電極の形成)
前記ドライエッチング工程で露出されたn型層2の表面に、蒸着、スパッタリング、CVD等、公知の金属薄膜の作製方法を適宜用いて、図3(f)に示すように、下部電極P1を形成する。
この後、図示していないが、電極ボンディングのために露出させておく必要のある、下部電極P1および反射膜Rの表面の一部を残して、素子の上面側を、SiO、Si等からなる、絶縁保護膜で被覆することが好ましい。その際、該絶縁保護膜で被覆しようとする下部電極P1や反射膜Rの表面が、Auのように酸化し難い金属からなる場合には、該絶縁保護膜を形成する前に、該表面に膜厚10nm程度のTi薄膜やNi薄膜を形成しておくと、該絶縁保護膜との密着性が良好となる。
(Formation of lower electrode)
As shown in FIG. 3F, a lower electrode P1 is formed on the surface of the n-type layer 2 exposed in the dry etching process by appropriately using a known metal thin film manufacturing method such as vapor deposition, sputtering, or CVD. To do.
Thereafter, although not shown, the upper surface side of the element is made to be SiO 2 , Si 3 N while leaving a part of the surface of the lower electrode P1 and the reflective film R that need to be exposed for electrode bonding. It is preferable to cover with an insulating protective film made of 4 or the like. At this time, if the surface of the lower electrode P1 or the reflective film R to be covered with the insulating protective film is made of a metal that is difficult to oxidize, such as Au, before the insulating protective film is formed, If a Ti thin film or Ni thin film having a thickness of about 10 nm is formed, the adhesion with the insulating protective film is improved.

(熱処理)
電極と半導体との接触抵抗を低下させるために、ウェハ全体を熱処理し、電極とGaN系半導体との密着を促進させる。このような熱処理は、半導体の表面にオーミック電極を形成する際に行われる通常の処理であり、熱処理の温度と時間は、電極の材料にもよるが、温度は350℃〜900℃、時間は1分間〜60分間とすることができる。
(Heat treatment)
In order to reduce the contact resistance between the electrode and the semiconductor, the entire wafer is heat-treated to promote adhesion between the electrode and the GaN-based semiconductor. Such heat treatment is a normal treatment performed when an ohmic electrode is formed on the surface of the semiconductor. The temperature and time of the heat treatment depend on the material of the electrode, but the temperature is 350 ° C. to 900 ° C., and the time is It can be 1 minute to 60 minutes.

(素子分離)
結晶基板1の下面を研削および/または研磨することにより、その厚さを100μm以下となるまで薄くした後、スクライビング、ダイシング、レーザ溶断など、公知の素子分離方法を適宜用いて、素子分離を行う。
以上が、図1に示すGaN系LEDの作製方法である。
(Element isolation)
The lower surface of the crystal substrate 1 is ground and / or polished so that the thickness is reduced to 100 μm or less, and then element isolation is performed by appropriately using a known element isolation method such as scribing, dicing, or laser fusing. .
The above is the manufacturing method of the GaN-based LED shown in FIG.

図1に示すGaN系LEDでは、発光層3から直接、または、結晶基板1とn型層2との界面等で反射されることにより、素子内部を上方に向かって進行する光のうち、一部は金属電極P2bにより下方に反射されるが、残りの大部分は、p型層4と半導体電極層P2aとの界面に入射する。このうち、この界面に約53度よりも小さな入射角で入射する光が、半導体電極層P2aの内部に進入する。前述のように、GaNとITOとの界面にGaN側から入射する光は、入射角が約53度よりも大きいと全反射されるからである。
半導体電極層P2aの内部に進入する光のうち、透明絶縁膜Insとの界面に約49度よりも大きな入射角で入射する光は、SiOの屈折率(約1.5)がITOの屈折率の約75%であることから、スネルの法則に従い、この界面で全反射される。従って、p型層4と半導体電極層P2aとの界面で生じる屈折を考慮すると、p型層4から、p型層4と半導体電極層P2aとの界面に、約53度よりも小さな入射角で入射する光が、半導体電極層P2aの内部に進入し、そのうち、該入射角が約36度よりも大きい光は、半導体電極層P2aと透明絶縁膜Insとの界面で全反射されることになる。
In the GaN-based LED shown in FIG. 1, one of the light traveling upward in the element by being reflected directly from the light emitting layer 3 or at the interface between the crystal substrate 1 and the n-type layer 2. The portion is reflected downward by the metal electrode P2b, but most of the remaining portion is incident on the interface between the p-type layer 4 and the semiconductor electrode layer P2a. Among these, light incident on this interface at an incident angle smaller than about 53 degrees enters the semiconductor electrode layer P2a. As described above, the light incident on the interface between GaN and ITO from the GaN side is totally reflected when the incident angle is larger than about 53 degrees.
Of the light that enters the semiconductor electrode layer P2a, light that enters the interface with the transparent insulating film Ins at an incident angle greater than about 49 degrees has a refractive index of SiO 2 (about 1.5) that is refracted by ITO. Since it is about 75% of the rate, it is totally reflected at this interface according to Snell's law. Therefore, in consideration of the refraction generated at the interface between the p-type layer 4 and the semiconductor electrode layer P2a, the incident angle smaller than about 53 degrees from the p-type layer 4 to the interface between the p-type layer 4 and the semiconductor electrode layer P2a. Incident light enters the semiconductor electrode layer P2a, and light having an incident angle larger than about 36 degrees is totally reflected at the interface between the semiconductor electrode layer P2a and the transparent insulating film Ins. .

図1に示すGaN系LEDでは、図10に示す従来のGaN系LEDと異なり、この、p型層4と半導体電極層P2aとの界面に約36度〜約53度の入射角で入射する光を、金属製の反射部材(図10の素子においては反射層P12b)で反射させるのではなく、半導体電極層P2aと透明絶縁膜Insとの界面で全反射させるので、光取り出し効率が改善される。これは、絶縁体であるSiOの光吸収が小さいために、透明絶縁膜Insとの界面での全反射に伴う損失が、金属製の反射部材の表面での反射に伴う損失と比べて、小さくなるからである。
発光ダイオードの内部では多重反射が発生し易いという事情から、このような、素子内部での光反射に伴う損失を低減することは、光取り出し効率の改善に大きな効果を有する。
In the GaN-based LED shown in FIG. 1, unlike the conventional GaN-based LED shown in FIG. 10, the light incident on the interface between the p-type layer 4 and the semiconductor electrode layer P2a at an incident angle of about 36 degrees to about 53 degrees. Is not reflected by the metallic reflecting member (the reflecting layer P12b in the element of FIG. 10), but is totally reflected at the interface between the semiconductor electrode layer P2a and the transparent insulating film Ins, so that the light extraction efficiency is improved. . This is because the light absorption of SiO 2 that is an insulator is small, the loss associated with the total reflection at the interface with the transparent insulating film Ins is smaller than the loss associated with the reflection on the surface of the metallic reflecting member, This is because it becomes smaller.
In view of the fact that multiple reflections are likely to occur inside the light emitting diode, reducing the loss due to light reflection inside the element has a great effect on improving the light extraction efficiency.

図4は、図1に示すGaN系LEDを、実装用基材の表面にフリップチップ実装したところを示す模式図である。
図4において、Sは実装用基材であり、AlN等からなる絶縁性の基板S1の実装面側に、Auからなるリード電極S2、S3のパターンが形成されたものである。GaN系LEDは、上面側を実装用基材Sの実装面に向けて、下部電極P1がリード電極S2に、反射膜Rがリード電極S3に、それぞれ、導電性接合材料Cで接合されることにより固定されている。ここで、導電性接合材料Cは、例えば、Au−Snハンダ等のろう材や、導電体微粒子が樹脂バインダに分散されてなる導電性ペーストである。
FIG. 4 is a schematic view showing a state where the GaN-based LED shown in FIG. 1 is flip-chip mounted on the surface of the mounting base material.
In FIG. 4, S is a mounting base material, and a pattern of lead electrodes S2 and S3 made of Au is formed on the mounting surface side of an insulating substrate S1 made of AlN or the like. In the GaN-based LED, the lower electrode P1 is bonded to the lead electrode S2 and the reflective film R is bonded to the lead electrode S3 with the conductive bonding material C, with the upper surface side facing the mounting surface of the mounting substrate S. It is fixed by. Here, the conductive bonding material C is, for example, a conductive paste in which a brazing material such as Au—Sn solder or conductive fine particles are dispersed in a resin binder.

以上、本発明を具体的な実施形態に即して説明したが、本発明は前記実施形態に限定されない。   As described above, the present invention has been described based on the specific embodiment, but the present invention is not limited to the embodiment.

本発明の実施に係るGaN系LEDに用いる結晶基板は、GaN系半導体結晶の成長に適用可能な基板であって、かつ、発光層で発生される光を透過する透明基板であればよく、サファイアの他、SiC、GaN、ZnO、AlN、スピネル、NGO等からなる基板が例示される。SiC、GaN、ZnO等からなるn型の半導体基板を用いた場合には、結晶基板の下面に下部電極を形成することができるため、ドライエッチングによりn型層を露出させる工程が不要となる。また、フリップチップ実装の際には、上部電極のみを導電性接合材料で実装用基材のリード電極に固定すればよく、基板下面に形成される下部電極にはワイヤボンディングを行うことができるため、実装工程で、導電性接合材料による電極間の短絡が発生し難くなり、歩留りの改善が期待できる。
結晶基板の下面および/または上面には、発光層で発生される光を散乱させ得る凹凸構造を設けると、素子の光取り出し効率が更に改善される。
The crystal substrate used for the GaN-based LED according to the embodiment of the present invention may be a substrate applicable to the growth of a GaN-based semiconductor crystal and a transparent substrate that transmits light generated in the light-emitting layer, and sapphire Other examples include substrates made of SiC, GaN, ZnO, AlN, spinel, NGO, and the like. When an n-type semiconductor substrate made of SiC, GaN, ZnO or the like is used, a lower electrode can be formed on the lower surface of the crystal substrate, so that a step of exposing the n-type layer by dry etching is not necessary. In flip chip mounting, only the upper electrode needs to be fixed to the lead electrode of the mounting substrate with a conductive bonding material, and wire bonding can be performed on the lower electrode formed on the lower surface of the substrate. In the mounting process, a short circuit between the electrodes due to the conductive bonding material is less likely to occur, and an improvement in yield can be expected.
If a concavo-convex structure capable of scattering light generated in the light emitting layer is provided on the lower surface and / or the upper surface of the crystal substrate, the light extraction efficiency of the device is further improved.

本発明の実施に係るGaN系LEDは、pn接合型の発光素子構造が形成されるように、n型層、発光層、p型層が順に積層された積層体を含むが、各層の結晶組成、厚さ、不純物濃度、キャリア濃度などは、従来公知の技術を適宜参照して、設計することができる。この積層体と結晶基板との間や、この積層体の内部には、結晶層の歪を緩和する機能、不純物の望ましくない拡散を抑制する機能、発光層の分解を防止する機能、発光層で発生される光を散乱させる機能、その他、種々の機能を有する層を、適宜設けることができる。   The GaN-based LED according to the embodiment of the present invention includes a stacked body in which an n-type layer, a light-emitting layer, and a p-type layer are sequentially stacked so that a pn junction type light-emitting element structure is formed. The thickness, impurity concentration, carrier concentration, and the like can be designed by appropriately referring to conventionally known techniques. Between the laminated body and the crystal substrate, or inside the laminated body, there is a function of relaxing the distortion of the crystal layer, a function of suppressing unwanted diffusion of impurities, a function of preventing the decomposition of the light emitting layer, and a light emitting layer. Layers having various functions other than the function of scattering the generated light can be provided as appropriate.

本発明の実施に係るGaN系LEDにおいて、半導体電極層の材料は、発光層で発生される光を透過するn型半導体であればよく、ITOの他、酸化インジウム、酸化錫、酸化亜鉛など、n型伝導性を示す各種の酸化物半導体を用いることができる。また、n型GaN系半導体を用いることもできる。n型GaN系半導体を用いる場合には、半導体電極層の成長を、p型層の成長と連続して、同じ方法を用いて、同じ製造装置内で行うこともできる。
いずれの材料で半導体電極層を形成する場合も、p型層との接合障壁が薄くなるように、キャリア濃度は高くすることが望ましい。また、接合界面にAuなどの金属からなる透明または島状の薄膜を介在させるなど、半導体電極層とp型層と接合部の抵抗を低下させるための公知の構造を適宜採用することができる。
In the GaN-based LED according to the implementation of the present invention, the material of the semiconductor electrode layer may be an n-type semiconductor that transmits light generated in the light emitting layer, and in addition to ITO, indium oxide, tin oxide, zinc oxide, etc. Various oxide semiconductors exhibiting n-type conductivity can be used. An n-type GaN-based semiconductor can also be used. In the case of using an n-type GaN-based semiconductor, the growth of the semiconductor electrode layer can be performed in the same manufacturing apparatus by using the same method in succession to the growth of the p-type layer.
When the semiconductor electrode layer is formed of any material, it is desirable to increase the carrier concentration so that the junction barrier with the p-type layer becomes thin. In addition, a known structure for reducing the resistance of the semiconductor electrode layer, the p-type layer, and the bonding portion, such as interposing a transparent or island-shaped thin film made of a metal such as Au at the bonding interface, can be appropriately employed.

本発明の実施に係るGaN系LEDにおいて、下部電極、金属電極は、Ni(ニッケル)、Au(金)、Pt(白金)、Pd(パラジウム)、Rh(ロジウム)、Ru(ルテニウム)、Os(オスミウム)、Ir(イリジウム)、Ti(チタン)、Al(アルミニウム)、Zr(ジルコニウム)、Hf(ハフニウム)、V(バナジウム)、Nb(ニオブ)、Ta(タンタル)、Co(コバルト)、Fe(鉄)、Mn(マンガン)、Mo(モリブデン)、Cr(クロム)、W(タングステン)、La(ランタン)、Cu(銅)、Ag(銀)、Y(イットリウム)などの単体や合金で形成することができ、積層構造を採用することもできる。また、下部電極とn型層との間には酸化物半導体層を介在させることもできる。下部電極を、n型の半導体基板の下面に設ける場合も同様である。   In the GaN-based LED according to the embodiment of the present invention, the lower electrode and the metal electrode are Ni (nickel), Au (gold), Pt (platinum), Pd (palladium), Rh (rhodium), Ru (ruthenium), Os ( Osmium), Ir (iridium), Ti (titanium), Al (aluminum), Zr (zirconium), Hf (hafnium), V (vanadium), Nb (niobium), Ta (tantalum), Co (cobalt), Fe ( Iron, Mn (manganese), Mo (molybdenum), Cr (chromium), W (tungsten), La (lanthanum), Cu (copper), Ag (silver), Y (yttrium), etc. It is also possible to adopt a laminated structure. In addition, an oxide semiconductor layer can be interposed between the lower electrode and the n-type layer. The same applies to the case where the lower electrode is provided on the lower surface of the n-type semiconductor substrate.

金属電極は、これを挟んで積層される半導体電極層と透明絶縁膜とが接触し得るように、半導体電極層の表面に部分的に形成する。図1に示す素子では、金属電極P2bが粗い格子状のパターンに形成されているが、金属電極の形状はこれに限定されず、他のネット状パターンとしてもよいし、ストライプ状、櫛状、放射状、環状、ミアンダ状、渦巻き状、樹枝状等に形成してもよく、これらが複合されたパターンとしてもよい。
金属電極のパターンは、半導体電極層のシート抵抗に応じて、該シート抵抗が高い場合には、半導体電極層の表面上に金属電極の電極膜が密に分散されるように、該シート抵抗が低い場合には、該表面上に該電極膜が疎に分散されるように、形成することが好ましい。これは、半導体電極層のシート抵抗が高い場合には、横方向の電流拡散を金属電極で補う必要性が生じる一方、該シート抵抗が低い場合にはその必要がなく、それよりも光反射性の改善のために、半導体電極層と透明絶縁膜との界面の面積を大きくすることが好ましいためである。
The metal electrode is partially formed on the surface of the semiconductor electrode layer so that the semiconductor electrode layer and the transparent insulating film stacked with the metal electrode in between can be brought into contact with each other. In the element shown in FIG. 1, the metal electrode P2b is formed in a coarse lattice pattern, but the shape of the metal electrode is not limited to this, and may be another net pattern, stripe shape, comb shape, It may be formed in a radial shape, a ring shape, a meander shape, a spiral shape, a dendritic shape, or the like, or a pattern in which these are combined.
When the sheet resistance of the metal electrode pattern is high according to the sheet resistance of the semiconductor electrode layer, the sheet resistance is set so that the electrode film of the metal electrode is densely dispersed on the surface of the semiconductor electrode layer. When it is low, it is preferable to form the electrode film so as to be sparsely dispersed on the surface. This is because when the sheet resistance of the semiconductor electrode layer is high, it is necessary to supplement the current diffusion in the lateral direction with a metal electrode, whereas when the sheet resistance is low, this is not necessary, and light reflectivity is higher than that. This is because it is preferable to increase the area of the interface between the semiconductor electrode layer and the transparent insulating film.

金属電極の膜厚に特に限定はないが、素子の光取出し効率を向上させるためには、十分な光反射性が生じる膜厚に形成することが望ましい。従って、金属電極の膜厚は、好ましくは30nm以上、より好ましくは50nm以上、特に好ましくは100nm以上である。膜厚が一定の値より大きくなると効果が飽和し、それ以上の膜厚とすることは材料の浪費となる。このことから、金属電極の好ましい膜厚は1μm以下である。   The film thickness of the metal electrode is not particularly limited, but it is desirable to form the film so as to generate sufficient light reflectivity in order to improve the light extraction efficiency of the element. Therefore, the film thickness of the metal electrode is preferably 30 nm or more, more preferably 50 nm or more, and particularly preferably 100 nm or more. When the film thickness is larger than a certain value, the effect is saturated, and when the film thickness is larger than that, the material is wasted. From this, the preferable film thickness of the metal electrode is 1 μm or less.

下部電極の膜厚は、実装の際に受ける衝撃に耐えることができ、かつ、剥離が生じ難くなる厚さであればよく、例えば、200nm〜3μmとすることができる。下部電極の上面と、上部電極に対するボンディング用電極の上面の高さがほぼ同じとなる厚さを選択することもできる。
図1に示す素子の下部電極P1は、最上層部分がろう材との濡れ性の良好なAuで形成されているが、このAuが、下層部分に含まれるAlと合金化反応を生じると、下部電極の特性、ひいては素子の特性が劣化する恐れがある。そこで、これを抑制するために、Alの上にAuを直接積層せず、Al層とAu層の間には、高融点金属(W、Mo、Zr、Ti、白金族から選ばれる単体または、それらの合金)のひとつであるPtからなる層を、バリア層として介在させている。
The thickness of the lower electrode may be any thickness as long as it can withstand the impact received during mounting and does not easily cause peeling, and can be, for example, 200 nm to 3 μm. It is also possible to select a thickness at which the upper surface of the lower electrode and the upper surface of the bonding electrode with respect to the upper electrode have substantially the same height.
In the lower electrode P1 of the element shown in FIG. 1, the uppermost layer portion is formed of Au having good wettability with the brazing material. When this Au causes an alloying reaction with Al contained in the lower layer portion, There is a risk that the characteristics of the lower electrode, and thus the characteristics of the element, will deteriorate. Therefore, in order to suppress this, Au is not directly laminated on Al, and a refractory metal (W, Mo, Zr, Ti, a simple substance selected from the platinum group or between the Al layer and the Au layer, or A layer made of Pt, which is one of those alloys, is interposed as a barrier layer.

下部電極や金属電極が、発光層で発生される光を反射し得るように構成されている場合、該反射に伴う損失が小さくなるよう、これらの電極の、少なくとも、該光を反射する部分は、光反射性の良好な金属であるAg、Al、Rh、Pt、Ir、Pdなどで形成することが好ましい。AgとAlは、GaN系LEDの典型的な発光波長である、緑色〜近紫外にかけての波長領域での反射率が特に高いことから、最も好ましい材料である。   When the lower electrode or the metal electrode is configured to reflect the light generated in the light emitting layer, at least a portion of the electrode that reflects the light is reduced so that the loss due to the reflection is reduced. It is preferable to use Ag, Al, Rh, Pt, Ir, Pd, etc., which are metals having good light reflectivity. Ag and Al are the most preferable materials because they have a particularly high reflectance in a wavelength region from green to near ultraviolet, which is a typical emission wavelength of a GaN-based LED.

本発明の実施に係るGaN系LEDにおいて、透明絶縁膜の材料は、発光層で発生される光を透過し、かつ、その屈折率が半導体電極層の屈折率よりも小さい材料であればよいが、熱的、化学的な安定性の点からは、無機絶縁体を用いることが好ましい。このような無機絶縁体として、SiOの他に、Al、スピネル、ZrO、TiO、Si、AlN等、各種の金属酸化物、金属窒化物が使用可能であり、半導体電極層の材料に応じて、それよりも屈折率の小さいものを適宜選択すればよい。
半導体電極層と透明絶縁膜との界面で、屈折率差による反射が十分に生じるように、透明絶縁膜の屈折率は、半導体電極層の屈折率の85%以下とすることが好ましく、80%以下とすることがより好ましく、75%以下とすることが特に好ましい。屈折率が低いSiOは、半導体電極層の材料によらず、透明絶縁膜の最も好ましい材料のひとつである。
In the GaN-based LED according to the embodiment of the present invention, the material of the transparent insulating film may be any material that transmits light generated in the light emitting layer and whose refractive index is smaller than that of the semiconductor electrode layer. From the viewpoint of thermal and chemical stability, it is preferable to use an inorganic insulator. As such an inorganic insulator, various metal oxides and metal nitrides such as Al 2 O 3 , spinel, ZrO 2 , TiO 2 , Si 3 N 4 , and AlN can be used in addition to SiO 2 . According to the material of the semiconductor electrode layer, a material having a smaller refractive index may be selected as appropriate.
The refractive index of the transparent insulating film is preferably 85% or less of the refractive index of the semiconductor electrode layer so that reflection due to the refractive index difference is sufficiently generated at the interface between the semiconductor electrode layer and the transparent insulating film, and 80% More preferably, it is more preferably 75% or less. SiO 2 having a low refractive index is one of the most preferable materials for the transparent insulating film regardless of the material of the semiconductor electrode layer.

透明絶縁膜の厚さは、本発明の効果が生じる厚さであればよく、特に限定はないが、半導体電極層と透明絶縁膜の界面で光が全反射される際に、透明絶縁膜の内部に染み出す光が、反射膜により受ける吸収が小さくなるよう、透明絶縁膜の厚さは100nm以上とすることが好ましく、200nm以上とすることがより好ましく、300nm以上とすることが特に好ましい。   The thickness of the transparent insulating film is not particularly limited as long as the effect of the present invention is produced, but when the light is totally reflected at the interface between the semiconductor electrode layer and the transparent insulating film, The thickness of the transparent insulating film is preferably 100 nm or more, more preferably 200 nm or more, and particularly preferably 300 nm or more so that the light that penetrates to the inside is less absorbed by the reflective film.

透明絶縁膜は、半導体電極層の上面部のみならず、その一部を延長して、ドライエッチングにより露出された半導体電極層、p型層、発光層の端面を覆うように形成してもよい。このような実施形態に係る素子の断面構造例を、図5に示す。図5に示す素子では、下部電極P1が形成された部分を除き、ドライエッチングにより露出されたn型層2の表面をも覆うように、透明絶縁膜Insの一部が延長して形成されている。   The transparent insulating film may be formed so as to extend not only the upper surface portion of the semiconductor electrode layer but also partially extend the semiconductor electrode layer, the p-type layer, and the light emitting layer exposed by dry etching. . An example of a cross-sectional structure of the element according to such an embodiment is shown in FIG. In the element shown in FIG. 5, a part of the transparent insulating film Ins is formed to extend so as to cover the surface of the n-type layer 2 exposed by dry etching except for the portion where the lower electrode P1 is formed. Yes.

本発明の実施に係るGaN系LEDにおいて、反射膜は、光反射性を有する金属膜であればよい。膜厚を20nmよりも薄くすると、金属膜であってもかなりの光透過性を示すことから、反射膜の膜厚は30nm以上とすることが好ましい。反射膜のより好ましい厚さは50nm以上であり、特に好ましい厚さは100nm以上である。反射膜の、少なくとも、発光層で発生される光を反射する部分は、光反射性の良好な金属であるAg、Al、Rh、Pt、Ir、Pdなどで形成することが好ましく、特に、AgまたはAlで形成することが好ましい。
金属電極や反射膜の材料にAgやAlを用いる場合、光反射性の観点からはAgやAlの単体を用いることが好ましいが、化学的安定性や耐熱性を向上させるために各種の元素を添加したAg合金やAl合金も、好適に用い得る。光反射性を大きく損なうことなく、化学的安定性や耐熱性を改善したAg合金やAl合金が、液晶表示装置など、各種のディスプレー装置の配線材料用に開発されているが、そのようなAg合金やAl合金は、金属電極や反射膜の材料として好適に用いることができる。
In the GaN-based LED according to the embodiment of the present invention, the reflection film may be a metal film having light reflectivity. When the film thickness is thinner than 20 nm, even a metal film exhibits a considerable light transmittance, and therefore the thickness of the reflective film is preferably 30 nm or more. A more preferable thickness of the reflective film is 50 nm or more, and a particularly preferable thickness is 100 nm or more. It is preferable that at least a portion of the reflective film that reflects light generated in the light emitting layer is formed of Ag, Al, Rh, Pt, Ir, Pd, or the like, which is a metal having good light reflectivity. Or it is preferable to form with Al.
When Ag or Al is used for the material of the metal electrode or the reflective film, it is preferable to use Ag or Al alone from the viewpoint of light reflectivity, but various elements may be added to improve chemical stability and heat resistance. An added Ag alloy or Al alloy can also be suitably used. Ag alloys and Al alloys with improved chemical stability and heat resistance without significantly impairing light reflectivity have been developed for wiring materials for various display devices such as liquid crystal display devices. An alloy or an Al alloy can be suitably used as a material for a metal electrode or a reflective film.

図1に示す素子の反射膜Rは、上部電極に対するボンディング用の電極を兼ねているために、その最上層部分がろう材との濡れ性の良好なAuで形成されている。一方、最下層部分はAlで形成されていることから、AlとAuの合金化反応によって反射膜Rの光反射性が低下しないよう、最下層部分と最上層部分との間には、Ptからなる層がバリア層として設けられている。   Since the reflective film R of the element shown in FIG. 1 also serves as an electrode for bonding to the upper electrode, its uppermost layer portion is formed of Au having good wettability with the brazing material. On the other hand, since the lowermost layer portion is made of Al, Pt is not formed between the lowermost layer portion and the uppermost layer portion so that the light reflectivity of the reflective film R is not lowered by the alloying reaction between Al and Au. This layer is provided as a barrier layer.

反射膜は、上部電極とではなく、下部電極と電気的に接続されるように、もしくは、下部電極と一体的に、形成することもできる。その場合、反射膜を、下部電極に対するボンディング用の電極として利用することもできる。
図6(a)(b)は、このような実施形態に係るGaN系LEDの構造例を示す模式図であり、図6(a)は上面図、図6(b)は図6(a)のX−Y線における断面図である。図6に示す素子では、反射膜Rと下部電極P1とが一体的に形成されているが、それによって素子のp型層側とn型層側が短絡されないように、透明絶縁膜Insの一部が、ドライエッチングにより露出された半導体電極層P2a、p型層4および発光層3の端面を覆うように、延長して形成されている。この実施形態では、透明絶縁膜で隔てられた反射膜と上部電極とが短絡するのを確実に防止するために、透明絶縁膜を、ピンホールが発生し難いプラズマCVD法を用いて形成することが好ましい。
また、図6において、P2cは、上部電極の一部をなすp側ボンディング電極であり、透明絶縁膜Insに設けられた開口部の位置に、金属電極P2bと接触するように形成されている。p側ボンディング電極P2cの材料に特に限定はないが、少なくとも表面部分を、ろう材との濡れ性の良好なAu、Sn、In等で形成することが好ましい。
このような、反射膜と下部電極とを接続または一体化する実施形態は、反射膜の材料にAgを用いる場合に特に適している。Agは光反射性の最も優れた金属であるが、高電位状態に置かれると電気化学的マイグレーションを生じ易いという問題があるのに対し、この実施形態では、反射膜が低電位側の電極である下部電極と接続されるために、この問題が軽減される。
The reflective film can be formed so as to be electrically connected to the lower electrode instead of the upper electrode, or integrally with the lower electrode. In that case, the reflective film can also be used as an electrode for bonding to the lower electrode.
6 (a) and 6 (b) are schematic views showing an example of the structure of a GaN-based LED according to such an embodiment, where FIG. 6 (a) is a top view and FIG. 6 (b) is FIG. 6 (a). It is sectional drawing in the XY line. In the element shown in FIG. 6, the reflective film R and the lower electrode P1 are integrally formed. However, a part of the transparent insulating film Ins is prevented so that the p-type layer side and the n-type layer side of the element are not short-circuited. Are extended so as to cover the end surfaces of the semiconductor electrode layer P2a, the p-type layer 4 and the light emitting layer 3 exposed by dry etching. In this embodiment, in order to reliably prevent a short circuit between the reflective film and the upper electrode separated by the transparent insulating film, the transparent insulating film is formed using a plasma CVD method in which pinholes are unlikely to occur. Is preferred.
In FIG. 6, P2c is a p-side bonding electrode that forms a part of the upper electrode, and is formed in contact with the metal electrode P2b at the position of the opening provided in the transparent insulating film Ins. The material of the p-side bonding electrode P2c is not particularly limited, but it is preferable that at least the surface portion is formed of Au, Sn, In or the like having good wettability with the brazing material.
Such an embodiment in which the reflective film and the lower electrode are connected or integrated is particularly suitable when Ag is used as the material of the reflective film. Ag is the metal having the best light reflectivity, but there is a problem in that it tends to cause electrochemical migration when placed in a high potential state, whereas in this embodiment, the reflective film is an electrode on the low potential side. This problem is alleviated because it is connected to a certain lower electrode.

反射膜の一部を下部電極と接続または一体化し、他の一部を、上部電極に対するボンディング電極と兼用させることもできる。このような実施形態に係るGaN系LEDの構造例を、図7に模式的に示す。図7(a)は素子の上面図、図7(b)は図7(a)のX−Y線における断面図である。図7に示す素子では、反射膜R1が下部電極P1と一体的に形成されており、反射膜R2が上部電極P2a、P2bに対するボンディング用の電極を兼用している。   A part of the reflective film can be connected to or integrated with the lower electrode, and the other part can also be used as a bonding electrode for the upper electrode. An example of the structure of a GaN-based LED according to such an embodiment is schematically shown in FIG. 7A is a top view of the element, and FIG. 7B is a cross-sectional view taken along line XY in FIG. 7A. In the element shown in FIG. 7, the reflective film R1 is formed integrally with the lower electrode P1, and the reflective film R2 also serves as an electrode for bonding to the upper electrodes P2a and P2b.

反射膜は、下部電極、上部電極のいずれからも独立させて形成することもできる。このような実施形態に係るGaN系LEDの構造例を、図8に模式的に示す。図8(a)は素子の上面図、図8(b)は図8(a)のX−Y線における断面図である。
図8(a)において、破線は、反射膜Rと透明絶縁膜Insの下に隠れている金属電極P2bの輪郭線を示している。この金属電極P2bは、その上にp側ボンディング電極P2cが積層された方形の部分と、該方形の部分から伸びた二本のストライプ状の部分とから構成されている。
The reflective film can also be formed independently of either the lower electrode or the upper electrode. A structural example of a GaN-based LED according to such an embodiment is schematically shown in FIG. 8A is a top view of the element, and FIG. 8B is a cross-sectional view taken along line XY in FIG. 8A.
In FIG. 8A, the broken line indicates the outline of the metal electrode P2b hidden under the reflective film R and the transparent insulating film Ins. The metal electrode P2b is composed of a rectangular portion on which the p-side bonding electrode P2c is stacked, and two stripe-shaped portions extending from the rectangular portion.

本発明の一実施形態に係るGaN系LEDにおいては、GaN系半導体層の成長に用いられる結晶基板が、最終的に素子から除去される。このような実施形態に係るGaN系LEDの構造および製造工程の例を、図9を用いて説明する。図9(a)〜(c)は、いずれも断面図であり、便宜上、ひとつの素子に相当する領域のみを表示しているが、素子分離前の工程はウェハの状態で行われる。
図9(a)は、結晶基板1の成長面上に、n型層2、発光層3、p型層4が順次成長され、更に、半導体電極層P2a、金属電極P2b、透明絶縁膜Ins、反射膜Rが形成されたところを示す。各部分の構成は、結晶基板を除去しない実施形態において採用し得る構成と同じである。
図9(b)は、反射膜Rの上に、導電性接合材料(図示せず)を介して、保持基板Bが接合されたところを示す。導電性接合材料は、例えば、ろう材や、導電性ペーストである。保持基板Bは、導電性基板であればよく、各種の半導体基板や、金属基板を用いることができる。保持基板Bを接合することにより、結晶基板1を除去した後も、ウェハや素子のハンドリングを通常の方法により行うことができる。保持基板Bを導電性接合材料で接合する代わりに、反射膜Rの表面に、メッキ法によってNiなどの金属の厚膜を堆積させ、これを保持基板Bとして用いることもできる。
図9(c)は、結晶基板1が除去され、露出されたn型層2の表面に、下部電極P1が形成されたところを示す。結晶基板1の除去は、従来公知の技術を用いて行うことができ、例えば、研削・研磨により結晶基板1を摩滅させる方法、レーザリフトオフの技術を用いて結晶基板1をn型層2から剥離させる方法、結晶基板1そのものを、または結晶基板1とn型層2との間に予め形成されたバッファ層(図示せず)を、選択的に溶解することにより、結晶基板1を消失させる、またはn型層2から剥離する方法などが用い得る。結晶基板1の除去により露出されるn型層2の表面は、下部電極P1を形成する前に、必要に応じて研磨やエッチングを行い、清浄化する。その後は、従来公知の方法を用いて、素子分離を行う。
レーザリフトオフの技術を用いると、結晶基板を除去することなく、通常の方法で作製した素子をフリップチップ実装した後、実装された素子から結晶基板を剥離除去することもできる。
In the GaN-based LED according to one embodiment of the present invention, the crystal substrate used for the growth of the GaN-based semiconductor layer is finally removed from the device. An example of the structure and manufacturing process of a GaN-based LED according to such an embodiment will be described with reference to FIG. FIGS. 9A to 9C are cross-sectional views, and for convenience, only a region corresponding to one element is displayed. However, a process before element separation is performed in a wafer state.
In FIG. 9A, an n-type layer 2, a light emitting layer 3, and a p-type layer 4 are sequentially grown on the growth surface of the crystal substrate 1, and further, a semiconductor electrode layer P2a, a metal electrode P2b, a transparent insulating film Ins, The place where the reflective film R is formed is shown. The structure of each part is the same as that which can be adopted in the embodiment in which the crystal substrate is not removed.
FIG. 9B shows a state where the holding substrate B is bonded onto the reflective film R via a conductive bonding material (not shown). The conductive bonding material is, for example, a brazing material or a conductive paste. The holding substrate B may be any conductive substrate, and various semiconductor substrates and metal substrates can be used. By bonding the holding substrate B, the wafer and the element can be handled by a normal method even after the crystal substrate 1 is removed. Instead of bonding the holding substrate B with a conductive bonding material, a thick film of a metal such as Ni can be deposited on the surface of the reflective film R by plating, and this can be used as the holding substrate B.
FIG. 9C shows that the crystal substrate 1 is removed and the lower electrode P1 is formed on the exposed surface of the n-type layer 2. The crystal substrate 1 can be removed using a conventionally known technique. For example, the crystal substrate 1 is peeled off from the n-type layer 2 using a method of abrasion of the crystal substrate 1 by grinding or polishing, or a laser lift-off technique. A method of causing the crystal substrate 1 to disappear by selectively dissolving the crystal substrate 1 itself or a buffer layer (not shown) formed in advance between the crystal substrate 1 and the n-type layer 2; Alternatively, a method of peeling from the n-type layer 2 can be used. The surface of the n-type layer 2 exposed by removing the crystal substrate 1 is cleaned by polishing or etching as necessary before forming the lower electrode P1. Thereafter, element isolation is performed using a conventionally known method.
When the laser lift-off technique is used, an element manufactured by a normal method can be flip-chip mounted without removing the crystal substrate, and then the crystal substrate can be peeled off from the mounted element.

本発明の実施形態に係るGaN系発光ダイオードの構造を説明する図である。It is a figure explaining the structure of the GaN-type light emitting diode which concerns on embodiment of this invention. 図1に示すGaN系発光ダイオードの製造工程を説明する図である。It is a figure explaining the manufacturing process of the GaN-type light emitting diode shown in FIG. 図1に示すGaN系発光ダイオードの製造工程を説明する図である。It is a figure explaining the manufacturing process of the GaN-type light emitting diode shown in FIG. 本発明の実施形態に係るGaN系発光ダイオードのフリップチップ実装例を説明する図である。It is a figure explaining the flip-chip mounting example of the GaN-type light emitting diode which concerns on embodiment of this invention. 本発明の実施形態に係るGaN系発光ダイオードの構造を説明する図である。It is a figure explaining the structure of the GaN-type light emitting diode which concerns on embodiment of this invention. 本発明の実施形態に係るGaN系発光ダイオードの構造を説明する図である。It is a figure explaining the structure of the GaN-type light emitting diode which concerns on embodiment of this invention. 本発明の実施形態に係るGaN系発光ダイオードの構造を説明する図である。It is a figure explaining the structure of the GaN-type light emitting diode which concerns on embodiment of this invention. 本発明の実施形態に係るGaN系発光ダイオードの構造を説明する図である。It is a figure explaining the structure of the GaN-type light emitting diode which concerns on embodiment of this invention. 本発明の実施形態に係るGaN系発光ダイオードの構造および製造工程を説明する図である。It is a figure explaining the structure and manufacturing process of the GaN-type light emitting diode which concern on embodiment of this invention. 従来技術に係るGaN系発光ダイオードの構造を示す図である。It is a figure which shows the structure of the GaN-type light emitting diode which concerns on a prior art.

符号の説明Explanation of symbols

1 結晶基板
2 n型GaN系半導体層
3 発光層
4 p型GaN系半導体層
P1 下部電極
P2a 半導体電極層
P2b 金属電極
P2c p側ボンディング電極
Ins 透明絶縁膜
R 反射膜
DESCRIPTION OF SYMBOLS 1 Crystal substrate 2 n-type GaN-type semiconductor layer 3 Light emitting layer 4 p-type GaN-type semiconductor layer P1 Lower electrode P2a Semiconductor electrode layer P2b Metal electrode P2c P side bonding electrode Ins Transparent insulating film R Reflective film

Claims (8)

n型GaN系半導体層と、GaN系半導体からなる発光層と、p型GaN系半導体層とをこの順に含む積層体と、
前記p型GaN系半導体層の表面に形成された、前記発光層で発生される光を透過するn型半導体からなる半導体電極層と、
前記半導体電極層の表面に部分的に形成された金属電極と、
前記金属電極を挟んで前記半導体電極層の表面に形成された、前記半導体電極層よりも低屈折率の透明絶縁膜と、
前記透明絶縁膜の表面に形成された金属製の反射膜と、
を有するGaN系発光ダイオード。
a laminate including an n-type GaN-based semiconductor layer, a light-emitting layer made of a GaN-based semiconductor, and a p-type GaN-based semiconductor layer in this order;
A semiconductor electrode layer formed on the surface of the p-type GaN-based semiconductor layer and made of an n-type semiconductor that transmits light generated in the light-emitting layer;
A metal electrode partially formed on the surface of the semiconductor electrode layer;
A transparent insulating film having a refractive index lower than that of the semiconductor electrode layer formed on the surface of the semiconductor electrode layer with the metal electrode interposed therebetween;
A metal reflective film formed on the surface of the transparent insulating film;
A GaN-based light emitting diode having:
前記半導体電極層が、酸化物半導体からなる、請求項1に記載のGaN系発光ダイオード。   The GaN-based light emitting diode according to claim 1, wherein the semiconductor electrode layer is made of an oxide semiconductor. 前記酸化物半導体がITOである、請求項2に記載のGaN系発光ダイオード。   The GaN-based light emitting diode according to claim 2, wherein the oxide semiconductor is ITO. 前記半導体電極層が、GaN系半導体からなる、請求項1に記載のGaN系発光ダイオード。   The GaN-based light-emitting diode according to claim 1, wherein the semiconductor electrode layer is made of a GaN-based semiconductor. 前記透明絶縁膜がSiOからなる、請求項1〜4のいずれかに記載のGaN系発光ダイオード。 The GaN-based light-emitting diode according to claim 1, wherein the transparent insulating film is made of SiO 2 . 前記反射膜の、発光層で発生される光を反射する部分が、AgまたはAlからなる、請求項1〜5のいずれかに記載のGaN系発光ダイオード。   The GaN-based light emitting diode according to any one of claims 1 to 5, wherein a portion of the reflective film that reflects light generated in the light emitting layer is made of Ag or Al. 前記金属電極が、発光層で発生される光を反射する、AgまたはAlからなる部分を有する、請求項1〜6のいずれかに記載のGaN系発光ダイオード。   The GaN-based light emitting diode according to claim 1, wherein the metal electrode has a portion made of Ag or Al that reflects light generated in the light emitting layer. 実装用基材と、その表面にフリップチップ実装された、請求項1〜7のいずれかに記載のGaN系発光ダイオードとを含む、発光装置。

A light-emitting device comprising a mounting substrate and the GaN-based light-emitting diode according to claim 1 mounted on the surface thereof in a flip-chip manner.

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