JP4738999B2 - Semiconductor optical device manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor optical device. It is particularly useful for group III nitride compound semiconductor optical devices. In this specification, the term “semiconductor optical element” refers to a light-emitting element, a light-receiving element, a conversion element from one to the other of light energy and electric energy, and other semiconductor elements having an arbitrary optical function.

Group III nitride compound semiconductor light emitting devices have emerged as light emitting devices that emit green, blue or ultraviolet light, and have different types of light emitting devices such as sapphire substrates and epitaxially grown light emitting devices on insulating substrates, or different types of materials such as silicon and SiC. The one using the conductive substrate is known. On the other hand, a technique for making a substrate for epitaxial growth different from a support substrate when used as an element, that is, a technique for transferring a group III nitride compound semiconductor layer or a group III nitride compound semiconductor element to another substrate after epitaxial growth. (Patent Documents 1 to 4, Non-Patent Document 1).
Patent 3418150 Special table 2001-501778 Special table 2005-522873 USP 6071795 Kelly et al., “Optical process for liftoff of group III-nitride films”, Physica Status Solidi (a) vol. 159, 1997, R3-R4

  In a group III nitride compound semiconductor optical device, an electrode layer made of a highly reflective metal may be used on one side of a laminated group III nitride compound semiconductor layer. From a reflective surface, an electrode made of, for example, silver (Ag) is preferable. In addition, an electrode made of rhodium (Rh) is preferable from the viewpoints of adhesion and ohmic properties to the group III nitride compound semiconductor layer.

  As a matter of fact, it is not possible to satisfy all the reflectivity for green, blue or ultraviolet light, and the adhesion and ohmic property with the group III nitride compound semiconductor layer with one metal. For example, silver (Ag) easily undergoes so-called migration, and deterioration of element characteristics during use, particularly disconnection and short-circuiting may occur frequently. Further, an electrode made of rhodium (Rh) does not necessarily have high reflectivity for green, blue, or ultraviolet light when compared with other metals.

As a highly reflective metal, for example, there is aluminum (Al), but adhesion and ohmic property with the group III nitride compound semiconductor layer are not necessarily good. Therefore, for example, indium tin oxide (ITO), which is an electrode with good adhesion and high translucency, is formed between them, and light absorption is ensured while ensuring adhesion and ohmic properties with the group III nitride compound semiconductor layer. It is conceivable to reflect the light with a highly reflective metal layer such as aluminum (Al). However, when an aluminum (Al) film is formed directly on a translucent electrode made of, for example, ITO formed on a group III nitride compound semiconductor layer, aluminum (Al) is very easy to form an oxide, and Since alumina (Al ₂ O ₃ ) is insulative, good electrode characteristics cannot be obtained. Accordingly, an object of the present invention is to provide an electrode configuration of a semiconductor element having a conductive oxide layer and a metal layer in which the oxide serves as an insulator as at least one of the electrode layers.

The invention according to claim 1, a conductive oxide layer, in the method for manufacturing a semiconductor optical device having a structure of oxide insulator at a the light reflective metal layer and a conductive electrode layer, the growth substrate On top, there is an n layer composed of an n-type group III nitride compound semiconductor, a light emitting layer, and a p layer, and the uppermost layer is a p layer composed of a p-type group III nitride compound semiconductor. Growing a plurality of group III nitride compound semiconductor layers, forming a conductive and translucent oxide layer on the p layer, and translucent dielectric on the oxide layer The body layer is uniformly formed, and a hole portion in which the oxide layer is exposed is formed in the dielectric layer, and the metal that is not oxidized even when contacting the oxide layer in the hole portion or the oxide is not an insulator Metal is filled so that it is also formed on the dielectric layer around the hole to form a connection part, and light reflection is uniformly applied on the dielectric layer and the connection part. Forming a metal layer, to form a uniform multilayered metal layer on the metal layer, and joining the multi-layer metal layer and the supporting substrate, the growth substrate is lifted off, the n-layer exposed by the lift-off, forming an electrode This is a method for manufacturing a semiconductor optical device .
It is desirable that the positive and negative electrodes are formed above and below the light emitting region or the light receiving region with the light emitting region or the light receiving region interposed therebetween .

The invention according to claim 2 is characterized in that the oxide layer is made of indium tin oxide (ITO). The invention according to claim 3 is characterized in that the metal layer is made of aluminum (Al).

The invention according to claim 4 is characterized in that the connecting portion is made of iridium (Ir), platinum (Pt), rhodium (Rh), or an alloy thereof, or a multilayer thereof. In the invention according to claim 5 , the connecting portion is made of cobalt (Co), chromium (Cr), copper (Cu), iron (Fe), manganese (Mn), molybdenum (Mo), nickel (Ni), tin (Sn). ), Tantalum (Ta), titanium (Ti), vanadium (V), tungsten (W), zinc (Zn), zirconium (Zr), an alloy thereof, or a multilayer thereof And

The invention according to claim 6 is characterized in that the connecting portion is formed of conductive metal nitride or metal carbide. The invention according to claim 7 is characterized in that the connecting portion is formed of a nitride or carbide of hafnium (Hf), tantalum (Ta), titanium (Ti), tungsten (W), or zirconium (Zr). To do.

When a conductive oxide layer is formed directly on a semiconductor layer, a contact electrode with good adhesion and ohmic properties is obtained. Since the oxide layer and the metal layer are electrically connected by the dielectric layer having a hole here and the connecting portion filled in the hole, the oxide layer and the metal layer are respectively formed over the entire electrode region. However, it is possible to separate them while electrically connecting them. Thereby, since the constituent element of the metal layer does not come into contact with the oxide layer, it is possible to use a metal layer in which an oxide becomes an insulator . This arrangement, Ri your suitable Group III nitride compound semiconductor optical device, in particular sandwich the light-emitting area or the light receiving region, which is positive and negative electrodes are formed above and below of the light emitting area or the light receiving region It is effective for. That is, as the metal layer, an oxide serves as an insulator, but a highly reflective metal such as aluminum can be used. Thereby, about the other electrode side, it becomes possible to ensure a light extraction area | region and a light acquisition area | region by making the said electrode into a window frame shape . It is also effective to apply the present invention to a structure in which positive and negative electrodes are provided on one side of an insulating substrate, for example, a positive electrode of a flip chip type III-nitride compound semiconductor optical device .

The conductive material for forming the connection portion is a metal that is not oxidized by contact with an oxide layer such as iridium (Ir), platinum (Pt), or rhodium (Rh), or cobalt (Co) or chromium (Cr). , Copper (Cu), iron (Fe), manganese (Mn), molybdenum (Mo), nickel (Ni), tin (Sn), tantalum (Ta), titanium (Ti), vanadium (V), tungsten (W) Even when oxidized, a metal whose oxide is not an insulator, such as zinc (Zn) or zirconium (Zr), can be used. At this time, an alloy or a multilayer of the metal may be used. In the case of the multilayer, the layer in contact with the oxide layer may be such a metal . Alternatively, a non-oxidized conductive material such as a nitride or carbide of hafnium (Hf), tantalum (Ta), titanium (Ti), tungsten (W), or zirconium (Zr) may be used .

As the oxide electrode, in addition to an indium tin oxide electrode (ITO electrode), any oxide electrode can be used. As the dielectric layer, SiO ₂ , SiO _x , Al ₂ O ₃ , MgO, SiN _x or any other compound or a multilayer thereof can be used. For the connecting portion, any material may be used as long as no oxide is generated in contact with the oxide electrode or an insulator is not formed. As the highly reflective metal whose oxide becomes an insulator, any metal other than aluminum (Al) may be used.

  The present invention can be applied to any semiconductor element, particularly a group III nitride compound semiconductor optical element, and in particular to a light emitting element having a light extraction region and a light receiving element having a light extraction region. In an element having a support substrate, a window frame-like electrode is preferably formed directly or through a light-transmitting electrode on a semiconductor layer that is not in contact with the substrate, for example, a group III nitride compound semiconductor layer. When positive and negative electrodes are positioned above and below the light emitting region, it is desirable to use a conductive substrate as the support substrate. Alternatively, it is also effective to apply the present invention to a configuration in which an insulating substrate is used and both positive and negative electrodes are provided on one side, for example, a positive electrode of a flip chip type group III nitride compound semiconductor optical device.

  For example, when the thin film portion of GaN is melted and decomposed by laser irradiation and separated from the epitaxial growth substrate, a laser having a wavelength shorter than 365 nm is suitable, a YAG laser having a wavelength of 365 nm, 266 nm, a XeCl laser having a wavelength of 308 nm, An ArF laser and KrF having a wavelength of 248 nm are preferably used. For example, if the chips are arranged on the wafer every 500 μm, 4 × 4 2 mm square laser irradiations or 6 × 6 3 mm square laser irradiations are used. Then, it is preferable that the boundary between “laser irradiated” and “unirradiated” does not cross each chip.

  For example, the group III nitride compound semiconductor multilayer structure is desirably formed by epitaxial growth. However, the buffer layer formed prior to the epitaxial growth may be formed by, for example, sputtering or other methods without depending on the epitaxial growth. The details of the epitaxial growth method, the epitaxial growth substrate, the structure of each layer, the structure of the functional layer such as the light emitting layer, the other structure method, and the handling method after dividing the element may not be described at all in the following embodiments. It means that the present invention can include any known configuration at the time of filing or forming a desired semiconductor element by arbitrarily combining a plurality of technical configurations.

  Group III nitride compounds, in a narrow sense, include quaternary semiconductors including arbitrary and binary AlGaInN compositions, and donor or acceptor impurities for imparting conductivity to them. In general, however, semiconductors using other groups III and V in addition or in part, or semiconductors added with any element to give other functions are excluded. It is not a thing.

  The electrode according to the present invention is as described above. For example, when the present invention is applied to the positive electrode, any conductive material can be used for the negative electrode. In the case where the side on which the negative electrode is formed is used as a light extraction region or a light extraction region, a light-transmitting electrode can be formed, and indium tin oxide, indium titanium oxide, or other oxide electrodes can be used.

  Solder can be suitably used to join the epitaxially grown wafer and the support substrate, and a multilayer metal film may be formed on the joining side surface of the support substrate or epitaxially grown wafer as needed depending on the solder component.

  The present invention is characterized by the electrode configuration, and as described repeatedly, any other known configuration and combination of known techniques can be used for other configurations.

  FIG. A to FIG. K is a process diagram (cross-sectional view) showing a method for manufacturing a group III nitride compound semiconductor light emitting device 1000 according to a specific example of the present invention. In addition, FIG. K shows a diagram substantially corresponding to a one-chip group III nitride compound semiconductor light-emitting device 1000. FIG. A to FIG. J also shows a drawing corresponding to a cross-sectional view of one chip. However, FIG. A to FIG. J is an enlarged representation of a “part” of a single wafer, etc. FIG. K also means an enlarged cross-sectional view of a “part” of a single wafer or the like in a state before dicing into chips.

First, a sapphire substrate 100 is prepared, and a group III nitride compound semiconductor layer is formed by normal epitaxial growth (FIG. 1.A). FIG. In A, a group III nitride compound semiconductor layer stacked as an n-type layer 11, a p-type layer 12, and a light emitting region L is shown in a simplified manner. FIG. A to FIG. In K, the n-type layer 11 and the p-type layer 12 are described as two layers that are in contact with each other in the light emitting region L indicated by a broken line, but these are not described in detail of the laminated structure. Actually, even if the sapphire substrate 100 includes, for example, a buffer layer, a high concentration n ⁺ layer made of GaN doped with silicon, a low concentration n layer made of GaN, and an n-AlGaN cladding layer, FIG. A to FIG. In K, the n-type layer 11 is represented. Similarly, even if a p-AlGaN cladding layer doped with magnesium, a low-concentration p layer made of GaN, and a high-concentration p ⁺ layer made of GaN are formed, FIG. A to FIG. In K, the p-type layer 12 is represented. The light emitting region L is represented by a broken line representing both the junction surface in the case of a pn junction and a light emitting layer having a multiple quantum well structure (usually, the well layer is an undoped layer). It does not mean the “interface between the mold layer 11 and the p-type layer 12”. However, the “plane of the light emitting region” is a plane existing in the vicinity of the broken line indicated by the light emitting region L. Note that the p-type layer 12 is “a layer containing a p-type impurity but not reduced in resistance” before the “heat treatment under nitrogen (N ₂ ) atmosphere” described below, and the “nitrogen ( After the “N ₂ ) heat treatment under atmosphere”, it is a p-type layer with a low resistance in the usual sense.

Next, a translucent electrode 121-t made of indium tin oxide (ITO) having a thickness of 300 nm is formed on the entire surface of the p-type layer 12 by electron beam evaporation. Thereafter, heat treatment is performed at 700 ° C. for 5 minutes in an N ₂ atmosphere to reduce the resistance of the p-type layer 12 and to reduce the contact resistance between the p-type layer 12 and the ITO electrode 121-t. . Next, a dielectric layer 150 made of silicon nitride (SiN _x ) having a thickness of 100 nm is formed on the entire surface of the ITO electrode 121-t (FIG. 1.B).

Next, a hole H is formed in the dielectric layer 150 made of SiN _x by dry etching by photolithography using a resist film (not shown). As will be described later, the shape and position of the hole H, that is, the shape and position of the connecting portion 121-c made of nickel (Ni) are related to the shape and position of the n-electrode 130 made of a multilayer metal film to be formed later. In FIG. 5, the orthogonal projections of the two projected on the “plane of the light emitting region L” are not overlapped. In the present example, the hole H was formed in a stripe shape having a width of about 20 μm and an interval of the hole H of 80 to 100 μm with respect to the square group III nitride compound semiconductor light emitting device 1000 having a side of 400 to 500 μm. Thereafter, the resist film is removed (FIG. 1.C).

Next, in order to form the connection part 121-c made of nickel (Ni) in the hole H, a resist film (not shown) is formed. In this resist film, a hole larger than the hole is formed above the hole H of the dielectric layer 150 made of SiN _x . Thus, nickel (Ni) is formed by resistance heating vapor deposition in the hole H of the dielectric layer 150 made of SiN _x and the hole of the resist film formed thereon. At this time, nickel (Ni) was deposited until the hole H of the dielectric layer 150 made of SiN _x was filled, and a 20 nm thick hook-like portion was formed on the dielectric layer 150. In this way, the resist film was removed, and a connection portion 121-c made of nickel (Ni) filling the hole H of the dielectric layer 150 made of SiN _x was formed (FIG. 1.D).

Next, the highly reflective metal layer 121-r made of aluminum (Al) having a thickness of 300 nm is formed on the dielectric layer 150 made of SiN _x having the connection part 121-c made of nickel (Ni) in the hole H. Is formed by vapor deposition (FIG. 1.E). Thus, the group III nitride compound semiconductor layer is formed by the translucent electrode 121-t made of ITO, the connection part 121-c made of nickel (Ni), and the highly reflective metal layer 121-r made of aluminum (Al). A multiple p-electrode is formed that has high adhesion to the surface and does not absorb light and highly reflects light. Note that the role of the dielectric layer 150 made of SiN _x having the connection part 121-c made of nickel (Ni) in the hole H is that aluminum (Al) and ITO are not in direct contact with each other, thereby oxidizing the aluminum (Al). It is to prevent deterioration of the electrode characteristics due to.

  Next, a multilayer metal film is formed by vapor deposition in the following order. A titanium (Ti) layer 122 having a thickness of 50 nm, a nickel (Ni) layer 123 having a thickness of 500 nm, and a gold (Au) layer 124 having a thickness of 50 nm. Thus, FIG. The layer structure is F. The functions of the titanium (Ti) layer 122, the nickel (Ni) layer 123, and the gold (Au) layer 124 are as follows. In providing the gold tin solder (Au-20Sn) 51 of 20% tin, a gold (Au) layer 124 is formed as an alloying layer with the gold tin solder (Au-20Sn) 51, and aluminum (Al) of tin (Sn). The nickel (Ni) layer 123 is used as a layer for preventing diffusion to the highly reflective metal layer 121-r made of, and the adhesion between the nickel (Ni) layer 123 and the highly reflective metal layer 121-r made of aluminum (Al) In order to improve the above, a titanium (Ti) layer 122 is provided.

  Next, a gold tin solder (Au-20Sn) 51 of 20% tin is formed on the gold (Au) layer 124 to a thickness of 1500 nm (1.G).

Next, an n-type silicon substrate 200 is prepared, and a conductive multilayer film is formed on both surfaces by vapor deposition or the like in the following order. The front side layers are denoted by reference numerals 221 to 224, and the back side layers are denoted by reference numerals 231 to 244. Titanium nitride (TiN) layers 221 and 231 having a thickness of 30 nm, titanium (Ti) layers 222 and 232 having a thickness of 50 nm, nickel (Ni) layers 223 and 233 having a thickness of 500 nm, and gold (Au) layer 224 having a thickness of 50 nm And 234. The titanium nitride (TiN) layers 221 and 231 are selected from the viewpoint of low contact resistance with the n-type silicon substrate 200. The titanium (Ti) layers 222 and 232, nickel (Ni) layers 223 and 233, gold The functions of the (Au) layers 224 and 234 are exactly the same as the functions of the titanium (Ti) layer 122, the nickel (Ni) layer 123, and the gold (Au) layer 124 described above. On the gold (Au) layer 224 that is the uppermost layer of the conductive multilayer film on the surface side formed on the n-type silicon substrate 200, a 20% tin gold tin solder (Au-20Sn) 52 is formed to a thickness of 1500 nm, FIG. A group III nitride compound semiconductor light emitting device wafer in which a gold tin solder (Au-20Sn) 51 of 20% tin of G is formed to a thickness of 1500 nm is bonded to the surfaces on which the gold tin solder (Au-20Sn) is formed ( Figure 1.H). Thus, the two wafers are united by hot pressing at 300 ° C. and 30 kg weight / cm ² (2.94 MPa). Hereinafter, gold tin solder (Au-20Sn) is shown as an integrated layer 50 (FIG. 1.I).

The integrated wafer is irradiated with a 248 nm KrF high-power pulse laser from the sapphire substrate 100 side. The irradiation conditions are 0.7 J / cm ² or more, a pulse width of 25 ns (nanoseconds), an irradiation area of 2 mm square or 3 mm square, and for each irradiation, the outer periphery of the laser irradiation area should not cross “one chip”. good. By this laser irradiation, the interface 11f of the n-type layer 11 (GaN layer) closest to the sapphire substrate 100 is melted into a thin film and decomposed into gallium (Ga) droplets and nitrogen (N ₂ ). After that, the sapphire substrate 100 is removed from the integrated wafer by lift-off (FIG. 1.J). Thereafter, the exposed surface of the n-type layer 11 is washed with diluted hydrochloric acid to remove gallium (Ga) droplets adhering to the surface.

  Next, a resist film (not shown) is formed, and an n-electrode 130 made of a multilayer metal film is formed by vapor deposition in the following order in the hole of the resist film. As will be described later, the hole portion of the resist film was formed in a “window frame shape” so that the shape of the connection portion 121-c made of nickel (Ni) and the orthogonal projection do not overlap each other. Next, on the n-type layer 11 (hole portion of the resist film), a vanadium (V) layer having a thickness of 15 nm, an aluminum (Al) layer having a thickness of 150 nm, a titanium (Ti) layer having a thickness of 30 nm, and a thickness. A 500 nm nickel (Ni) layer and a 500 nm thick gold (Au) layer. Thereafter, the resist is lifted off and removed, whereby the n-electrode 130 made of the multilayer metal film in the hole of the resist film remains, and the metal film in the other region is removed together with the resist. Thus, the n-type silicon substrate 200 having the conductive multilayer film formed on both sides is used as a support substrate, the p-side transparent electrode 121-t made of ITO, the connection part 121-c made of nickel (Ni), aluminum (Al And a highly reflective metal layer 121-r, and is electrically connected to the n-type silicon substrate 200 with a gold-tin solder (Au-20Sn) 50 via a multilayer metal film. A compound semiconductor light emitting device 1000 was formed (FIG. 1.K). The group III nitride compound semiconductor light emitting device 1000 is a light emitting device in which a region where the n-electrode 130 made of a multilayer metal film formed in a “window frame shape” is not formed is a light extraction region.

  Thereafter, it is divided into arbitrary elements by an arbitrary method. For example, half cutting is performed with a dicing blade, and braking is performed for division. In the half cut, the silicon substrate 200 is cut to some extent from the back surface 200B of the silicon substrate 200. On the other hand, the n-type layer 11 and the p-type layer 12 that are epitaxial layers may be separated by cutting at least the n-type layer 11 and the p-type layer 12 that are the epitaxial layers in the vicinity of the dividing line. The cutting need not reach the surface 200F of the silicon substrate 200.

[About the planar shape of the hole H of the dielectric layer 150 filled with the n electrode 130 and the connection part 121-c]
It is desirable that the orthogonal projections of the n-electrode 130 and the planar shape of the hole H of the dielectric layer 150 filled with the connection portion 121-c, that is, the plane of the light emitting region L do not overlap, and the orthogonal projection is It is preferable not to be less than a certain distance at any position. In this case, the “certain distance” is preferably set to a distance of about the total film thickness of the n-type layer 11 and the p-type layer 12, or a multiple of the distance. For example, if the total film thickness of the n-type layer 11 and the p-type layer 12 is 5 μm, the two orthogonal projections are preferably separated by 5 μm or more at any position, more preferably 10 μm or more, More preferably, the distance is 20 μm or more.

  In the above embodiment, the n-electrode 130 may not be formed directly on the n-type layer 11, but a window frame-shaped n-electrode may be further formed after forming a translucent electrode, for example.

FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000. FIG. 3 is a step view showing one step of a method for manufacturing a group III nitride compound semiconductor light emitting device 1000.

1000: Group III nitride compound semiconductor light emitting device 100: Sapphire substrate (epitaxial growth substrate)
11: n-type group III nitride compound semiconductor layer 12: p-type group III nitride compound semiconductor layer L: Light emitting region 121-t: Translucent electrode made of ITO 121-c: Connection portion 121- made of Ni r: highly reflective metal layer made of Al 200: silicon substrate (support substrate)
221, 231: TiN layer 122, 222, 232: Ti layer 123, 223, 233: Ni layer 124, 224, 234: Au layer 130: n-electrode made of multilayer metal film 50, 51, 52: Au-20Sn solder layer 150: Dielectric layer made of SiN _x H: Hole of dielectric layer

Claims (7)

A conductive oxide layer, oxides in the method for manufacturing a semiconductor optical device having a an insulating material light reflecting metal layer,
On the growth substrate, there is an n layer made of an n-type group III nitride compound semiconductor, a light emitting layer, and a p layer, and the uppermost layer is a p layer made of a p-type group III nitride compound semiconductor. Growing a plurality of Group III nitride compound semiconductor layers,
Forming the oxide layer that is conductive and translucent on the p layer;
A dielectric layer that is translucent is uniformly formed on the oxide layer,
Forming a hole in which the oxide layer is exposed in the dielectric layer;
The hole is filled with a metal that is not oxidized even when it comes into contact with the oxide layer, or a metal whose oxide is not an insulator, so that it is also formed on the dielectric layer around the hole. To form a connection,
Uniformly forming the light-reflective metal layer on the dielectric layer and the connecting portion;
Forming a multilayer metal layer uniformly on the metal layer;
Bonding the multilayer metal layer and the support substrate;
Lift off the growth substrate;
The method of manufacturing a semiconductor optical device, characterized in that the n layer exposed by the lift-off to form the electrodes. The method of manufacturing a semiconductor optical device according to claim 1 , wherein the oxide layer is made of indium tin oxide (ITO) . 3. The method of manufacturing a semiconductor optical device according to claim 1, wherein the metal layer is made of aluminum (Al) . The connection portion is made of iridium (Ir), platinum (Pt), rhodium (Rh), an alloy thereof, or a multilayer thereof . 2. A method for producing a semiconductor optical device according to item 1 . The connecting portion includes cobalt (Co), chromium (Cr), copper (Cu), iron (Fe), manganese (Mn), molybdenum (Mo), nickel (Ni), tin (Sn), tantalum (Ta), titanium (Ti), vanadium (V), tungsten (W), zinc (Zn), or zirconium (Zr), or alloys thereof, or claims 1 to, characterized in that consisting of multiple layers 4. The method for producing a semiconductor optical device according to any one of items 3 . The method for manufacturing a semiconductor optical device according to claim 1, wherein the connection portion is formed of a conductive metal nitride or a metal carbide . It said connection unit, hafnium (Hf), tantalum (Ta), titanium (Ti), tungsten (W) or zirconium according to claim 6, characterized in that it is formed from a nitride or carbide (Zr) A method for manufacturing a semiconductor optical device.

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