JP2006186036A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having high reliability wiring capable of restraining any void from happening in a via hole bottom in a semiconductor device including embedded wiring using a conductive film such as copper. <P>SOLUTION: The semiconductor device comprises a first wiring layer 13 formed in a first insulating film 11, a second wiring layer formed in a second insulating film 16 formed on the first insulating film 11, and a via plug 18 formed in the second insulating film 16 for connecting the first wiring layer 13 and the second wiring layer. The first wiring layer 13 has a width of ≥1 μm, and an insulating dummy region 14 is formed in the first wiring layer 13 within 0.5 μm from a connection between the via plug 18 and the first wiring layer 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a buried wiring using a conductive film such as copper.

  In recent years, with the miniaturization of semiconductor devices, it is necessary to reduce wiring resistance, and buried wiring using a conductive film such as copper has become an indispensable technology. The embedded wiring is suitable for wiring formation using a metal that is difficult to dry-etch, such as copper, and there is an advantage that a via plug for connecting the upper and lower wiring layers can be formed of the same kind of metal as the wiring.

  FIG. 18 is a cross-sectional view of a conventional semiconductor device having embedded wiring.

  In FIG. 18, 21 is a first insulating film on which a first wiring layer is formed, 22 is a barrier metal film made of a single layer or a laminated film of Ta or TaN in the first wiring layer, and 23 is a first wiring made of a copper film. 24, an insulating film for preventing copper diffusion of the first wiring layer 23, 25 a second insulating film on which a via hole and a second wiring layer are formed, and 26 a single layer or a laminated film of Ta or TaN in the via hole A barrier metal film 27 is a via plug made of a copper film embedded in the via hole. The second wiring layer (not shown) is made of a copper film like the via plug 27 and is formed on the second insulating film 25 via a barrier metal film made of a single layer or a stacked layer of Ta or TaN. The

  A via plug 27 connecting the first wiring layer 23 and the second wiring layer is formed in a copper film in a via hole formed by dry etching on the first wiring layer 23 so as to partially penetrate the second insulating film 25. It is formed by embedding a conductive film made of As described above, when the via hole is formed by dry etching, the surface of the first wiring layer 23 is exposed to the etching gas, so that a minute recess is formed on the surface of the first wiring layer 23. When the via hole is filled with the conductive film, the concave portion is very small and is not completely filled with the conductive film, which may lead to insufficient coverage of the conductive film filling the via hole or undercut. As a result, in the wiring layer in which the coverage of the conductive film is insufficient or the undercut occurs, there is a problem that the reliability of the device is lowered due to a decrease in the adhesion strength between the conductive film and the insulating film. In particular, when the width of the first wiring layer 23 is larger than the diameter of the via hole, the surface of the first wiring layer 23 is exposed to the etching gas, and the influence spreads to a portion other than the exposed portion. It is formed so as to cover the periphery of the bottom of the hole. If a force is applied in the direction in which the via plug 27 is pulled out due to the expansion and contraction effect of the copper film by the heat treatment in the subsequent diffusion process, a void 28 is generated at the bottom of the via plug and the reliability of the wiring is lowered.

  As shown in FIG. 3, in the via hole reliability evaluation of the copper wiring, it can be seen that the reliability decreases as the width of the first wiring layer 23 increases. As the width of the first wiring layer 23 connecting the via hole is increased, the force for pulling out the plug metal of the via plug 27 is increased accordingly, and the generation of the void 28 at the bottom of the via plug is accelerated.

  Therefore, a method for improving the reliability of the wiring related to the via hole has been proposed. Specifically, as a countermeasure against undercut that can be formed at the bottom of the via hole, in Patent Document 1, an insulating film layer serving as a sacrificial layer is formed in advance before dry etching for hole formation. There has been proposed a method of removing the sacrificial layer after the occurrence of undercut.

  Hereinafter, this method will be described with reference to FIG.

  In FIG. 19, 31 is a silicon of a base metal film for forming a via hole, 32 is a silicon alloy layer alloyed with a metal such as nickel in order to lower the contact resistance in the base metal film, and 33 is a via hole. An insulating film layer to be formed, 34 is a stopper film (for example, a silicon nitride film) for removing a sacrificial film for reducing undercut at the bottom of the via hole, 35 is a via hole, and 36 is for reducing undercut. A sacrificial film (for example, silicon oxide film) 37 is an undercut at the bottom of the via hole generated by CDE (Chemical Dry Etching) processing for reducing contact resistance after via hole etching.

  First, as shown in FIG. 19A, a via hole 35 for contact with the silicon alloy layer 32 is formed by dry etching, and then a silicon nitride film is deposited and etched back by dry etching on the entire surface. A stopper film 34 for removing the film 36 is formed.

  Next, as shown in FIG. 19B, a silicon oxide film is deposited and etched back by whole surface dry etching to form a sacrificial film.

  Thereafter, as shown in FIG. 19C, when the CDE process for reducing the contact resistance of the via hole 35 is performed, an undercut 37 is generated at the bottom of the via hole.

Finally, as shown in FIG. 19D, when the sacrificial film 36 is removed by wet etching for etching the silicon oxide film, the undercut 37 is also removed at the same time, and the via hole 35 without the undercut is obtained.
Japanese Patent Laid-Open No. 10-41389

  However, the method shown in FIG. 19 requires steps for depositing and etching back the stopper film 34 when removing the sacrificial film 36, depositing and etching back the sacrificial film 36, and finally removing the sacrificial film 36. There is a problem that the manufacturing process becomes complicated.

  An object of the present invention is to provide a semiconductor device capable of preventing a decrease in device reliability even if undercut occurs without causing complication of a manufacturing process.

  The semiconductor device of the present invention includes a first wiring layer formed in the first insulating film, a second wiring layer formed in the second insulating film formed on the first insulating film, and the second wiring layer. A via plug formed in an insulating film and connecting the first wiring layer and the second wiring layer; the first wiring layer having a width of 1 μm or more; and the connection between the via plug and the first wiring layer An insulating dummy region is formed in the first wiring layer within 0.5 μm from the portion.

  The semiconductor device of the present invention includes a first wiring layer formed in the first insulating film, a second wiring layer formed in the second insulating film formed on the first insulating film, A via plug formed in a second insulating film and connecting the first wiring layer and the second wiring layer, and the via plug has a width larger than the diameter of the via plug; Insulating dummy regions are formed in the first wiring layer in contact with the outer periphery of the connection portion between the first wiring layer and the first wiring layer.

  According to the semiconductor device of the present invention, by forming an insulating dummy region in the first wiring layer, the surface of the first wiring layer is etched when the width of the first wiring layer is larger than the diameter of the via hole. Insulating dummy area prevents the effects of exposure to gas and etchant from spreading to parts other than the exposed areas, and prevents undercuts from being formed around the bottom of the via hole. it can. Even when the insulating dummy region and the second insulating film are in close contact with each other and the width of the first wiring layer is wide, the first insulating film on which the first wiring layer is formed, the second wiring layer, and the via plug Adhesiveness with the second insulating film formed with is improved.

  In the present invention, when a via hole is connected to a wide first wiring layer, by providing an insulating dummy region in the first wiring layer, voids at the bottom of the via hole can be suppressed. A highly reliable semiconductor device can be provided. Further, even when there is no undercut at the bottom of the via hole, the adhesion is improved by the insulating dummy region, and the reliability of the semiconductor device can be improved.

(Embodiment 1)
A first embodiment of the present invention will be described with reference to FIGS.

  1 is a cross-sectional view of the semiconductor device, FIG. 2 is a partial perspective view of the semiconductor device, FIG. 3 is a graph showing a reliability evaluation result of the semiconductor device, and FIGS.

  In the figure, 11 is a first insulating film on which a first wiring layer is formed, 12 is a barrier metal film made of a single layer or a laminated film of Ta or TaN in the first wiring layer, and 13 is a first wiring layer made of a copper film. , 14 is a dummy region made of an insulating film arranged so as to sandwich a via hole in the first wiring layer 13, 15 is an insulating film for preventing copper diffusion of the first wiring layer 13, and 16 is a via hole and a second wiring. A second insulating film in which a layer is formed, 17 is a barrier metal film made of a single layer or a laminated film of Ta or TaN in a via hole, and 18 is a via plug made of a copper film. The second wiring layer (not shown) is made of a copper film like the via plug 18 and is formed on the second insulating film 16 via a barrier metal film made of a single layer or a stacked layer of Ta or TaN. The

  The wiring shown in FIG. 1 is formed by the following damascene wiring forming method.

  First, a groove for forming the first wiring layer 13 is formed in the first insulating film 11 using lithography or an etching technique. At this time, a groove is formed so that the first insulating film 11 remains as a dummy region 14 in the vicinity of the via plug 18 in the first wiring layer 13 is formed. Next, a barrier metal film 12 and a copper film 13 for forming the first wiring layer 13 are deposited, and an excess film is removed by a CMP (Chemical Mechanical Polishing) method. An insulating film 15 for preventing copper diffusion is deposited so as to cover the first insulating film 11 and the first wiring layer 13, and then a second insulating film 16 for forming the second wiring layer and the via plug 18 is deposited. To do. Grooves and holes for forming the second wiring layer and the via plug 18 are formed in the insulating film 15 for preventing copper diffusion and the second insulating film 16 by lithography or etching technique. Next, a barrier metal film 17 and a copper film 18 for forming the second wiring layer and the via plug 18 are deposited, and an excess film is removed by a CMP method. By repeating these methods several times, a multi-layer damascene wiring can be formed.

  Next, the reliability evaluation results shown in FIG. 3 will be described. In the graph of FIG. 3, the horizontal axis represents the width dimension (μm) of the first wiring layer 13 and the vertical axis represents the average failure time (au). As an example, the diameter D of the via hole is 0.2 μm. The reliability evaluation is shown. In addition, a.u. means an arbitrary unit (arbitrary unit), and the vertical axis is expressed by relative evaluation because it depends greatly on measurement conditions and process conditions.

  From the reliability evaluation results shown in FIG. 3, it can be seen that when the width of the first wiring layer 13 is 1 μm or less, it is a desirable wiring width that does not deteriorate the reliability by 10% or more. That is, the leftmost plot in the graph plot is data with a wiring width of 0.2 μm, which is the most reliable structure. When the wiring width is 1 μm (second plot from the left), the failure time is about 10% worse than 0.2 μm, but when the wiring width is less than 10 μm, it is not worse than 10%.

  This is an example of the result of evaluating the reliability. However, when a void at the bottom of the via hole is generated, the yield may be directly reduced. Therefore, the dummy may be formed so that the distance T from the via hole to the dummy region 14 is 0.4 μm or less when the width W of the first wiring layer 13 is 1 μm or more. Note that the distance T of 0.4 μm or less is 0.4 μm because the wiring is 1 μm wide with respect to the 0.2 μm via, and the occurrence of defects is due to the undercut at the bottom of the via hole. The relationship that the width W is 1 μm or more and the distance T is 0.4 μm or less is established without greatly depending on the via hole diameter.

  4 to 9 show various examples of the dummy area 14. In any example, the diameter D of the via hole is 0.2 μm, the width W of the first wiring layer 13 is 1 μm or more, and the distance T from the via hole to the dummy region 14 is 0.4 μm or less.

  In the example of FIG. 4, the dummy region 14 is provided so as to sandwich the via plug 18 when the via plug 18 is arranged at a ratio of at least one via plug in the range of 1 μm × 1 μm.

  In the example of FIG. 5, a U-shaped dummy region 14 is provided so as to surround the via plug 18, and the via plug 18 is surrounded on three sides, so that the reliability can be further improved.

  In the example of FIG. 6, when there are a plurality of via plugs 18 and are arranged in a line such that the distance S between adjacent via plugs 18 is 0.5 μm or less, a plurality of vias arranged in a line are arranged. A pair of dummy regions 14 are provided along both sides of the via plug 18 so as to sandwich the plug 18 together.

  In the example of FIG. 7, a plurality of via plugs 18 are arranged in a row, and dummy regions 14 are provided so as to sandwich each via plug 18 between and between the via plugs 18. Increase can be suppressed.

  In the example of FIG. 8, a plurality of via plugs 18 are arranged in a line, the dummy region 14 is formed in a U shape with respect to the via plug 18, and a U shape is formed in the adjacent via plug 18. The dummy areas 14 are alternately installed in opposite directions, and the reliability can be further improved.

  In the example of FIG. 9, when a plurality of via plugs 18 are arranged both vertically and horizontally so that the distance S between adjacent via plugs 18 is 0.5 μm or less, they are parallel to the column direction or the row direction. A dummy region 14 corresponding to the length of the via plug 18 is provided.

  The width of the dummy region 14 is most desirably the minimum size in the semiconductor manufacturing process, and the length of the dummy region 14 only needs to be secured to the length where the corresponding via plug 18 is disposed.

  According to the semiconductor device configured as described above, when the width of the first wiring layer 13 is widened, the dummy region 14 is provided so as to sandwich the via plug 18 in the first wiring layer 13, thereby moving the bottom of the via hole. The generation of voids can be suppressed, and the deterioration of device reliability can be prevented without complicating the manufacturing process.

  Further, when the width of the first wiring layer 13 is increased, a dummy region 14 is provided so as to sandwich the via plug 18 in the first wiring layer 13 to improve the adhesion with the insulating film 15 for preventing copper diffusion. As a result, it is possible to suppress the pull-out of the plug metal of the via plug 18 and suppress the generation of voids at the bottom of the via hole.

(Embodiment 2)
A second embodiment of the present invention will be described with reference to FIGS.

  10 is a cross-sectional view of the semiconductor device, FIG. 11 is a partial perspective view of the semiconductor device, and FIGS. 12 to 17 are wiring top views of the semiconductor device. In addition, the same code | symbol is attached | subjected to the same part as Embodiment 1, and the description is abbreviate | omitted.

  In the second embodiment, when the width of the first wiring layer 13 is larger than the diameter of the via plug 18, the insulating dummy region 14 is in contact with the outer periphery of the connection portion between the via plug 18 and the first wiring layer 13. Is formed.

  The wiring shown in FIG. 10 is formed in the same manner as the damascene wiring forming method in the example of FIG.

  12 to 17 show various examples of the dummy area 14. In any example, the via hole diameter D is 0.2 μm, and the width W of the first wiring layer 13 is 1 μm or more.

  In the example of FIG. 12, when the via plug 18 is arranged at a ratio of at least 1 μm × 1 μm, the dummy region 14 is provided in contact with the outer periphery so as to sandwich the via plug 18. is there.

  In the example of FIG. 13, a U-shaped dummy region 14 is provided in contact with the outer periphery so as to surround the via plug 18, and the via plug 18 is surrounded on three sides, so that the reliability can be further improved. .

  In the example of FIG. 14, when there are a plurality of via plugs 18 and are arranged in a line such that the distance S between adjacent via plugs 18 is 0.5 μm or less, for example, a plurality of vias arranged in a line are arranged. A pair of dummy regions 14 are provided along both sides of the via plug 18 so as to be in contact with the outer periphery so as to sandwich the plug 18 in a lump.

  In the example of FIG. 15, a plurality of via plugs 18 are arranged in a row, and a dummy region 14 is provided between the via plugs 18 and at the outermost part so as to contact the outer periphery so as to sandwich each via plug 18. A local increase in current density can be suppressed.

  In the example of FIG. 16, a plurality of via plugs 18 are arranged in a line, the dummy region 14 is formed in U-shape in contact with the outer periphery in a U shape with respect to the via plug 18, and with respect to the adjacent via plug 18. The U-shaped dummy regions 14 are alternately installed in the opposite directions, and the reliability can be further improved.

  In the example of FIG. 17, when a plurality of via plugs 18 are arranged both vertically and horizontally so that the distance S between adjacent via plugs 18 is 0.5 μm or less, they are parallel to the column direction or the row direction. A dummy region 14 corresponding to the length of the via plug 18 is provided in contact with the outer periphery.

  The width of the dummy region is most desirably the minimum size in the semiconductor manufacturing process, and it is sufficient that the length of the dummy region can be ensured by the length in which the corresponding via hole is arranged.

  According to the semiconductor device configured as described above, when the width of the first wiring layer 13 is increased, the dummy region 14 is provided so as to sandwich the via plug 18 in the first wiring layer 13, and the dummy region 14 is formed in the via region. When the plug 18 and the first wiring layer 13 are arranged so as to be in contact with a part of the outer periphery, the undercut at the bottom of the via hole does not surround the entire periphery of the bottom of the via hole, and a void is generated at the bottom of the via hole. The device reliability can be prevented without complicating the manufacturing process.

  Further, when the width of the first wiring layer 13 is increased, a dummy region 14 is provided so as to sandwich the via plug 18 in the first wiring layer 13 to improve the adhesion with the insulating film 15 for preventing copper diffusion. As a result, it is possible to suppress the pull-out of the plug metal of the via plug 18 and suppress the generation of voids at the bottom of the via hole.

  In the first and second embodiments, the dummy region is not limited to being provided so as to sandwich the via plug, and may be provided, for example, in at least one of the four sides of the via plug. Can be improved.

  The present invention is useful when forming a multilayer wiring in a semiconductor device.

Sectional drawing of the semiconductor device in Embodiment 1 of this invention The partial perspective view of the semiconductor device in Embodiment 1 of this invention Graph showing the results of reliability evaluation of semiconductor devices Wiring top view of the semiconductor device in the first embodiment of the present invention Wiring top view of the semiconductor device in the first embodiment of the present invention Wiring top view of the semiconductor device in the first embodiment of the present invention Wiring top view of the semiconductor device in the first embodiment of the present invention Wiring top view of the semiconductor device in the first embodiment of the present invention Wiring top view of the semiconductor device in the first embodiment of the present invention Sectional drawing of the semiconductor device in Embodiment 2 of this invention The partial perspective view of the semiconductor device in Embodiment 2 of this invention Wiring top view of the semiconductor device in the second embodiment of the present invention Wiring top view of the semiconductor device in the second embodiment of the present invention Wiring top view of the semiconductor device in the second embodiment of the present invention Wiring top view of the semiconductor device in the second embodiment of the present invention Wiring top view of the semiconductor device in the second embodiment of the present invention Wiring top view of the semiconductor device in the second embodiment of the present invention Sectional view of a semiconductor device in a conventional example Sectional view of manufacturing process of semiconductor device in conventional example

Explanation of symbols

11 First insulating film 12 Barrier metal film 13 First wiring layer (copper film)
14 Dummy area (insulating film)
15 Insulating film 16 Second insulating film 17 Barrier metal film 18 Via plug (copper film)

Claims (12)

A first wiring layer formed in the first insulating film; a second wiring layer formed in the second insulating film formed on the first insulating film; and the second wiring layer formed in the second insulating film. A via plug connecting the first wiring layer and the second wiring layer;
The first wiring layer has a width of 1 μm or more, and an insulating dummy region is formed in the first wiring layer within 0.5 μm from a connection portion between the via plug and the first wiring layer. Semiconductor device. When the connection portion between the via plug and the first wiring layer is provided at a rate of at least one connection portion within the range of 1 μm ^{2 on} the surface of the first wiring layer, the dummy region is sandwiched between the via plugs. The semiconductor device according to claim 1, wherein the semiconductor device is formed.   The semiconductor device according to claim 2, wherein the dummy region is formed in a U shape so as to sandwich the via plug.   In the case where a plurality of the via plugs are installed on the surface of the first wiring layer and the distance between adjacent via plugs is 0.5 μm or less, the dummy regions are formed so as to sandwich the via plugs, respectively. The semiconductor device according to claim 1.   5. The semiconductor according to claim 4, wherein the plurality of via plugs are arranged in a line, and the dummy regions are formed along both sides of the via plugs so as to sandwich the plurality of via plugs together. apparatus.   The plurality of via plugs are arranged in a line, the dummy regions are formed in a U-shape with respect to each via plug, and the U-shaped dummy regions are alternately arranged with respect to the adjacent via plugs. The semiconductor device according to claim 4, wherein the semiconductor device is installed in a reverse direction. A first wiring layer formed in the first insulating film; a second wiring layer formed in the second insulating film formed on the first insulating film; and the second wiring layer formed in the second insulating film. A via plug connecting the first wiring layer and the second wiring layer;
When the width of the first wiring layer is larger than the diameter of the via plug, an insulating dummy region is formed in the first wiring layer in contact with the outer periphery of the connection portion between the via plug and the first wiring layer. A semiconductor device formed. When the connection portion between the via plug and the first wiring layer is disposed at a ratio of at least one within the range of the surface of the first wiring layer of 1 μm ² , the dummy region is sandwiched between the via plugs. The semiconductor device according to claim 7, wherein the semiconductor device is formed.   The semiconductor device according to claim 8, wherein the dummy region is formed in a U shape so as to sandwich the via plug.   In the case where a plurality of the via plugs are installed on the surface of the first wiring layer and the distance between adjacent via plugs is 0.5 μm or less, the dummy regions are formed so as to sandwich the via plugs, respectively. The semiconductor device according to claim 7.   11. The semiconductor according to claim 10, wherein the plurality of via plugs are arranged in a line, and the dummy regions are formed along both sides of the via plug so as to sandwich the plurality of via plugs together. apparatus.   The plurality of via plugs are arranged in a line, the dummy regions are formed in a U-shape with respect to each via plug, and the U-shaped dummy regions are alternately arranged with respect to the adjacent via plugs. The semiconductor device according to claim 10, wherein the semiconductor device is installed in an opposite direction.

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