JP2005183888A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, which has stable copper wiring because contact resistance between via-hole and metal is small, and to provide a manufacturing method of the semiconductor device. <P>SOLUTION: In a semiconductor device 1, wiring of a first metal 14 of copper is formed below a via-hole 12 by damascene method, further, although metal wiring 15 of copper is formed above via-hole layer, the via-hole 12 and the first metal 14 is tied by the same copper layer without inserting a barrier metal 13, moreover, Cu wiring 16, which is metal wiring at an upper part of the via-hole 12, is connected through the barrier metal 13 in such a manner that a second metal 15 surrounds it. Therefore, a stable via-hole 12 is realized by making the contact resistance low, moreover, the generation of void is prevented, further, it can be strengthened against stress caused by expansion by making the longitudinal direction of the via-hole 12 be the same material. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a stable Cu (copper) wiring having a small contact resistance between a via hole and a metal and a method for manufacturing the semiconductor device.

  Semiconductor devices are becoming increasingly highly integrated and require miniaturization, and wiring is concerned about yields and reduced reliability due to increased resistance and EM (electromigration) degradation. ing.

  Therefore, the wiring has been conventionally changed from AL (aluminum) to Cu (copper). However, since Cu is difficult to form by conventional etching, a method called a damascene method is used in the insulating film. Embedded in.

  Since Cu embedded by the damascene method itself diffuses into the insulating film, a barrier metal such as TiN or Ta is required. This barrier metal is formed by sputtering on the lower and side portions of the groove. The Cu film is usually formed by electrolytic plating, but a Cu seed metal layer is required before plating.

  That is, in the conventional semiconductor device, as shown in FIG. 10, the via hole 103 that connects the lower layer metal 101 and the upper layer metal 102 is formed. However, as shown in FIG. (Void) 104 may occur.

  (1) Cu stress is applied due to the difference in thermal expansion coefficient of Cu / TiN / oxide film.

  (2) Since Cu seed metal is not sufficiently deposited, Cu does not grow by electrolytic plating.

  (3) Since there is a TiN layer in the lower portion of the via, Cu cannot move freely, and voids are generated after annealing.

  When voids are generated in this manner, the generated voids increase the resistance of the via holes, leading to a decrease in yield and reliability of the semiconductor device.

  Therefore, conventionally, a method of forming a wiring in which an intermediate layer such as Zr or the like is embedded in the via hole portion instead of Cu has been proposed in order to improve the adhesion of the via hole lower portion (see Patent Document 1).

  Conventionally, in order to reduce the resistance of the via hole, a semiconductor device has been proposed in which the via hole and the copper of the lower layer metal are directly bonded to each other by etching to a part of the lower layer metal at the time of via etching (patent). Reference 2).

  Furthermore, conventionally, a method of manufacturing a semiconductor device has been proposed in which a via hole is etched to a lower part of a lower layer metal to increase a contact area between the via hole and the lower layer metal, thereby suppressing wiring disconnection and high resistance (patent) Reference 3).

Japanese Patent Laid-Open No. 2001-230219 JP 2002-246467 A Japanese Patent Laid-Open No. 2002-64139

  However, in the above prior art, there is a need for improvement in effectively manufacturing a semiconductor device in which generation of voids is suppressed without forming a barrier metal in the lower portion of the via hole.

  That is, the prior art described in Patent Document 1 has a problem that a new intermediate layer is required in the via hole portion, and contact resistance between the via hole, the lower metal portion, and the upper metal portion is increased.

  Further, in the prior art described in Patent Document 2, the structure in which the via hole and the lower layer wiring are connected by the same copper is the same, but with the current technology, the lower layer metal cannot be etched, and the lower layer metal portion It is difficult to plate Cu in the via hole portion, which is a difficult technique.

  Furthermore, in the prior art described in Patent Document 3, it is difficult to etch Cu in the lower layer wiring, and since the lower layer wiring and the via hole are joined via a barrier metal, high resistance and migration are prevented. It becomes a problem.

  Therefore, the invention according to claim 1 connects the via hole layer and the lower layer metal with the same copper layer without using the barrier metal layer when the copper lower layer metal wiring is formed below the via hole layer by the damascene method. By reducing the contact resistance, a stable via hole is realized, and even if Cu (copper) moves due to heat, it can move relatively freely, preventing the generation of voids, It is another object of the present invention to provide a semiconductor device that is resistant to the stress caused by expansion, with the vertical direction of the via hole being the same material.

  According to the second aspect of the present invention, when the copper metal wiring is formed above the via hole layer by the damascene method, the metal wiring is provided so as to surround the metal wiring on the upper portion of the via hole layer, and the barrier metal is interposed. By connecting, the upper metal is contacted so as to surround the side surface of the via hole, the contact area is increased, the resistance is lowered and stabilized, and a margin is also provided for the deviation of the photoengraving process. An object of the present invention is to provide a semiconductor device that can be manufactured.

  The invention described in claim 3 adds a new photoengraving process by applying the etch-back technique to the barrier metal by forming the via hole layer only on the side of the via hole layer. Therefore, an object of the present invention is to provide a semiconductor device which forms a barrier metal for preventing Cu diffusion only on the side portion of a via hole, and has a low contact resistance and a high resistance against expansion stress.

  According to the invention of claim 4, the copper of the via hole layer is produced using the copper of the lower layer metal, so that Cu of the lower layer metal is used as a seed metal that becomes a seed of electrolytic plating in the lower part of the via hole. Another object of the present invention is to provide a semiconductor device having low contact resistance and high resistance to expansion stress by allowing Cu to be formed by electrolytic plating.

  In the invention according to claim 5, when forming a copper lower layer metal wiring under the via hole layer by the damascene method, the via hole layer and the lower layer metal are connected by the same copper layer without using the barrier metal layer. Another object of the present invention is to provide a semiconductor device manufacturing method for manufacturing a semiconductor device that does not generate voids, has low resistance, is stable, and has high reliability without using new devices and materials.

  According to a sixth aspect of the present invention, when a copper metal wiring is formed above the via hole layer by the damascene method, the metal wiring is provided so as to surround the metal wiring on the upper portion of the via hole layer, and the barrier metal is interposed. By connecting, the upper metal is contacted so as to surround the side surface of the via hole, the contact area is increased, the resistance is lowered and stabilized, and the void is also provided with a margin against the deviation of the photoengraving. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can manufacture a stable and reliable semiconductor device that does not generate low resistance.

  The invention according to claim 7 adds a new photoengraving process by applying the etch-back technique to the barrier metal by forming the via hole layer only on the side portion of the via hole layer. A method of manufacturing a semiconductor device in which a barrier metal for preventing Cu diffusion is formed only on the side portion of a via hole, and a semiconductor device having low contact resistance and low resistance to expansion stress can be manufactured easily and inexpensively. It is intended to provide.

  In the invention according to claim 8, by using the copper of the lower layer metal to form the copper of the via hole layer, it is possible to reliably use Cu of the lower layer metal as a seed metal that becomes a seed for electrolytic plating in the lower part of the via hole. It is another object of the present invention to provide a method for manufacturing a semiconductor device, in which Cu can be formed by electroplating, and a semiconductor device having a low contact resistance and strong against expansion stress can be manufactured more inexpensively and easily.

  The semiconductor device according to claim 1 is a semiconductor device in which a copper lower layer metal wiring is formed below a via hole layer by a damascene method, and the via hole layer and the lower layer metal do not pass through a barrier metal layer. The said objective is achieved by being connected by the same copper layer.

According to a second aspect of the present invention, in a semiconductor device in which a copper metal wiring is formed above a via hole layer by a damascene method, an upper metal surrounds the metal wiring above the via hole layer. The above-mentioned purpose is achieved by being wired and connected via a barrier metal. In each of the above cases, for example, as described in claim 3, the via hole layer is formed on a side portion of the via hole layer. Only the barrier metal may be formed.

  Moreover, in the case of Claim 1 and Claim 3, as described in Claim 4, for example, copper of the via hole layer may be generated using copper of the lower layer metal.

  According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to a fifth aspect of the present invention, in which a damascene method is used to form a copper wiring of a lower layer metal below a via hole layer. The above-mentioned object is achieved by connecting with the same copper layer without going through.

  According to a sixth aspect of the present invention, there is provided a semiconductor device manufacturing method in which a copper metal wiring is formed above a via hole layer by a damascene method so as to surround the metal wiring above the via hole layer. The above-mentioned object is achieved by wiring the upper layer metal and connecting them through the barrier metal.

  In the case of claim 5 or claim 6, for example, as described in claim 7, in the semiconductor manufacturing method, a barrier metal may be formed only on a side portion of the via hole layer.

  In the case of claim 5 or claim 7, for example, as described in claim 8, the semiconductor manufacturing method may generate the via hole layer using copper of the lower layer metal.

  According to the semiconductor device of the first aspect of the present invention, when the copper lower layer metal wiring is formed below the via hole layer by the damascene method, the via hole layer and the lower layer metal are made of the same copper without using the barrier metal layer. Since the layers are connected, the contact resistance can be lowered, a stable via hole can be realized, and even if there is movement of Cu (copper) due to heat, it can move relatively freely. Generation of (Void) can be prevented, and further, the vertical direction of the via hole can be made the same material and can be made strong against stress due to expansion.

  According to the semiconductor device of the second aspect of the present invention, when the copper metal wiring is formed above the via hole layer by the damascene method, the metal wiring is wired so as to surround the metal wiring above the via hole layer, Since the connection is made through the barrier metal, the upper layer metal can be brought into contact with the via hole so that the contact area can be increased, the resistance can be lowered and stabilized, and the deviation of photolithography In contrast, it can be easily manufactured with a margin.

  According to the semiconductor device of the third aspect of the invention, since the via hole layer is formed with the barrier metal only on the side portion of the via hole layer, the etch back technique is applied to the barrier metal, and a new A barrier metal for preventing Cu diffusion can be formed only on the side of the via hole without adding photoengraving, and it can be made inexpensive and easy, and has low contact resistance and high resistance to expansion stress. can do.

  According to the semiconductor device of the present invention, since the copper of the via hole layer is generated by using the copper of the lower layer metal, Cu of the lower layer metal is used as a seed metal that becomes a seed of electrolytic plating in the lower part of the via hole. Thus, Cu can be surely formed by electrolytic plating, and it can be made cheaper and easier, and the contact resistance is low and it is strong against expansion stress.

  According to the method for manufacturing a semiconductor device of claim 5, when forming a copper lower layer metal wiring below the via hole layer by the damascene method, the via hole layer and the lower layer metal are not interposed through the barrier metal layer. Since they are connected by the same copper layer, it is possible to manufacture a stable and reliable semiconductor device with low resistance without using a new device or material, without generating voids.

  According to the semiconductor device manufacturing method of the sixth aspect of the present invention, when the copper metal wiring is formed above the via hole layer by the damascene method, the metal is surrounded by the metal wiring above the via hole layer. Wiring and connecting via barrier metal, upper metal can be contacted so as to surround the side surface of the via hole, the contact area can be increased, resistance can be lowered and stabilized, and photolithography It is possible to manufacture a stable and highly reliable semiconductor device having a margin against the deviation, generating no voids, and having a low resistance.

  According to the semiconductor device manufacturing method of the seventh aspect of the invention, since the via hole layer is formed with the barrier metal only on the side portion of the via hole layer, the etch back technique is applied to the barrier metal. The barrier metal for preventing Cu diffusion can be formed only on the side of the via hole without adding new photoengraving, and it is easy to manufacture a semiconductor device with low contact resistance and high resistance to expansion stress. can do.

  According to the semiconductor device manufacturing method of the invention described in claim 8, since the copper of the via hole layer is generated by using the copper of the lower layer metal, the lower layer is used as a seed metal that becomes a seed of electrolytic plating in the lower part of the via hole. By using metal Cu, it is possible to reliably form Cu by electrolytic plating, and it is possible to manufacture a semiconductor device with low contact resistance and high resistance to expansion stress even more inexpensively and easily.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The scope of the present invention limits this invention especially in the following description. As long as there is no description of the effect, it is not restricted to these aspects.

  1 to 9 are diagrams showing an embodiment of a semiconductor device and a manufacturing method of the semiconductor device of the present invention, and FIG. 1 is an application of an embodiment of the semiconductor device and the manufacturing method of the semiconductor device of the present invention. 1 is a front sectional view of a semiconductor device 1. FIG.

  In FIG. 1, a semiconductor device 1 has a transistor gate electrode 2 formed at the bottom thereof, and the gate electrode 2 is covered with a poly-metal interlayer insulating film 3. On the poly-metal interlayer insulating film 3, an etching stop layer 4, an interlayer film 5, a cap layer 6, an interlayer film 7, an etching stop layer 8, an interlayer film 9 and a cap layer 10 are sequentially formed.

  In the semiconductor device 1, a contact hole 11 is formed in the interlayer insulating film 3, and a via hole 12 is formed immediately above the contact hole 11. A barrier metal 13 for preventing Cu diffusion is formed around the via hole 12, and Cu of the first metal (lower layer metal) 14 is buried between the via hole 12 and the contact hole 11. A Cu wiring of the second metal (upper layer metal) 15 is formed in the interlayer film 9 portion above the via hole 12, and a Cu wiring 16 of the via hole 12 is filled in the intermediate interlayer film 7 portion in the via hole 12. Has been.

  The contact hole 11 is usually filled with tungsten, and the etching stop layers 4 and 8 are made of SiON or the like. The interlayer films 5, 7, and 9 are interlayer films between metal wirings, and what is commonly referred to as a Low-K film is used. The cap layers 6 and 10 are cap layers for preventing diffusion of Cu, and SiN is used.

  The semiconductor device 1 is manufactured as shown in FIGS. That is, first, as shown in FIG. 2, element isolation is performed on the Si substrate 21 by the STI 22. After the transistor 2 is formed, the poly-metal interlayer film 3 is deposited and a contact hole 11 is formed.

  Thereafter, the etching stop layer 4 and the interlayer film 5 which is a Low-K film are deposited, and the barrier metal 23 and Cu 24 are formed as the wiring of the first metal 14 by a normal damascene method.

  Next, as shown in FIG. 3, a cap layer 6 for preventing diffusion of Cu 24 of the first metal 14 is formed of Si 3 N 4, interlayer films 5 and 7 which are Low-K films such as FSG and SiOC, and an etching stop layer. 8, 8 'are formed.

  Next, as shown in FIG. 4, patterning for the via hole 12 is performed by photolithography, and the interlayer films 7 and 9, the cap layer 6, and the etching stop layers 8 and 8 ′ are removed to form the via hole 12.

  Next, as shown in FIG. 5, in order to prevent the diffusion of Cu 24 in the first metal 14 of the via hole 12, TiN 25 is deposited with a thickness of about 50 nm to 100 nm. At this time, TiN 25 is formed on the entire surface including the lower and side portions of the via hole 12.

  Next, as shown in FIG. 6, the TiN 25 is anisotropically etched by a so-called etch-back method to remove the TiN 25 in portions other than the side portions of the via hole 12, and thereafter, the Cu seed layer 26 is formed to a thickness of 50 nm. It is formed by sputtering about 200 nm. At this time, in the lower portion 12a of the via hole 12, Cu of the first metal 14 and Cu of the seed metal (Cu seed layer 26) are directly connected.

  Next, as shown in FIG. 7, a Cu layer is formed on the entire surface of the wafer by electrolytic plating to a thickness of about 500 nm to 3000 nm, and is cut by CMP (Chemical Mechanical Polishing). A Cu layer 27 is formed.

  Next, as shown in FIG. 8, photoengraving of the second metal 15 is performed, and the insulating film in the wiring portion is removed. At this time, since the metal is already present in the upper portion of the via hole 12, it is not etched. After the groove 28 of the second metal 15 is formed, the barrier metal 13 and the Cu seed layer 29 are deposited by about 50 nm to 200 nm, respectively.

  Next, as shown in FIG. 9, the Cu layer is deposited by about 500 nm to 3000 nm by electrolytic plating, and is cut by CMP to form the Cu wiring of the second metal 15. Then, a cap (Cap) layer 10 for preventing diffusion is deposited with Si3N4 to a thickness of about 50 nm to 200 nm. Then, an upper layer metal wiring is also formed by the same method as described above.

  As described above, the semiconductor device 1 and the manufacturing method of the semiconductor device 1 according to the present embodiment are the damascene method. When forming the wiring of the first metal 14 of copper below the via hole 12, the via hole 12 and the first metal 14 are formed. They are connected by the same copper layer without using the barrier metal 13.

  Therefore, a stable via hole 12 can be realized by reducing the contact resistance, and even if there is movement of Cu (copper) due to heat, it can move relatively freely, and voids are generated. In addition, the vertical direction of the via hole 12 can be made of the same material and can be made strong against stress due to expansion.

  Further, in the semiconductor device 1 of the present embodiment, wiring is performed so as to surround the second metal 15 with respect to the Cu wiring 16 that is the metal wiring above the via hole 12, and is connected via the barrier metal 13.

  Therefore, the second metal 15 is brought into contact with the side surface of the via hole 12 so that the contact area can be increased, the resistance can be lowered and stabilized, and a margin is also provided for deviations in photolithography. It can be easily manufactured.

  Further, in the semiconductor device 1 of this embodiment, the barrier metal 13 is formed only on the side portion of the via hole 12, and there is no barrier metal on the bottom portion of the via hole 12.

  Therefore, the barrier metal 13 for preventing Cu diffusion can be formed only on the side portion of the via hole 12 without applying new photoengraving by applying the etch back technique to the barrier metal 13, which is inexpensive and easy. In addition, the contact resistance is low and it can be made strong against expansion stress.

  Further, in the semiconductor device 1 of the present embodiment, the copper 24 of the via hole 12 is generated using the copper of the first metal 14.

  Therefore, Cu 24 of the first metal 14 can be used as a seed metal that becomes a seed of electrolytic plating in the lower portion of the via hole 12, and Cu can be surely formed by electrolytic plating. In addition, the contact resistance is low and it can be made strong against expansion stress.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to the above, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a semiconductor device that forms a stable Cu (copper) wiring with a small contact resistance between a via hole and a metal by a damascene method and a method for manufacturing the semiconductor device.

1 is a front cross-sectional view of a semiconductor device to which one embodiment of a semiconductor device and a semiconductor device manufacturing method of the present invention is applied. FIG. 3 is a cross-sectional view illustrating a manufacturing procedure from a first layer interlayer film to a second layer interlayer film on a first stage substrate of the semiconductor device manufacturing method of FIG. 1; FIG. 3 is a cross-sectional view showing a manufacturing procedure from a transistor and a third interlayer film to a fourth interlayer film on a second stage substrate of the semiconductor device manufacturing method of FIG. 1; FIG. 4 is a cross-sectional view showing a manufacturing procedure for forming a via hole on the first metal of FIG. 3 in the third stage of the method for manufacturing the semiconductor device of FIG. 1; Sectional drawing which shows the manufacture procedure which forms TiN for Cu diffusion prevention in the via hole of the 4th step of the manufacturing method of the semiconductor device of FIG. Sectional drawing which shows the manufacture procedure which forms Cu layer in the via hole of FIG. 5 of the 5th step of the manufacturing method of the semiconductor device of FIG. FIG. 7 is a cross-sectional view showing a manufacturing procedure in which a portion other than the inside of a via hole is removed after a Cu layer is formed on the entire surface of the wafer of FIG. Sectional drawing which shows the manufacture procedure which performs the etching for 2nd metals of the 7th step of the manufacturing method of the semiconductor device of FIG. Sectional drawing which shows the manufacture procedure which forms the 2nd metal of the 8th step of the manufacturing method of the semiconductor device of FIG. Front sectional drawing of the conventional semiconductor device. FIG. 12 is a front sectional view of the conventional semiconductor device of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Gate electrode 3 Poly-metal interlayer insulation film 4 Etching stop layer 5 Interlayer film 6 Cap layer 7 Interlayer film 8, 8 'Etching stop layer 9 Interlayer film 10 Cap layer 11 Contact hole 12 Via hole 13 Barrier metal 14 1st Metal 15 Second metal 16 Cu wiring 21 Si substrate 22 STI
23 Barrier metal 24 Cu
25 TiN
26 Cu seed layer 27 Cu layer 28 Groove 29 Cu seed layer

Claims (8)

  In a semiconductor device in which a copper lower layer metal wiring is formed below a via hole layer by a damascene method, the via hole layer and the lower layer metal are connected by the same copper layer without a barrier metal layer. A featured semiconductor device.   In a semiconductor device in which copper metal wiring is formed above a via hole layer by the damascene method, wiring is performed so that an upper metal surrounds the metal wiring above the via hole layer and is connected via a barrier metal. A semiconductor device characterized by comprising:   3. The semiconductor device according to claim 1, wherein the via hole layer has a barrier metal formed only on a side portion of the via hole layer.   4. The semiconductor device according to claim 1, wherein copper in the via hole layer is generated by using copper in the lower layer metal.   In a method of manufacturing a semiconductor device in which a copper wiring of a lower layer metal is formed below a via hole layer by a damascene method, the via hole layer and the lower layer metal are connected by the same copper layer without a barrier metal layer. A method for manufacturing a semiconductor device.   In a method of manufacturing a semiconductor device in which a copper metal wiring is formed above a via hole layer by a damascene method, an upper metal is wired so as to surround the metal wiring above the via hole layer, and is connected via a barrier metal. A method for manufacturing a semiconductor device.   7. The method of manufacturing a semiconductor device according to claim 5, wherein a barrier metal is formed only on a side portion of the via hole layer.   8. The method of manufacturing a semiconductor device according to claim 5, wherein the via hole layer is generated using copper of the lower layer metal.

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