JP2006173882A - Wideband offset circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain flat transmission characteristics from DC to high frequency region while sustaining impedance matching in a wideband offset circuit. <P>SOLUTION: The wideband offset circuit 1 includes a high frequency signal path passing a capacitor 12, and a low frequency signal path passing an amplifier 13 having an offset control voltage source 19 and compounds a low frequency signal and a high composite signal having a desired offset voltage. An output signal having flat transmission characteristics from DC to high frequency is obtained as a composite signal. Furthermore, an impedance matching circuit consisting of a resistor 10 and an inductance 11 is provided on the input terminal 50 side, and an impedance matching circuit consisting of a resistor 14 and an inductance 15 is provided on the output terminal 60 side. Consequently, impedance can be matched from DC to high frequency on the input side and the output side. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wide band offset circuit for applying a desired DC offset to a wide band electric signal.

  For example, in a high-speed digital data transmission system and its test, a signal level shift, that is, a DC bias is required for a wide-band electrical signal ranging from a low frequency to several tens of GHz. In such a case, a circuit called a normal bias T is used to apply a desired DC offset to a high-frequency electric signal.

  As shown in FIG. 5, in the bias T, a capacitor C is inserted between an input terminal and an output terminal which are signal paths, and an inductance L is inserted between a DC voltage application terminal and the output terminal. By interposing the bias T, the DC voltage of the signal is blocked by the capacitor C, and the DC voltage on the output terminal side is determined by the DC voltage applied from the DC voltage application terminal. The bias T has a good high-frequency characteristic because the signal path is composed of only passive elements such as resistors, capacitors, and transmission lines. That is, at a frequency sufficiently higher than the cut-off frequency determined by C and L, a high frequency signal is hardly attenuated and transmitted to the output terminal. Therefore, the bias T is more effective for high-frequency signals than a bias circuit using a semiconductor element that is restricted by a high-frequency signal depending on the operating frequency of the semiconductor element, and a circuit having a band exceeding 40 GHz has been put into practical use.

However, the bias T has the following problems.
The first is that the low band is cut by the capacitor C. That is, a frequency component lower than the cutoff frequency cannot be faithfully transmitted. Therefore, a sag occurs in a low-frequency square wave signal or the like. In a high-speed digital data transmission system, when the transmission data is a low-cycle burst signal or a random signal, the average level after passing through the bias T varies depending on the data arrangement (for example, the difference between 0 and 1). This causes a decrease in voltage margin and an increase in jitter.

  The second is deterioration of reflection characteristics at low frequencies. For transmission of high frequency signals, a 50Ω transmission line is usually used. When the bias T is inserted here, the impedance is matched and there is almost no reflection at a frequency sufficiently higher than the cutoff frequency. However, on the input terminal side, reflection increases at a frequency lower than the cut-off frequency by the inserted capacitor C, and total reflection occurs at DC. This greatly affects the circuit or device connected to the input terminal.

  For example, in the case of a device or signal source that has a source impedance of 50Ω and is assumed to be terminated and used at 50Ω, at a frequency sufficiently lower than the cut-off frequency, the amplitude of the high frequency is almost twice due to an increase in reflection. Get out. In a high-speed digital data transmission system, if the signal amplitude largely fluctuates due to a low-cycle signal or data pause, the operating point and power consumption of the device fluctuate, leading to deterioration in the signal quality output from the device due to thermal distortion or the like. In addition, since many high-speed semiconductor devices have a low withstand voltage, it may not be allowed to produce a double amplitude due to total reflection.

  A wideband signal coupling circuit capable of providing an offset, which has a high-frequency path and a low-frequency path and has a flat transfer characteristic from direct current to high frequency has been proposed (see Patent Document 1). The impedance matching by improving the reflection characteristics is not considered at all.

US Pat. No. 4,551,636

  In view of the above problems, an object of the present invention is to provide a wide band offset circuit capable of obtaining flat transfer characteristics while maintaining impedance matching from a direct current to a high frequency region.

  According to the present invention, a high-frequency signal path including a capacitor connected between a signal input terminal and a signal output terminal, a first impedance matching circuit connected to the signal input terminal, and an input connected to the signal input terminal There is provided a wide band offset circuit comprising an amplifier for providing a desired offset and a low frequency signal path including an output of the amplifier and a second impedance matching circuit connected between the signal output terminals.

  The first and second impedance matching circuits can be composed of a series circuit of a resistor and an inductance, and the other end of the impedance matching circuit is connected to a voltage source that determines a termination voltage. May be.

  Furthermore, the amplifier that provides the desired offset may have an offset control voltage source.

  Therefore, according to the wide-band offset circuit of the present invention, it is possible to provide an arbitrary DC offset while maintaining impedance matching and achieving a flat characteristic from DC to high frequency.

  That is, since a flat transfer characteristic from DC to high frequency is obtained, a signal including a low frequency component can be transmitted without being distorted, and only the DC offset can be controlled. In addition, impedance matching can be achieved from DC to high frequency when viewed from either the input terminal or output terminal side, so that distortion due to device operating points and power consumption fluctuations does not change from the DC region. Can be suppressed. Furthermore, the present invention can be applied to a device that requires a termination with a small voltage level margin.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a wide band offset circuit 1 according to an embodiment of the present invention. In the broadband offset circuit 1 of the present embodiment, an external signal source 31 is connected to the input terminal 50 for explanation of the operation. Resistor 30 represents the impedance of signal source 31. A termination resistor 32 is connected to the output terminal 60. In this embodiment, the characteristic impedance of the system is 50Ω, and the resistors 30 and 32 are also 50Ω.

Next, the internal configuration of the wide band offset circuit 1 will be described.
The input terminal 50 and the output terminal 60 are connected by a transmission line having a characteristic impedance of 50Ω, and a capacitor 12 is inserted in the middle. The path including the capacitor 12 is a high-frequency signal path.

  The + input of the operational amplifier 13 is connected to the input terminal 50, and the output of the operational amplifier 13 is connected to the output terminal 60 via the inductance 15 and the resistor 14. The path including the operational amplifier 13 is a low frequency signal path.

  The output of the operational amplifier 13 is connected to the negative input of the operational amplifier 13 through the resistor 16. An offset control voltage source 19 is connected to the negative input of the operational amplifier 13 through a resistor 17. A desired DC offset can be given to the signal input to the circuit 1 by the offset control voltage source 19. Here, although the offset control power source 19 is disposed in the wide band offset circuit 1, it may be configured to control supply of the offset voltage using an external power source.

  An input termination voltage source 20 is further connected to the input terminal 50 via a resistor 10 and an inductance 11. Although the input termination voltage source 20 is provided so as to correspond to various signal source voltages, the inductance 11 can be directly connected to the GND except for the input termination voltage source 20. When viewed from the input terminal 50 side, the impedance to the capacitor 12 and the operational amplifier 13 is high impedance, so that the terminating resistance as a direct current is almost determined by the resistor 10. When viewed from the output terminal 60 side, the termination resistance as a direct current is almost determined by the resistance 14 when the operational amplifier 13 is not operating. Therefore, in this embodiment, the resistors 10 and 14 are selected to be 50Ω. The inductance 11 connected to the resistor 10 and the inductance 15 connected to the resistor 14 are elements that determine the characteristics of the low-frequency path, and have the same value to obtain a flat characteristic after combining the low-frequency signal and the high-frequency signal. It is. The resistor 10 and the inductance 11 become an impedance matching circuit on the input side, and the resistor 14 and the inductance 15 become an impedance matching circuit on the output side.

  The resistors 16 and 17 determine the gain of the operational amplifier 13 and select a value that doubles the gain of the amplifier 13 so that the total gain at DC becomes 1. The resistor 18 is an isolation resistor that prevents the input capacitance of the operational amplifier 13 from affecting the high-frequency signal path.

  As described above, the wide-band offset circuit 1 of the present embodiment includes the high-frequency signal path including the capacitor 12 and the low-frequency signal path including the operational amplifier 13, and the operational amplifier 13 is offset control connected to the − input. A DC offset can be provided by the voltage source 19. Therefore, a composite signal of a high frequency signal and a low frequency signal having a desired DC offset is output from the output terminal 60. Further, an impedance matching circuit on the input side composed of the resistor 10 and the inductance 11 and an matching circuit on the output side composed of the resistor 14 and the inductance 15 are provided, and impedance matching can be achieved on the input side and the output side.

Next, the characteristics of the wide band offset circuit of this embodiment will be described.
The voltage at the input terminal 50 is V1, the voltage at the output terminal 60 is V2, the output voltage of the operational amplifier 13 is Vop, the capacitance of the capacitor 12 is C, and the value of the inductance 15 is L. Since the resistor 14 and the resistor 32 are 50Ω, when Z1 = 1 / jωC, Z2 = 50 + jωL, and Kirchoff's current law is applied to the output terminal 60,

It becomes.

  Since the gain of the operational amplifier 13 is double, when Vop = 2Vi and the transfer characteristic G = V2 / V1 is obtained using the equation (1),

It becomes.

  Next, assuming that the voltage of the signal source 31 is Vs, the value of the inductance 11 is L which is the same as the value of the inductance 15. Therefore, if Z4 = 50 + jωL, the current law at the input terminal 50 is

It becomes. The branch current passing through the resistor 18 is ignored because of its high impedance.

  Substituting V2 in equation (2) into V2 in equation (3) and solving for V1,

It becomes.

  In general, in a high frequency circuit, an S parameter is used to define circuit characteristics. That is, when the incident waves a1 and a2 and the reflected waves b1 and b2 at each port are considered in the 2-port circuit shown in FIG. 2A, the relationship is expressed by the equation shown in FIG. 2B using the S parameter Sij. It is expressed by For example, S11 represents the ratio (b1 / a1) of reflection when the incident wave from port 1 is input when port 2 is non-reflective terminated (a2 = 0), and S21 is port 2 non-reflective. It represents the rate (b2 / a1) at which the incident wave from port 1 is transmitted to port 2 as a reflection termination (a2 = 0).

  In the wide-band bias circuit 1 of the present embodiment, if Vs = 2, among the S parameters, S11 representing the reflection characteristics and S21 representing the forward transfer characteristics can be calculated as follows.

S11 = V1-1 (5)
S21 = V1 · G (6)
If the signal source 31 is connected to the output terminal 60 instead of the input terminal 50, S22 (reflection characteristic of the port 2) can be obtained by the same method.

  According to this embodiment, in addition to the high-frequency signal path formed by the capacitor 12, the low-frequency signal path provided with the operational amplifier 13 through which the low-frequency signal passes is provided. The transfer characteristic can be made flat from direct current to high frequency, that is, S parameter S21 can be set to approximately 1. Further, since the impedance matching circuit in the low frequency region is provided for each of the input terminal 50 and the output terminal 60, impedance matching can be performed on both the input terminal and output terminal sides, that is, S11 and S22 can be performed from DC to high frequency. Both can be almost zero.

  Hereinafter, specific numerical values of the transfer characteristic S21 and the reflection characteristics S11 and S22 are calculated and described. FIG. 3 shows the calculation result of S21 calculated with the value of the capacitor 13 as 1 μFarad and the values of the inductances 11 and 15 as 1 μH. FIG. 4 shows the calculation of the reflection characteristics S11 and S22 calculated with the same numerical example as FIG. It is a result.

In the graph of FIG. 3, the vertical axis represents the absolute value of S21, which is the transfer characteristic, and the horizontal axis ^represents the index k of the frequency 10 kHz. For example, at k = 4, the frequency is 10 kHz, at k = 7, the frequency is 10 MHz, and at k = 10, the frequency is 10 GHz. As is apparent from the figure, | S21 (k) | = 1 is substantially satisfied in the high frequency region from DC to about 1 MHz and 100 MHz or higher, indicating ideal transfer characteristics. Although it does not reach 1 slightly in the vicinity of 10 MHz, this fluctuation is about 0.0001 = 0.01%.

4, the vertical axis, S11 represents the reflection characteristic (k) and takes the absolute value of the S22 (k), the horizontal axis is obtained by taking the exponent k of the frequency ¹⁰ k Hz. Since | S11 (k) | and | S22 (k) | have almost the same results, they are indicated by a single curve in the figure. In S22 and S11, the values are almost zero at a high frequency from DC to about 100 Hz and higher than 100 MHz, indicating ideal reflection characteristics. The reflection characteristic is slightly increased over 100 Hz to 100 MHz, but this variation is within 0.05%. As described above, in the wide-band bias circuit of this embodiment, even if there are fluctuations in the transfer characteristics and the reflection characteristics, they are within 0.05%, which is practically satisfactory.

  In addition, since the transfer characteristic and the reflection characteristic vary in the frequency region where the signal of the high frequency path and the signal of the low frequency path are combined, if the overlap of the frequency of the high frequency path and the low frequency path is increased, Furthermore, the fluctuation can be reduced. That is, by increasing the capacitance C of the capacitor 12 to lower the cut-off frequency of the high-frequency path, or decreasing the inductance L of the inductance 15 to increase the cut-off frequency of the low-frequency path, transfer characteristics or reflection characteristics. It is possible to reduce the error. However, since the characteristics of the low frequency path are also governed by the frequency characteristics of the operational amplifier, if the cut-off frequency of the low frequency path is too high, the high frequency signal input to the operational amplifier may not be correctly processed. If an expensive operational amplifier is used, it may be possible to process an input high-frequency signal due to an increase in the cutoff frequency, but this increases the cost. Therefore, it is desirable to select the overlapping frequency so that the gain of the operational amplifier does not change.

  As described above, according to the present invention, an arbitrary DC offset can be given to a signal while maintaining impedance matching from DC to high frequency, and a flat transfer characteristic from DC to high frequency can be obtained. Therefore, for example, when applied to a circuit such as logic signal level conversion in a high-speed digital data transmission system, a remarkable effect can be obtained. Further, even if the transmission data is a burst signal or a random signal with a low cycle, the average level does not fluctuate depending on the data arrangement or increase in jitter is not caused.

FIG. 3 is a diagram illustrating a wideband offset circuit according to an embodiment of the present invention. (1) is a diagram showing a two-port circuit for explaining the S parameter, and (2) is a diagram showing an S parameter matrix. It is a figure which shows the transfer characteristic of the wide band offset circuit of FIG. It is a figure which shows the reflective characteristic of the input of the wide band offset circuit of FIG. 1, and an output. It is a figure which shows the conventional bias T.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Broadband offset circuit 12 Capacitor 13 Operational amplifier 19 Offset control voltage source 20 Input termination power supply 10, 14 Resistance 11, 15 Inductance 31 Signal source

Claims (4)

A high-frequency signal path including a capacitor connected between the signal input terminal and the signal output terminal;
A first impedance matching circuit connected to the signal input end;
A low-frequency signal path including an amplifier having an input connected to the signal input terminal and providing a desired offset, and an output of the amplifier and a second impedance matching circuit connected between the signal output terminals;
Broadband offset circuit with   The wide-band offset circuit according to claim 1, wherein the first and second impedance matching circuits comprise a series circuit of a resistor and an inductance.   3. The wide-band offset circuit according to claim 1, wherein the first impedance matching circuit has the other end connected to a voltage source that determines a termination voltage.   The wide-band offset circuit according to claim 1, wherein the amplifier that provides the desired offset includes an offset control voltage source.

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