JP6640073B2 - Digital signal offset adjusting device and digital signal offset adjusting method - Google Patents

Description

  The present invention relates to a digital signal offset adjustment device and a digital signal offset adjustment method for applying an arbitrary bias voltage to a digital signal and outputting the digital signal.

  In recent years, with the increase in the number of users and the spread of multimedia communications, various types of digital communication devices have been required to have higher transmission capacity, and one of the indicators for evaluating the quality of digital signals in these digital communication devices. A bit error rate (hereinafter abbreviated as an error rate) defined as a comparison between the number of occurrences of code errors in received data and the total number of received data is known.

  Therefore, when a desired digital communication device is used as a device under test and the error rate of the device under test is measured, for example, an error rate measurement device disclosed in Patent Document 1 below is used. In this type of error rate measuring device, an electrical stress signal of a known pattern is applied as a test signal from a pattern generator in order to measure how much the device under test can tolerate electrical stress. Jitter tolerance measurement is performed in which loopback is performed inside or outside the device under test, received by an error detector, and compared with a test signal to determine the presence or absence of an error with respect to the amount of stress applied.

  Further, when receiving the digital signal looped back inside or outside of the device under test by the error detector of the error rate measurement device described above, a digital signal offset adjustment for applying an arbitrary bias voltage to the digital signal and outputting the digital signal. As an apparatus, for example, an apparatus disclosed in Patent Document 2 below is known.

JP 2007-274474 A Japanese Patent No. 4261555

  By the way, the digital signal offset adjusting device of the above-mentioned patent document 2 is adopted as the signal receiving unit in the error rate measuring device of the above-mentioned patent document 1, and the connection between the input and the output is performed under the assumption that the DUT is measured. In the digital signal offset adjusting device of Patent Document 2, the DC connection is always performed. If the DC component of the output signal from the device under test is 0, there is no problem with the DC connection, but the output signal from the device under test is If the DC component is not zero, the current continues to flow from the object to be measured, which has a problem of adversely affecting the measurement. For this reason, as a countermeasure, for example, a configuration in which a DC block circuit represented by a capacitor or the like is separately provided as an external circuit is adopted, and the connection between the input and output is AC-connected.

  However, in a configuration in which the DC block circuit is provided as an external circuit, the transmission loss of the DC block circuit itself may adversely affect the measurement result when AC connection is made. For this reason, there has been a demand for a digital signal offset adjusting device capable of realizing DC connection and AC connection with a simple configuration without adversely affecting measurement results.

  Therefore, the present invention has been made in view of the above problems, and provides a digital signal offset adjusting device and a digital signal offset adjusting method capable of realizing DC connection and AC connection with a simple configuration. The purpose is.

To achieve the above object, a digital signal offset adjusting device according to claim 1 of the present invention includes an input terminal 2 and an output terminal 4,
A capacitor 3 provided between the input terminal and the output terminal for transmitting an AC component of the digital signal Di input to the input terminal to the output terminal;
A bias application coil 8 having one end connected to the output terminal;
A low-frequency extraction coil 6 having one end connected to the input terminal and passing a DC component and a low-frequency component of a digital signal input to the input terminal;
A DC voltage generator 5 for outputting a DC signal of an arbitrary voltage;
A DC signal output from the DC voltage generator is combined with a signal output from the other end of the low frequency extraction coil, and a signal obtained by the combination is combined with the other end of the bias application coil. In the digital signal offset adjusting device 1 including the synthesizing circuit 7 for supplying
A switching unit 9 including a switch circuit 9a formed of a semiconductor relay , connected in series between the low-frequency extraction coil and the synthesis circuit ;
An auxiliary circuit 9b composed of a capacitor C2 or a series circuit of the capacitor and the resistor R2 is connected in parallel to the switch circuit of the switching unit .

The digital signal offset adjusting method according to claim 3, wherein the input terminal 2 and the output terminal 4
A capacitor 3 provided between the input terminal and the output terminal for transmitting an AC component of the digital signal Di input to the input terminal to the output terminal;
A bias application coil 8 having one end connected to the output terminal;
A low-frequency extraction coil 6 having one end connected to the input terminal and passing a DC component and a low-frequency component of a digital signal input to the input terminal;
A DC voltage generator 5 for outputting a DC signal of an arbitrary voltage;
A DC signal output from the DC voltage generator is combined with a signal output from the other end of the low frequency extraction coil, and a signal obtained by the combination is combined with the other end of the bias application coil. In the digital signal offset adjusting method using the digital signal offset adjusting device 1 including the synthesizing circuit 7 for supplying
Connecting a switching unit 9 including a switch circuit 9a formed of a semiconductor relay in series between the low-frequency extraction coil and the synthesis circuit ;
Connecting the auxiliary circuit 9b, which is a series circuit of the capacitor C2 or the resistor R2, to the switch circuit of the switching unit in parallel .

  According to the present invention, the switching unit includes a switch circuit including a semiconductor relay including an on-resistance and an off-capacitance, and the switching unit is connected in series between the low-frequency extraction coil and the combining circuit. DC connection can be realized with a simple configuration.

  Further, if an auxiliary circuit composed of a series circuit of a capacitor or a capacitor and a resistor is connected in parallel to the switch circuit as a switching unit, the possibility of causing waveform distortion and oscillation of the digital signal offset adjustment device is reduced, and an AC voltage close to ideal is reduced. Connection can be realized.

FIG. 1 is a diagram illustrating a first embodiment of a digital signal offset adjusting device according to the present invention. FIG. 4 is a diagram illustrating a digital signal offset adjusting device according to a second embodiment of the present invention. FIG. 3 is a diagram illustrating frequency characteristics when a switch circuit in the digital signal offset adjusting device of FIGS. 1 and 2 is turned on. FIG. 2 is a diagram illustrating frequency characteristics when a switch circuit in the digital signal offset adjusting device in FIG. 1 is off. FIG. 3 is a diagram illustrating frequency characteristics when a switch circuit in the digital signal offset adjusting device in FIG. 2 is off.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.

  A digital signal offset adjusting device (hereinafter, abbreviated as an offset adjusting device) according to the present invention applies an arbitrary bias voltage to a digital signal and outputs the digital signal. The digital signal offset adjusting device according to the first embodiment in FIG. 1 or FIG. Of the second embodiment. Hereinafter, each embodiment will be described.

[First Embodiment]
As shown in FIG. 1, the offset adjusting device 1 (1A) of the first embodiment includes an input terminal 2, a capacitor 3, an output terminal 4, a DC voltage generator 5, a first coil 6, a combining circuit 7, It has a schematic configuration including two coils 8, a switching unit 9 (9A), and a control unit 10.

  The input terminal 2 receives a digital signal Di having a broadband frequency characteristic including a low frequency component, a DC component, and a high frequency component.

  The capacitor 3 is connected between the input terminal 2 and the output terminal 4, and passes the high frequency component (AC component) of the digital signal Di input from the input terminal 2 to the output terminal 4.

  The output terminal 4 converts the AC component of the digital signal Di input from the input terminal 2 and passed through the capacitor 3 into a signal input from the input terminal 2 and extracted by the first coil 6 by the DC voltage generator 5. A digital signal Do to which a synthesized signal obtained by synthesizing the generated offset voltage is added is output. The digital signal Do is used as a test signal, for example, a device under test (DUT) (not shown) such as a PCIe device (for example, a video card, an SSD (Solid State Drive), a network card, a graphics card, etc.). Is input to

  The DC voltage generator 5 generates and outputs an offset voltage based on a desired DC voltage fixed or variably set in advance under the control of the control unit 10.

  The first coil 6 is a low-frequency extraction coil connected between the input terminal 2 and the combining circuit 7. The first coil 6 allows the low frequency component and the DC component of the digital signal Di input from the input terminal 2 to pass to the other end (the switching unit 9 side).

  The synthesizing circuit 7 includes a low-frequency component and a DC component signal of the digital signal Di input from the input terminal 2 via the first coil 6 and the switching unit 9, an offset voltage output from the DC voltage generator 5, And outputs a synthesized signal obtained by synthesizing. The synthesizing circuit 7 can be configured by a well-known circuit such as Patent Document 2.

  The second coil 8 is a bias application coil connected between the combining circuit 7 and the output terminal 4. The second coil 8 passes the synthesized signal input from the synthesis circuit 7 to the output terminal 4. Note that the first coil 6 and the second coil 8 are inductors used in a general bias T circuit.

  The switching unit 9 (9A) is connected between the first coil 6 and the combining circuit 7 in order to switch between DC connection and AC connection with a simple configuration.

  The switching unit 9A is configured by a semiconductor relay including a switch circuit 9a. As shown in FIG. 1, the switch circuit 9a includes an equivalent circuit including a contact S1 switched and controlled by the control unit 10, a resistor (on resistance: about several Ω), a resistor R1, and a capacitor (off capacitance: about 1 to 100 pF) C1. It consists of.

  Since the DC level of the semiconductor relay is not always constant, the switch circuit 9a needs to use a circuit that does not need to match the DC level with the control system. At this time, for example, a semiconductor relay typified by a photo MOS relay may be used as the switch circuit 9a.

  However, as shown in FIG. 1, the existence of the ON resistance by the resistor R1 and the OFF capacitance by the capacitor C1 cannot be ignored in the equivalent circuit of the switch circuit 9a. In particular, when the contact S1 of the semiconductor relay is off, series resonance occurs due to the input impedance of the first coil 6, the capacitor C1, and the combining circuit 7.

  Here, in the offset adjusting apparatus 1A of the first embodiment, the frequency characteristics when the semiconductor relay of the switch circuit 9a is on are shown in FIG. 3, and the semiconductor characteristics when the semiconductor relay of the switch circuit 9a is off are shown. FIG. 4 shows the frequency characteristics of only the equivalent circuit of the relay. Note that the two-dot chain lines in FIGS. 3 and 4 show the frequency characteristics of only the capacitance that passes 100 kHz or more.

  In the offset adjustment device 1A of the first embodiment, when the semiconductor relay of the switch circuit 9a is on (contact S1: closed), the original offset adjustment for transmitting a signal from DC to high frequency is performed as in the related art. It operates as a device, and is DC-connected for input and output, and has a flat characteristic from low frequency to high frequency as shown in FIG.

  In the case of DC connection, since only the resistance R1 is affected, performance degradation can be reduced by selecting, as the resistance R1, a component whose on-resistance is as small as about several Ω.

  In the offset adjusting device 1A of the first embodiment, when the semiconductor relay of the switch circuit 9a is off (contact S1: open), the transmission of the DC component transmitted from the input terminal 2 is cut, and It operates as a level shift circuit for transmitting only the component, and the connection between the input and output is AC-connected via the capacitor C1.

  By the way, in the first embodiment described above, in the case of AC connection, series resonance occurs due to the input impedance of the first coil 6, the capacitor C1, and the combining circuit 7, and a dip due to unnecessary resonance occurs in the pass characteristic (for example, FIG. (Frequency of about 5 MHz), which may cause deterioration of the transmitted signal due to waveform distortion and oscillation of the offset adjusting apparatus 1A. An offset adjusting device that solves this problem is a second embodiment described below.

[Second embodiment]
As shown in FIG. 2, the offset adjusting device 1 (1B) of the second embodiment includes an input terminal 2, a capacitor 3, an output terminal 4, a DC voltage generator 5, a first coil 6, a combining circuit 7, It has a schematic configuration including two coils 8, a switching unit 9 (9B), and a control unit 10.

  The offset adjusting device 1B according to the second embodiment is different from the offset adjusting device 1A according to the first embodiment in the internal configuration of the switching unit 9, and other configurations are the same as those in the first embodiment. Therefore, the same reference numerals are given and the description is omitted.

  The switching unit 9B in the offset adjustment device 1B is connected between the first coil 6 and the combining circuit 7 to switch between DC connection and AC connection with a simple configuration, similarly to the switching unit 9A of the first embodiment. Is done.

  The switching unit 9A includes a switch circuit 9a and an auxiliary circuit 9b. As shown in FIG. 2, the switch circuit 9a has an equivalent circuit including a contact S1, a resistor (on resistance: about several Ω) R1, and a capacitor (off capacitance: about 1 to 100 pF) C1, as shown in FIG. It consists of a semiconductor relay consisting of

  The auxiliary circuit 9b is connected in parallel to the switch circuit 9a and, as shown in FIG. 2, is composed of a series circuit in which a resistor R2 and a capacitor C2 are connected in series. In this example, the resistor R2 is assumed to have a capacity of, for example, about several ohms to several tens of ohms, and the capacitor C2 is assumed to have a capacity such that a high frequency of 100 kHz or more can pass therethrough. It is preferable to design it.

  The auxiliary circuit 9b is provided to solve the problem of waveform distortion and oscillation at the time of the AC connection in the first embodiment described above, and reduces the resonance frequency to a low band outside the transmission band where there is no influence. By lowering the resonance Q, the influence on the frequency characteristics is minimized.

  Here, in the offset adjusting device 1B of the second embodiment, FIG. 3 shows a frequency characteristic when the semiconductor relay of the switch circuit 9a is on, and a frequency characteristic when the semiconductor relay of the switch circuit 9a is off. The characteristics are shown in FIG. Note that the two-dot chain lines in FIGS. 3 and 5 show the frequency characteristics of only the capacitance that passes 100 kHz or more.

  In the offset adjustment device 1B of the second embodiment, when the semiconductor relay of the switch circuit 9a is on (contact S1: closed), signals from DC to high frequency are transmitted as in the first embodiment. It operates as an original offset adjustment device, and is DC-connected between input and output, and has a flat characteristic from low frequency to high frequency as shown in FIG.

  In the case of DC connection, the resistor R2 and the capacitor C2 are short-circuited, and only the resistor R1 is affected. Therefore, it is possible to reduce the performance deterioration by selecting a component whose on-resistance is as small as about several Ω as the resistor R1. it can.

  Further, in the offset adjustment device 1B of the second embodiment, when the semiconductor relay of the switch circuit 9a is off (contact S1: open), the auxiliary circuit 9b transmits the DC component transmitted from the input terminal 2. It operates as a level shift circuit for cutting and transmitting only high frequency components, and the connection between the input and the output is AC-connected via the capacitor C1. Then, as shown in FIG. 5, a pass characteristic close to the frequency characteristic of only the capacitance indicated by the two-dot chain line is obtained, and an AC connection close to ideal can be realized.

  In the example of FIG. 2, the auxiliary circuit 9b is configured as a series circuit in which the capacitor C2 and the resistor R2 are connected in series. However, the auxiliary circuit 9b may be configured only with the capacitor C2.

  As described above, according to the present embodiment, the switching unit 9 is connected between the first coil 6 and the combining circuit 7, and the semiconductor relay of the switching unit 9 is turned on (the contact S1 of the switching circuit 9a is opened). , The transmission of the DC component of the signal input from the input terminal 2 is cut, the circuit operates as a level shift circuit for the purpose of transmitting only the high-frequency component, and the connection between the input and output via the capacitor C1. AC connection. When the semiconductor relay of the switching section 9 is turned off (the contact S1 of the switch circuit 9a is closed), it operates as an original offset adjusting device for transmitting a signal from DC to high frequency, as in the conventional case. DC connection can be made between the outputs. Thereby, the AC connection and the DC connection can be realized with a simple configuration.

  Further, if the switching unit 9 employs a switching unit 9B in which a switching circuit 9a and an auxiliary circuit 9b are connected in parallel, as shown in FIG. 5, a pass characteristic close to the frequency characteristic of only the capacitance indicated by the two-dot chain line can be obtained. Thus, the possibility of causing waveform distortion and oscillation of the offset adjusting device is reduced, and an AC connection close to ideal can be realized.

  By the way, the offset adjusting device according to the present invention is not limited to the configurations shown in FIGS. That is, in FIGS. 1 and 2, an isolation circuit may be connected between the capacitor and the output terminal. In this case, the AC component of the input digital signal Di input to the input terminal 2 is transmitted to the output terminal 4 via the capacitor 3 and the isolation circuit, and the DC component and the low frequency component are extracted by the first coil 6. The signal is combined with a DC signal for bias and supplied to the output terminal 4 via the second coil 8. Further, the backflow of the low frequency component to the input terminal 2 side is prevented by the isolation circuit. As a result, the influence of a circuit connected to the output side, for example, reflection due to mismatch does not return to the input side, and a wide-band waveform transmission with little distortion is enabled.

  Further, it is preferable that the synthesizing circuit 7 of FIGS. 1 and 2 has a configuration including a current limiting circuit for protecting the overcurrent from occurring at the moment of the short circuit. Further, a configuration may be employed in which a resistor for output matching is connected between the combining circuit 7 and the second coil 8. In this case, the resistor allows the combined signal output from the combining circuit 7 to pass through the second coil 8 to the output terminal 4.

  Further, each of the synthesizing circuit 7 and the isolation circuit is configured to include a variable gain amplifier, and each of the synthesizing circuit 7 and the isolation circuit is output so that a digital signal having a designated amplitude value is output from an output terminal. The variable gain amplifier may be controlled by the control unit 10. Thus, not only an arbitrary DC offset can be given to the output digital signal, but also the amplitude can be set arbitrarily.

  The best mode of the offset adjusting apparatus and method according to the present invention has been described above, but the present invention is not limited by the description and the drawings according to this mode. That is, it goes without saying that all other forms, examples, operation techniques, and the like made by those skilled in the art based on this form are included in the scope of the present invention.

1 (1A, 1B) Offset adjuster 2 Input terminal 3 Capacitor 4 Output terminal 5 DC voltage generator 6 First coil 7 Synthesizing circuit 8 Second coil 9 (9A, 9B) Switching unit 9a Switch circuit 9b Auxiliary circuit 10 Control unit Di Digital signal (input)
Do digital signal (output)
R1, R2 Resistance C1, C2 Capacitor S1 Contact

Claims (2)

An input terminal (2) and an output terminal (4);
A capacitor (3) provided between the input terminal and the output terminal, for transmitting an AC component of the digital signal (Di) input to the input terminal to the output terminal;
A bias application coil (8) having one end connected to the output terminal;
A low-frequency extraction coil (6) having one end connected to the input terminal and passing a DC component and a low-frequency component of a digital signal input to the input terminal;
A DC voltage generator (5) for outputting a DC signal of an arbitrary voltage;
A DC signal output from the DC voltage generator is combined with a signal output from the other end of the low frequency extraction coil, and a signal obtained by the combination is combined with the other end of the bias application coil. A digital signal offset adjusting device (1) comprising a synthesizing circuit (7) for supplying
A switching unit (9) including a switch circuit (9a) including a semiconductor relay , connected in series between the low-frequency extraction coil and the synthesis circuit ;
A digital signal offset adjusting device, wherein an auxiliary circuit (9b) comprising a capacitor (C2) or a series circuit of the capacitor and a resistor (R2) is connected in parallel to the switch circuit of the switching unit . An input terminal (2) and an output terminal (4);
A capacitor (3) provided between the input terminal and the output terminal, for transmitting an AC component of the digital signal (Di) input to the input terminal to the output terminal;
A bias application coil (8) having one end connected to the output terminal;
A low-frequency extraction coil (6) having one end connected to the input terminal and passing a DC component and a low-frequency component of a digital signal input to the input terminal;
A DC voltage generator (5) for outputting a DC signal of an arbitrary voltage;
A DC signal output from the DC voltage generator is combined with a signal output from the other end of the low frequency extraction coil, and a signal obtained by the combination is combined with the other end of the bias application coil. A digital signal offset adjusting method using a digital signal offset adjusting device (1) comprising a synthesizing circuit (7) for supplying
Connecting a switching unit (9) including a switch circuit (9a) composed of a semiconductor relay in series between the low-frequency extraction coil and the synthesis circuit ;
Connecting an auxiliary circuit (9b) composed of a series circuit of a capacitor (C2) or a resistor and a resistor (R2) to the switch circuit of the switching unit in parallel. .

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