JP4256894B2 - Digital signal offset adjusting device and pulse pattern generator using the same - Google Patents

Description

  The present invention relates to a digital signal offset adjusting device and a pulse pattern generator using the same, and more particularly, a digital signal that outputs an arbitrary bias voltage applied to a digital signal used when testing various devices used in a communication system. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal offset adjusting device that employs a technique for enabling a wideband digital signal to be handled in an offset adjusting device and a pulse pattern generator using the same.

  The communication speed of a communication system using a digital signal has been increased year by year, extending from a conventional low-speed digital signal in the MHz band to a high-speed digital signal in the GHz band in recent years.

  Therefore, when testing various devices used in such a communication system, the pulse pattern generator generates a high-speed digital signal in the GHz band from a low-speed digital signal in the MHz band according to the input interface of the device to be tested. It is necessary to supply a digital signal that has been offset-adjusted with a bias voltage.

  As an example, when the output amplitude of the digital signal is 0.25 to 2 Vpp (2 mV step), the bias voltage is set to −2 to +2 V (1 mV step).

  FIG. 7 shows a configuration of a conventional digital signal offset adjusting apparatus 10 used for such a purpose.

  This apparatus is generally called “bias T”, and transmits the AC component Dac of the digital signal D input from the input terminal 10 a to the output terminal 10 b via the capacitor 11.

  Further, one end side of the bias applying coil 12 is provided at a terminal on the output terminal 10 b side of the capacitor 11.

  Then, by applying an arbitrary bias voltage Vb from the other end side of the bias applying coil 12, a digital signal D ′ in which the AC component Dac that has passed through the signal transmission capacitor 11 and the bias voltage Vb are superimposed is output terminal. 10b.

The bias T as described above is described in, for example, the following Patent Documents 1 and 2.
JP 2004-193275 A JP 2004-193866 A

  However, in the conventional digital signal offset adjusting device, in order to correctly transmit the waveform of the digital signal in the low frequency band, the capacitance of the signal transmission capacitor 11 connected between the input terminal 10a and the output terminal 10b. Must be increased, and the inductance of the bias applying coil 12 must be increased accordingly.

  In particular, in a test of various devices used in a communication system, in the case of a digital signal having a commonly used random pattern generated from a pulse pattern generator, there is a data pattern in which the same bit data continues, and the data The frequency included in the pattern may be lower than the bit rate of the digital signal itself.

  For this reason, as a digital signal offset adjusting device, even a digital signal having a bit rate of about several Mbps, it is necessary to transmit a low frequency component that is much lower than that, for example, up to several hundred Hz without loss.

  In order to transmit the low-frequency component without loss in this way, a large-capacity capacitor must be used as the signal transmission capacitor, and the inductance of the bias applying coil 12 must be increased accordingly.

  However, as described above, the signal transmission capacitor having a large capacity (for example, 100 μF) and the bias applying coil having a large inductance (for example, several tens of mH) inevitably have a large physical size. .

  This not only increases the overall cost of the digital signal offset adjusting device, but also makes it difficult to match the impedance of the high-frequency transmission line in the digital signal offset adjusting device, and the high-frequency component of the digital signal, particularly the signal component in the GHz band. This is a problem in that the waveform cannot be transmitted correctly and waveform distortion occurs.

  Depending on the pattern of the digital signal, a component close to a direct current component may be included.

  However, the conventional digital signal offset adjusting device also has a problem in that a component close to a direct current component that exists due to the pattern of the digital signal cannot be correctly transmitted and waveform distortion occurs.

  Therefore, the present invention has been made to solve the above-described problems caused by the prior art. For example, a wideband digital signal including a DC component and a low frequency component of several hundred Hz to a high frequency component in the GHz band can be obtained. It is an object of the present invention to provide a digital signal offset adjusting device and a pulse pattern generator using the digital signal offset adjusting device capable of correctly transmitting without causing waveform distortion.

In order to achieve the above object, according to a first aspect of the present invention,
An input terminal (20a) to which an input digital signal having a broadband frequency characteristic including a low frequency component, a direct current component and a high frequency component is input;
A DC voltage generator (25) for outputting a desired DC bias voltage;
An output digital signal obtained by adding the DC bias voltage output from the DC voltage generator (25) to the low frequency component, DC component, and high frequency component of the input digital signal input to the input terminal (20a). An output terminal (20b) for outputting;
A capacitor (21) connected between the input terminal (20a) and the output terminal (20b) and for allowing a high-frequency component of the input digital signal input to the input terminal (20a) to pass through the output terminal (20b). )When,
A first coil (23) having one end connected to the input terminal (20a) and passing the low frequency component and direct current component of the input digital signal to the other end;
A second coil (22) having one end connected to the output terminal (20b);
A first input terminal is connected to the other end side of the first coil (23), a second input terminal is connected to the DC voltage generator (25), and the second coil (22) An output end is connected to the other end side, and the low frequency component of the input digital signal passed to the other end side of the first coil (23) input to the first and second input ends and A synthesized signal obtained by synthesizing the DC component and the DC bias voltage output from the DC voltage generator (25) is passed through the other end of the second coil (22) from the output end. An operational amplifier (31a) for outputting to the output terminal (20b);
Connected between the second input end of the operational amplifier (31a) and a reference potential point (earth line) or between the second input end and the output end, the first coil (23) A frequency characteristic compensation circuit for compensating the frequency characteristic so that the gain of the operational amplifier (31a) increases as the frequency of the low-frequency component of the input digital signal passed to the other end of the input signal increases. 35)
A digital signal offset adjusting apparatus is provided.

In order to achieve the above object, according to the second aspect of the present invention,
When the first and second input terminals of the operational amplifier (31a) are a non-inverting input terminal (+) and an inverting input terminal (−), respectively.
An input matching resistor (31b) having a predetermined value is connected between the non-inverting input terminal (+) and the reference potential point (earth line),
A feedback resistor (31c) is connected between the output terminal and the inverting input terminal (−) of the operational amplifier (31a),
An output matching resistor (31d) having a predetermined value is connected between the output end of the operational amplifier (31a) and the other end side of the second coil (22).
A DC input resistor (31e) having a predetermined value is connected between the inverting input terminal (−) of the operational amplifier (31a) and the DC voltage generator (25).
The low-frequency component and the direct-current component of the input digital signal passed to the other end side of the first coil (23) input to the inverting input terminal (−) of the operational amplifier (31a) A subtracted synthesized signal obtained by subtracting and synthesizing the DC bias voltage from the DC voltage generator (25) inputted to the non-inverting input terminal (+) of the operational amplifier (31a) by the operational amplifier (31a). Is output from the output end of the operational amplifier (31a) to the output terminal (20b) via the other end of the second coil (22). An adjustment device is provided.

In order to achieve the above object, according to the third aspect of the present invention,
The DC input resistor (31e) connected between the inverting input terminal (−) of the operational amplifier (31a) and the DC voltage generator (25) has the operational amplifier (31) as the predetermined value. 31a) having a value equal to the value of the feedback resistor (31c) connected between the output terminal and the inverting input terminal (-),
The frequency characteristic compensation circuit (35) includes a capacitor (Cc) and a resistor (Rc) connected in series between the inverting input terminal (−) of the operational amplifier (31a) and the reference potential point (earth line). The digital signal offset adjusting device according to the second aspect is provided.

In order to achieve the above object, according to the fourth aspect of the present invention,
The frequency characteristic compensation circuit (35) is a series circuit of a coil (Lc) and a resistor (Rc ′) connected between the output terminal and the inverting input terminal (−) of the operational amplifier (31a). Configured,
The DC input resistor (31e) connected between the inverting input terminal (−) of the operational amplifier (31a) and the DC voltage generator (25) has the operational amplifier (31) as the predetermined value. The digital signal according to the second aspect, which has a value equal to a parallel combined resistance value of the feedback resistor (31c) of 31a) and the resistor (Rc ') of the frequency characteristic compensation circuit (35). A signal offset adjustment apparatus is provided.

In order to achieve the above object, according to the fifth aspect of the present invention,
The frequency characteristic compensation circuit (35 ′) is connected between the output terminal and the inverting input terminal (−) of the operational amplifier (31a) by the resistor (Rc ′) of the frequency characteristic compensation circuit (35 ′). The feedback resistor (31c) that is connected is also used, and the resistor (Rc ′) that also serves as the feedback resistor (31c) and the inverting input terminal (−) of the operational amplifier (31a) are connected in series. It is composed of a connected coil (Lc) and
The resistance value of the resistor (Rc ') of the frequency characteristic compensation circuit (35') that also serves as the feedback resistor (31c) of the operational amplifier (31a) is the DC input resistance (25) of the DC voltage generator (25). A digital signal offset adjusting device according to the fourth aspect is provided, which is set to be equal to the resistance value of 31c).

In order to achieve the above object, according to the sixth aspect of the present invention,
An input terminal (20a) to which an input digital signal having a broadband frequency characteristic including a low frequency component, a direct current component and a high frequency component is input;
A DC voltage generator (25) for outputting a desired DC bias voltage;
An output digital signal obtained by adding the DC bias voltage output from the DC voltage generator (25) to the low frequency component, DC component, and high frequency component of the input digital signal input to the input terminal (20a). An output terminal (20b) for outputting;
A capacitor (21) connected between the input terminal (20a) and the output terminal (20b) and for allowing a high-frequency component of the input digital signal input to the input terminal (20a) to pass through the output terminal (20b). )When,
A first coil (23) having one end connected to the input terminal (20a) and passing the low frequency component and direct current component of the input digital signal to the other end;
A second coil (22) having one end connected to the output terminal (20b);
A first input terminal is connected to the other end of the first coil (23), a second input terminal is connected to a reference potential point (earth line), and the first coil (23) is connected to the first coil (23). A first operational amplifier (40) for outputting a first inverted amplified signal obtained by inverting and amplifying the low frequency component and the DC component of the input digital signal passed to the other end side from an output end;
A first input terminal is connected to the DC voltage generator (25), a second input terminal is connected to the reference potential point (earth line), and the DC voltage output from the DC voltage generator (25). A second operational amplifier (41) for outputting a second inverted amplified signal obtained by inverting and amplifying the bias voltage from the output end;
A first input terminal is connected in common to each output terminal of the first and second operational amplifiers (40, 41), a second input terminal is connected to the base potential point (earth line), and A third operational amplifier (42) that inverts and amplifies a synthesized signal obtained by synthesizing the first and second inverted amplified signals and outputs the resultant signal from the output end to the other end of the second coil (22); ,
The first and third operational amplifiers (40, 42) are respectively connected between the first input terminals of the first and third operational amplifiers (40, 42) and the reference potential point (earth line). A component having a high frequency among the low frequency components of the input digital signal connected between the first input ends and the output ends of the input digital signal and passing to the other end of the first coil (23). First and second frequency characteristic compensation circuits (35a, 35b) for compensating frequency characteristics so that the gains of the first and third operational amplifiers (40, 42) are increased.
A digital signal offset adjusting apparatus is provided.

In order to achieve the above object, according to the seventh aspect of the present invention,
When the first and second input terminals of the first to third operational amplifiers (40, 41, 42) are an inverting input terminal (−) and a non-inverting input terminal (+), respectively.
Non-inverting input terminals (+) of the first to third operational amplifiers (40, 41, 42) are connected to the reference potential point (earth line),
An input matching resistor (31b) having a predetermined value is connected between the inverting input terminal (−) of the first operational amplifier (40) and the reference potential point (earth line),
Between each output terminal and each inverting input terminal (-) of the first to third operational amplifiers (40, 41, 42), first to third feedback resistors (31c1, 31c2, 31c3) are respectively provided. ) Is connected,
A DC input resistor (31e) having a predetermined value is connected between the inverting input terminal (-) of the second operational amplifier (41) and the DC voltage generator (25).
Between each output terminal of the first and second operational amplifiers (40, 41) and the inverting input terminal (-) of the third operational amplifier (42), each having a predetermined value. The first and second output matching resistors (31d1, 31d2) are connected,
A third output matching resistor (31d3) having the predetermined value is provided between the output end of the third operational amplifier (42) and the other end side of the second coil (22). By being connected,
The third and second amplifiers that invert and amplify an added combined signal obtained by adding and combining the first and second inverted amplified signals output from the output terminals of the first and second operational amplifiers (40 and 41). The digital signal offset adjusting device according to the sixth aspect, wherein the output is output from the output end of the operational amplifier (42) to the output terminal (20b) via the other end of the second coil (22). Is provided.

In order to achieve the above object, according to the eighth aspect of the present invention,
The DC input resistor (31e) connected between the inverting input terminal (−) of the second operational amplifier (41) and the DC voltage generator (25) has the predetermined value as the predetermined value. The second operational amplifier (41) has a value equal to the value of the second feedback resistor (31c2) connected between the output terminal and the inverting input terminal (-);
The first and second frequency characteristic compensation circuits (35a, 35b) are connected to the inverting input terminals (-) of the first and third operational amplifiers (40, 42) and the reference potential point (earth line). Are provided with capacitors (Cc1, Cc2) and resistors (Rc1, Rc2) connected in series, respectively, and the digital signal offset adjusting device according to the seventh aspect is provided.

In order to achieve the above object, according to the ninth aspect of the present invention,
The DC input resistor (31e) connected between the inverting input terminal (−) of the second operational amplifier (41) and the DC voltage generator (25) has the predetermined value as the predetermined value. The second operational amplifier (41) has a value equal to the value of the second feedback resistor (31c2) connected between the output terminal and the inverting input terminal (-);
The first and second frequency characteristic compensation circuits (35a, 35b) are connected between the output terminals and the inverting input terminals (−) of the first and third operational amplifiers (40), respectively. A digital signal offset adjusting device according to a seventh aspect is provided, wherein the digital signal offset adjusting device comprises a series circuit of coils (Lc1, Lc1) and resistors (Rc1, Rc2).

In order to achieve the above object, according to the tenth aspect of the present invention,
The first and second frequency characteristic compensation circuits (35a ', 35b') are respectively connected to the first and second frequency characteristic compensation circuits (35a ', 35b') by the resistors (Rc1, Rc2). The first and third feedback resistors (31c1, 31c3) connected between the output terminals of the first and third operational amplifiers (40, 42) and the inverting input terminals (-) are also used. Between the resistors (Rc1, Rc2) that also serve as the first and third feedback resistors (31c1, 31c3) and the inverting input terminals (-) of the first and third operational amplifiers (40, 42) A digital signal offset adjusting device according to the ninth aspect is provided, which is configured with coils (Lc1, Lc2) connected in series to each other.

In order to achieve the above object, according to the eleventh aspect of the present invention,
A digital signal output unit that outputs a digital signal having a desired pulse pattern including a data pattern in which the same bit data is continuous, which is a digital signal having a wideband frequency characteristic including a low frequency component, a direct current component, and a high frequency component. 101)
A digital signal offset adjusting device (20) connected to the digital signal output unit (101),
The digital signal offset adjusting device (20)
Input terminal (20a) for inputting a digital signal of a desired pulse pattern having a wide frequency characteristic including the low frequency component, direct current component and high frequency component output from the digital signal output unit (101) as an input digital signal When,
A DC voltage generator (25) for outputting a desired DC bias voltage;
An output digital signal obtained by adding the DC bias voltage output from the DC voltage generator (25) to the low frequency component, DC component, and high frequency component of the input digital signal input to the input terminal (20a). An output terminal (20b) for outputting;
A capacitor (21) connected between the input terminal (20a) and the output terminal (20b), and allowing a high-frequency component of the input digital signal input to the input terminal (20a) to pass through the output terminal;
A first coil (23) having one end connected to the input terminal (20a) and passing the low frequency component and direct current component of the input digital signal to the other end;
A second coil (22) having one end connected to the output terminal (20b);
A first input terminal is connected to the other end side of the first coil (23), a second input terminal is connected to the DC voltage generator (25), and the second coil (22) An output end is connected to the other end side, and the low frequency component of the input digital signal passed to the other end side of the first coil (23) input to the first and second input ends and A synthesized signal obtained by synthesizing the DC component and the DC bias voltage output from the DC voltage generator (25) is passed through the other end of the second coil (22) from the output end. An operational amplifier (31a) for outputting to the output terminal (20b);
The operational amplifier (31a) is connected between the second input terminal and the reference potential point (earth line) or between the second input terminal and the output terminal, and the first coil (23 The frequency characteristic compensation circuit compensates the frequency characteristic so that the gain of the operational amplifier (31a) increases as the frequency of the low frequency component of the input digital signal passed to the other end of the (35) and
A pulse pattern generator is provided.

In order to achieve the above object, according to a twelfth aspect of the present invention,
When the first and second input terminals of the operational amplifier (31a) of the digital signal offset adjusting device (20) are a non-inverting input terminal (+) and an inverting input terminal (−), respectively.
An input matching resistor (31b) having a predetermined value is connected between the non-inverting input terminal (+) of the operational amplifier (31a) and a reference potential point (earth line),
A feedback resistor (31c) is connected between the output terminal and the inverting input terminal (−) of the operational amplifier (31a),
An output matching resistor (31d) having a predetermined value is connected between the output end of the operational amplifier (31a) and the other end side of the second coil (22).
A DC input resistor (31e) having a predetermined value is connected between the inverting input terminal (−) of the operational amplifier (31a) and the DC voltage generator (25).
The low frequency component and the direct current component of the input digital signal passed to the other end of the first coil (23) input to the non-inverting input terminal (+) of the operational amplifier (31a); A subtracted synthesized signal obtained by subtracting and synthesizing the DC bias voltage from the DC voltage generator (25) input to the inverting input terminal (−) of the operational amplifier (31a) by the operational amplifier (31a). Is output from the output end of the operational amplifier (31a) to the output terminal (20b) via the other end of the second coil (22). Is provided.

In order to achieve the above object, according to the thirteenth aspect of the present invention,
The DC input resistor (31e) connected between the inverting input terminal (−) of the operational amplifier (31a) and the DC voltage generator (25) has the operational amplifier (31) as the predetermined value. 31a) having a value equal to the value of the feedback resistor (31c) connected between the output terminal and the inverting input terminal (-),
The frequency characteristic compensation circuit (35) includes a capacitor (Cc) and a resistor (Rc) connected in series between the inverting input terminal (−) of the operational amplifier (31a) and the reference potential point (earth line). The pulse pattern generator according to the twelfth aspect is provided.

In order to achieve the above object, according to the fourteenth aspect of the present invention,
The frequency characteristic compensation circuit (35) is a series circuit of a coil (Lc) and a resistor (Rc ′) connected between the output terminal and the inverting input terminal (−) of the operational amplifier (31a). Configured,
The DC input resistor (31e) connected between the inverting input terminal (−) of the operational amplifier (31a) and the DC voltage generator (25) has the operational amplifier (31) as the predetermined value. The pulse according to the twelfth aspect, having a value equal to a parallel combined resistance value of the feedback resistor (31c) of 31a) and the resistor (Rc ') of the frequency characteristic compensation circuit (35) A pattern generator is provided.

In order to achieve the above object, according to the fifteenth aspect of the present invention,
The DC input resistor (31e) has a value equal to the value of the feedback resistor (31c) as the predetermined value,
The frequency characteristic compensation circuit (35 ') is connected between the output terminal and the inverting input terminal (-) of the operational amplifier (31a) by a resistor (Rc') of the frequency characteristic compensation circuit (35 '). A coil (Lc) connected in series between the resistor (Rc ′) also used as the feedback resistor (31c) and the inverting input terminal (−). And consists of
The resistance value of the resistor (Rc ') of the frequency characteristic compensation circuit (35') that also serves as the feedback resistor (31c) of the operational amplifier (31a) is the DC input resistance (25) of the DC voltage generator (25). The pulse pattern generator according to the fourteenth aspect is provided, which is set to be equal to the resistance value of 31e).

In order to achieve the above object, according to the sixteenth aspect of the present invention,
A digital signal output unit that outputs a digital signal having a desired pulse pattern including a data pattern in which the same bit data is continuous, which is a digital signal having a wideband frequency characteristic including a low frequency component, a direct current component, and a high frequency component. 101)
A digital signal offset adjusting device (20) connected to the digital signal output unit (101),
The digital signal offset adjusting device (20)
Input terminal (20a) for inputting a digital signal of a desired pulse pattern having a wide frequency characteristic including the low frequency component, direct current component and high frequency component output from the digital signal output unit (101) as an input digital signal When,
A DC voltage generator (25) for outputting a desired DC bias voltage;
An output digital signal obtained by adding the DC bias voltage output from the DC voltage generator (25) to the low frequency component, DC component, and high frequency component of the input digital signal input to the input terminal (20a). An output terminal (20b) for outputting;
A capacitor (21) connected between the input terminal (20a) and the output terminal (20b) and for allowing a high-frequency component of the input digital signal input to the input terminal (20a) to pass through the output terminal (20b). )When,
A first coil (23) having one end connected to the input terminal (20a) and passing the low frequency component and direct current component of the input digital signal to the other end;
A second coil (22) having one end connected to the output terminal (20b);
A first input terminal is connected to the other end of the first coil (23), a second input terminal is connected to a reference potential point (earth line), and the first coil (23) is connected to the first coil (23). A first operational amplifier (40) for outputting a first inverted amplified signal obtained by inverting and amplifying the low frequency component and the DC component of the input digital signal passed to the other end side from an output end;
A first input terminal is connected to the DC voltage generator (25), a second input terminal is connected to the reference potential point (earth line), and the DC voltage output from the DC voltage generator (25). A second operational amplifier (41) for outputting a second inverted amplified signal obtained by inverting and amplifying the bias voltage from the output end;
A first input terminal is commonly connected to the output terminals of the first and second operational amplifiers (40, 41), a second input terminal is connected to the reference potential point (earth line), and the first A third operational amplifier (42) that inverts and amplifies a synthesized signal obtained by synthesizing the first and second inverted amplified signals and outputs the resultant signal from the output end to the other end of the second coil (22);
The first and third operational amplifiers (40, 42) are respectively connected between the first input terminals of the first and third operational amplifiers (40, 42) and the reference potential point (earth line). Of the low frequency components of the input digital signal that are connected between the first input terminals and the output terminals of the first digital coil 23 and pass to the other end of the first coil (23). First and second frequency characteristic compensation circuits (35a, 35b) for compensating frequency characteristics so that the gains of the first and third operational amplifiers (40, 42) are increased.
A pulse pattern generator is provided.

In order to achieve the above object, according to the seventeenth aspect of the present invention,
The first and second input terminals of the first to third operational amplifiers (40, 41, 42) of the digital signal offset adjusting device (20) are an inverting input terminal (−) and a non-inverting input, respectively. When at the end (+)
Non-inverting input terminals (+) of the first to third operational amplifiers (40, 41, 42) are connected to the reference potential point (earth line),
An input matching resistor (31b) having a predetermined value is connected between the inverting input terminal (−) of the first operational amplifier (40) and the reference potential point (earth line),
Between each output terminal and each inverting input terminal (-) of the first to third operational amplifiers (40, 41, 42), first to third feedback resistors (31c1, 31c2, 31c3) are respectively provided. ) Is connected,
A DC input resistor (31e) having a predetermined value is connected between the inverting input terminal (-) of the second operational amplifier (41) and the DC voltage generator (25).
Between each output terminal of the first and second operational amplifiers (40, 41) and the inverting input terminal (-) of the third operational amplifier (42), each having a predetermined value. The first and second output matching resistors (31d1, 31d2) are connected,
A third output matching resistor (31d3) having the predetermined value is provided between the output end of the third operational amplifier (42) and the other end side of the second coil (22). By being connected,
The third and second amplifiers that invert and amplify an added combined signal obtained by adding and combining the first and second inverted amplified signals output from the output terminals of the first and second operational amplifiers (40 and 41). A pulse pattern generator according to a sixteenth aspect is provided, wherein the pulse pattern generator outputs from the output end of the operational amplifier (42) to the output terminal (20b) via the other end side of the second coil (22). Is done.

In order to achieve the above object, according to the eighteenth aspect of the present invention,
The DC input resistor (31e) connected between the inverting input terminal (−) of the second operational amplifier (41) and the DC voltage generator (25) has the predetermined value as the predetermined value. The second operational amplifier (41) has a value equal to the value of the second feedback resistor (31c2) connected between the output terminal and the inverting input terminal (-);
The first and second frequency characteristic compensation circuits (35a, 35b) are connected to each inverting input terminal (−) of the first and second operational amplifiers (40, 41) and the reference potential point (earth line). Are provided with capacitors (Cc1, Cc2) and resistors (Rc1, Rc2) connected in series, respectively, to provide a pulse pattern generator according to the seventeenth aspect.

In order to achieve the above object, according to the nineteenth aspect of the present invention,
The DC input resistor (31e) connected between the inverting input terminal (−) of the second operational amplifier (41) and the DC voltage generator (25) has the predetermined value as the predetermined value. The second operational amplifier (41) has a value equal to the value of the second feedback resistor (31c2) connected between the output terminal and the inverting input terminal (-);
The first and second frequency characteristic compensation circuits (35a, 35b) are respectively connected between the output terminals and the inverting input terminals (-) of the first and third operational amplifiers (40, 42). A pulse pattern generator according to a seventeenth aspect is provided, which comprises a series circuit of connected coils (Lc1, Lc1) and resistors (Rc1, Rc2).

In order to achieve the above object, according to the twentieth aspect of the present invention,
The first and second frequency characteristic compensation circuits (35a ', 35b') are respectively connected by the resistors (Rc1, Rc2) of the first and second frequency characteristic compensation circuits (35a ', 35b'). The first and third feedback resistors (31c1, 31c3) connected between the output terminals of the first and third operational amplifiers (40) and the inverting input terminals (−) are also used, Between the resistors (Rc1, Rc2), which also serve as the first and third feedback resistors (31c1, 31c3), and the inverting input terminals (-) of the first and third operational amplifiers (40), in series. A pulse pattern generator according to a nineteenth aspect is provided, comprising a coil (Lc1, Lc2) connected thereto.

FIG. 1 is a connection diagram showing a configuration of a first embodiment of a digital signal offset adjusting apparatus according to the present invention. FIG. 2 is a diagram showing an example of transfer characteristics between input and output without compensation by the frequency characteristic compensation circuit of the digital signal offset adjusting apparatus according to the first embodiment shown in FIG. FIG. 3 is a diagram showing an example of transfer characteristics between input and output without compensation by the frequency characteristic compensation circuit of the digital signal offset adjusting apparatus according to the first embodiment shown in FIG. FIG. 4 is a diagram showing an example of transfer characteristics between input and output without compensation by the frequency characteristic compensation circuit of the digital signal offset adjusting apparatus according to the first embodiment shown in FIG. FIG. 5 is a diagram showing an example of transfer characteristics between input and output with compensation by the frequency characteristic compensation circuit of the digital signal offset adjusting apparatus according to the first embodiment shown in FIG. FIG. 6 is a connection diagram showing the configuration of the second embodiment of the digital signal offset adjusting apparatus according to the present invention. FIG. 7 is a connection diagram showing a configuration of a conventional digital signal offset adjusting apparatus. FIG. 8 is a connection diagram showing the configuration of the third embodiment of the digital signal offset adjusting apparatus according to the present invention. FIG. 9 is a connection diagram showing the configuration of the fourth embodiment of the digital signal offset adjusting apparatus according to the present invention. FIG. 10 is a connection diagram showing a configuration of a pulse pattern generator according to the fifth embodiment of the present invention. FIG. 11 is a connection diagram showing a configuration of a pulse pattern generator according to the sixth embodiment of the present invention. FIG. 12 is a connection diagram showing a configuration of a pulse pattern generator according to the seventh embodiment of the present invention. FIG. 13 is a connection diagram showing a configuration of a pulse pattern generator according to the eighth embodiment of the present invention. FIG. 14 is a connection diagram showing a configuration of a pulse pattern generator according to the ninth embodiment of the present invention. FIG. 15 is a connection diagram showing a configuration of a pulse pattern generator according to the tenth embodiment of the present invention. FIG. 16 is a connection diagram showing a configuration of a pulse pattern generator according to the eleventh embodiment of the present invention. FIG. 17 is a connection diagram showing a configuration of a pulse pattern generator according to the twelfth embodiment of the present invention.

  Hereinafter, several embodiments of a digital signal offset adjusting apparatus and a pulse pattern generator using the same according to the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a circuit configuration of a digital signal offset adjusting apparatus 20 according to the first embodiment of the present invention.

  The digital signal offset adjusting apparatus 20 according to the first embodiment shown in FIG. 1 has an input to which an input digital signal having a wideband frequency characteristic including a low frequency component, a direct current component, and a high frequency component is input. A DC voltage generator 25 that outputs a desired DC bias voltage, a DC voltage generator 25 that outputs a low frequency component, a DC component, and a high frequency component of an input digital signal input to the input terminal 20a. An output terminal 20b for outputting an output digital signal to which a bias voltage is applied is connected between the input terminal 20a and the output terminal 20b, and a high-frequency component of the input digital signal input to the input terminal 20a is output as the output signal. One end is connected to the capacitor 21 to be passed through the terminal and the input terminal 20a, and the low frequency component and direct input of the input digital signal are connected. A first coil 23 that passes the component to the other end side, a second coil 22 that is connected to the output terminal 20b at one end side, and a first input end that is connected to the other end side of the first coil 23; A second input terminal is connected to the DC voltage generator 25, an output terminal is connected to the other end of the second coil 22, and other than the first coil 23 input to the first and second input terminals. A synthesized signal obtained by synthesizing the low frequency component of the input digital signal passed to the end side and the DC component and the DC bias voltage output from the DC voltage generator 25 is output from the output end to the second coil 22. The operational amplifier 31a that outputs to the output terminal 20b via the end side, and between the second input terminal of the operational amplifier 31a and the reference potential point (earth line) or between the second input terminal and the output terminal Input connected and passed to the other end of the first coil 23 And a frequency characteristic compensation circuit 35 for compensating the frequency characteristic such that the gain of the operational amplifier 31a as the frequency is higher component of the low-frequency component of the digital signal increases.

  Specifically, as shown in FIG. 1, the input signal 20a is input from the input terminal 20a between the input terminal 20a and the output terminal 20b of the digital signal offset adjustment apparatus 20 in the same manner as the conventional digital signal offset adjustment apparatus. A capacitor 21 for passing an AC component (hereinafter referred to as a high frequency component) Da having a predetermined frequency or higher included in the digital signal D is connected.

  Further, one end side of a bias application coil (second coil) 22 is connected to the output terminal 20b.

  In addition, the input terminal 20a has, for example, a component that is greatly attenuated by the capacitor 21 (a component that cannot be passed) among the frequency components of the digital signal D input from the digital signal output unit of the pulse pattern generator described later, that is, One end of a low frequency extraction coil (first coil) 23 for extracting a signal Db including a component below the predetermined frequency (hereinafter referred to as a low frequency component) and a direct current component is connected.

  The inductance of the low frequency extracting coil 23 may be different from the inductance of the bias applying coil 22, but here it is assumed to be equal.

  The signal Db including the low frequency component and the DC component extracted by the low frequency extracting coil 23 is input to the synthesis circuit 30 together with the DC signal Ddc of the arbitrary voltage Vd output from the DC voltage generator 25.

  Here, the arbitrary voltage Vd output from the DC voltage generator 25 is set to a desired voltage by the bias voltage setting unit 26 as described later.

  The synthesizing circuit 30 subtracts and synthesizes the DC signal Ddc from the signal Db including the low frequency component and the DC component output from the low frequency extracting coil 23, and biases the subtracted synthesized signal obtained by the subtraction synthesis. It is for supplying to the other end side of the application coil 22.

  Here, as shown in FIG. 1, the synthesis circuit 30 has a configuration of a differential amplifier circuit using an operational amplifier 31a.

  That is, in this synthesis circuit 30, for example, a 50Ω input matching resistor 31b is provided between the non-inverting input terminal (+) as the first input terminal of the operational amplifier 31a and the reference potential point (earth line). Is connected.

  A feedback resistor 31c is connected between the output terminal of the operational amplifier 31a and the inverting input terminal (−) as the second input terminal.

  Further, a 50Ω output matching resistor 31d is connected between the output terminal of the operational amplifier 31a and the bias applying coil 22, for example.

  A DC signal Ddc is input from the DC voltage generator 25 to the inverting input terminal (−) of the operational amplifier 31a through a DC input resistor 31e having a resistance value equal to that of the feedback resistor 31c.

  Note that the output resistance (internal resistance) of the DC voltage generator 25 is negligibly small with respect to the feedback resistance 31c and the DC input resistance 31e, and is connected to a reference potential point (earth line) in terms of AC. It shall be.

  In the digital signal offset adjusting apparatus 20 configured as described above, if the compensation action of the frequency characteristic compensation circuit 35 described later is ignored, the operational amplifier 31a of the synthesis circuit 30 assumes that the output terminal 20b is terminated at 50Ω. Thus, the low frequency component Db including the attenuation due to the output matching resistor 31d acts as a common-mode buffer with a gain of 1.

  The operational amplifier 31a of the synthesis circuit 30 acts as an inverting buffer (attenuator) having a gain of 0.5 on the DC signal Ddc of the voltage Vd output from the DC voltage generator 25.

That is, the output signal Vo of the synthesis circuit 30 is
Vo = Db-Vd / 2
It becomes.

Here, if the low frequency component Db is the sum of the DC component Vdc and the AC component Vac, the output signal Vo is
Vo = Vac + (Vdc−Vd / 2)
It becomes.

  The output signal Vo is input to the other end side of the capacitor 21, that is, the output terminal 20b via the bias applying coil 22.

Therefore, the digital signal D ′ output from the output terminal 20b is
D ′ = Da + Vo = (Da + Vac) + (Vdc−Vd / 2)
It becomes.

  In the above equation, (Da + Vac) is an AC component, and (Vdc−Vd / 2) is a DC component. Therefore, the DC voltage generator is set so that the DC component (Vdc−Vd / 2) becomes a desired value at the output terminal 20b. The output voltage Vd of 25 is variably adjusted by the voltage setting unit 26 to set a desired bias voltage to the digital signal D ′, that is, the offset of the digital signal D ′ can be adjusted to a desired value. it can.

  On the other hand, the frequency range of the AC component Vac of the high frequency component Da and the low frequency component Db is determined by the capacitance C of the capacitor 21 and the inductance L of the bias applying coil 22 and the low frequency extracting coil 23.

  In this case, the capacitance C of the capacitor 21, the bias application coil 22, and the low frequency extraction coil are set so that the lower limit frequency of the frequency range of the high frequency component Da and the upper limit frequency of the AC component Vac of the low frequency component Db substantially coincide. A value of inductance L of 23 is set.

  Further, the synthesizing circuit 30 is provided with a frequency characteristic compensation circuit 35 for compensating for a gain reduction in a specific frequency region between signal paths from the input terminal 20a to the output terminal 20b.

  The frequency characteristic compensation circuit 35 includes a capacitor Cc and a resistor Rc connected in series between the inverting input terminal (−) of the operational amplifier 31a of the synthesis circuit 30 and the reference potential point (earth line). .

  That is, the frequency characteristic compensation circuit 35 lowers the impedance as the frequency becomes higher with respect to the AC component Vac of the low frequency component Db, and lowers the parallel combined impedance of the resistor Rc and the DC input resistor 31e, thereby reducing the parallel characteristic. The gain of the operational amplifier 31a determined by the ratio between the combined impedance and the feedback resistor 31c is increased.

  Further, the frequency characteristic compensation circuit 35 has a frequency near the upper limit of the AC component Vac due to the gain increase of the operational amplifier 31a and the signal attenuation (gain decrease) due to the inductance L of the bias applying coil 22 and the low frequency extracting coil 23. There is an effect of increasing the gain of the band (peaking effect).

  Here, the simulation result of the above embodiment will be described.

  2 to 4 show the input / output transfer characteristics when the inductance L of the bias applying coil 22 and the low frequency extracting coil 23 is 1 mH, 3 mH, and 5 mH when the frequency characteristic compensating circuit 35 is not included. The low-frequency part is shown.

  In FIG. 2 to FIG. 4, the high-frequency portion exceeding 1 MHz in the input / output transfer characteristics is omitted because it is flat up to a desired band in the GHz band, for example.

  Further, the capacitance C of the capacitor 21 used for obtaining the input / output transfer characteristics of FIGS. 2 to 4 is 10 μF.

  As is apparent from FIGS. 2 to 4, a frequency region in which the gain slightly decreases in the low frequency region is generated at any inductance value.

  The frequency region in which the gain is slightly reduced shifts to the low frequency side as the inductances of the bias applying coil 22 and the low frequency extracting coil 23 increase, so that the inductance of the low frequency extracting coil 23 and the bias applying coil 22 is increased. This is presumably due to the parallel resonance effect of the series portion of the capacitor and the capacitor 21.

  In this case, since the Q value of the parallel resonance circuit is low due to the insertion of the matching input resistor 31b having a low resistance, the gain reduction is slow.

  However, if the above-described gain reduction is compensated by the frequency characteristic compensation circuit 35, a flat input / output transfer characteristic can be obtained over a wider frequency range as shown in FIG.

  FIG. 5 shows a compensation of 0.12 μF as the capacitor Cc and 47Ω as the resistor Rc of the frequency characteristic compensation circuit 35 in order to increase the AC amplification of the operational amplifier 31a in the gain reduction region of the characteristic (L = 3 mH) of FIG. The input / output transfer characteristics between the input / output terminals 20a and 20b when the circuit 35 is used are shown.

  As apparent from comparing the input / output transfer characteristic shown in FIG. 5 with the input / output transfer characteristic without frequency characteristic compensation shown in FIG. 3, the gain as seen in the low frequency part of FIGS. The lowered region is eliminated, and almost completely flat characteristics are obtained over almost the entire region.

  Therefore, in the digital signal offset adjusting apparatus 20 using such a frequency characteristic compensation circuit 35, the DC component and the high frequency component from the low frequency component to several GHz among the frequency components included in the input digital signal are one. Signal transmission without waveform distortion.

  In addition, since the synthesis circuit 30 of the above embodiment is configured by a differential amplifier circuit using a single operational amplifier 31a, the circuit configuration is simple and can be reduced in size, and the influence of the DC offset error of the operational amplifier itself and its drift. One is sufficient, and stable DC bias supply can be performed.

(Second Embodiment)
FIG. 6 shows a circuit configuration of the digital signal offset adjusting apparatus 20 according to the second embodiment of the present invention.

  In FIG. 6, the same reference numerals are used for the same circuit components as those of the digital signal offset adjusting apparatus 20 of the first embodiment shown in FIG. 1, and the description thereof is omitted.

  That is, in the digital signal offset adjustment apparatus 20 of the second embodiment of the present invention shown in FIG. 6, the configuration of the frequency characteristic compensation circuit 35 'is the digital signal offset adjustment of the first embodiment shown in FIG. This is different from the configuration of the frequency characteristic compensation circuit 35 of the device 20.

  The frequency characteristic compensation circuit 35 of the digital signal offset adjusting apparatus 20 of the first embodiment shown in FIG. 1 described above includes the inverting input terminal (−) of the operational amplifier 31a of the synthesis circuit 30 and the reference potential point (earth line). This is a case where the capacitor Cc and the resistor Rc connected in series are connected in series.

  On the other hand, in the digital signal offset adjusting apparatus 20 of the second embodiment shown in FIG. 6, the frequency characteristic compensation circuit 35 'is connected between the output terminal of the operational amplifier 31a and the inverting input terminal (-). It comprises a series circuit of a coil Lc and a resistor Rc ′.

  In this case, the parallel combined resistance value of the feedback resistor 31c of the operational amplifier 31a and the resistor Rc 'of the frequency characteristic compensation circuit 35' is set to be equal to the resistance value of the DC input resistor 31e from the DC voltage generator 25. Just do it.

  That is, the frequency characteristic compensation circuit 35 'lowers the impedance as the frequency becomes higher with respect to the AC component Vac of the low frequency component Db, like the frequency characteristic compensation circuit 35 of FIG. By reducing the parallel combined impedance with 31e, the gain of the operational amplifier 31a determined by the ratio of the parallel combined impedance and the feedback resistor 31c is increased.

  The frequency characteristic compensation circuit 35 ′ of FIG. 6 configured as described above is similar to the frequency characteristic compensation circuit 35 of FIG. 1 in that the gain of the operational amplifier 31 a is increased and the inductance of the bias application coil 22 and the low frequency extraction coil 23 is increased. The signal attenuation (gain reduction) due to L has the effect of increasing the gain in the frequency band near the upper limit of the AC component Vac (peaking effect).

(Third embodiment)
FIG. 8 shows a circuit configuration of a digital signal offset adjusting apparatus 20 according to the third embodiment of the present invention.

  In FIG. 8, the same reference numerals are used for the same circuit components as those of the digital signal offset adjusting apparatus 20 of the second embodiment shown in FIG. 6, and the description thereof is omitted.

  That is, in the digital signal offset adjustment apparatus 20 of the third embodiment of the present invention shown in FIG. 8, the frequency characteristic compensation circuit 35 'is replaced with the digital signal offset adjustment apparatus of the second embodiment shown in FIG. 20 frequency characteristic compensation circuit 35 '.

  In the digital signal offset adjusting apparatus 20 of the second embodiment shown in FIG. 6, the frequency characteristic compensation circuit 35 'is connected between the output terminal and the inverting input terminal (-) of the operational amplifier 31a. This is a case where a series circuit of a coil Lc and a resistor Rc ′ is used.

  On the other hand, in the digital signal offset adjusting apparatus 20 of the third embodiment shown in FIG. 8, the frequency characteristic compensation circuit 35 ′ is replaced by the resistor Rc ′ of the frequency characteristic compensation circuit 35 ′ shown in FIG. The operational amplifier 31a is also used as a feedback resistor 31c, and a coil Lc is inserted in series between a resistor Rc 'also used as the feedback resistor 31c and the inverting input terminal (-) of the operational amplifier 31a.

  In this case, the resistance value of the resistor Rc ′ of the frequency characteristic compensation circuit 35 ′ also serving as the feedback resistor 31 c of the operational amplifier 31 a is set to be equal to the resistance value of the DC input resistor 31 c from the DC voltage generator 25. That's fine.

  That is, the frequency characteristic compensation circuit 35 ′ in FIG. 8 reduces the impedance as the frequency increases with respect to the AC component Vac of the low frequency component Db, similarly to the frequency characteristic compensation circuit 35 in FIG. By reducing the parallel combined impedance with the DC input resistor 31e, the gain of the operational amplifier 31a determined by the ratio of the parallel combined impedance and the resistor Rc that also serves as a feedback resistor is increased.

  The frequency characteristic compensation circuit 35 ′ of FIG. 8 configured in this way is similar to the frequency characteristic compensation circuit 35 of FIG. 6, and increases the gain of the operational amplifier 31 a and the inductance of the bias application coil 22 and the low frequency extraction coil 23. The signal attenuation (gain reduction) due to L has the effect of increasing the gain in the frequency band near the upper limit of the AC component Vac (peaking effect).

(Fourth embodiment)
FIG. 9 shows a circuit configuration of a digital signal offset adjusting apparatus 20 according to the fourth embodiment of the present invention.

  In FIG. 9, the same reference numerals are used for the same circuit components as those of the digital signal offset adjusting apparatus 20 of the first embodiment shown in FIG. 1, and the description thereof is omitted.

  That is, in the digital signal offset adjusting apparatus 20 of the fourth embodiment of the present invention shown in FIG. 9, the composition of the synthesis circuit 30 is the same as that of the digital signal offset adjusting apparatus 20 of the first embodiment shown in FIG. This is different from the configuration of the synthesis circuit 30.

  In the synthesis circuit 30 of the digital signal offset adjusting apparatus 20 of the first embodiment shown in FIG. 1 described above, the signal output from the low frequency extraction coil 23 and the DC signal Ddc from the DC voltage generator 25 are combined. This is a case where the subtractive synthesis is performed by two operational amplifiers 31a.

  On the other hand, in the digital signal offset adjusting apparatus 20 of the fourth embodiment shown in FIG. 9, the synthesis circuit 30 includes a signal output from the low frequency extraction coil 23 and a DC signal from the DC voltage generator 25. It is configured to add and synthesize Ddc using a plurality of operational amplifiers.

  Specifically, as shown in FIG. 9, in the synthesis circuit 30, the inverting input terminal (−) is connected to the other end side of the low frequency extraction coil 23, and the other end side of the low frequency extraction coil 23 is connected. A first operational amplifier 40 that outputs a first inverted amplified signal obtained by inverting and amplifying a low frequency component and a DC component of the input digital signal that is passed through from the output end, and an output end of the DC voltage generator 25. A second operational amplifier 41 connected to an inverting input terminal (−) and outputting a second inverted amplified signal obtained by inverting and amplifying the DC bias output from the DC voltage generator 25 from an output terminal; An inverting input terminal (-) is connected to each output terminal of the first and second operational amplifiers 40 and 41, and an added synthesized signal obtained by adding and synthesizing the first and second inverted amplified signals is inverted and amplified. From the output end to the other end of the bias applying coil 22 And a third operational amplifier 42 to force.

  Here, the normal rotation input terminals (+) of the first to third operational amplifiers 40, 41, and 42 are all connected to a reference potential point (earth line).

  Note that feedback resistors 31c1, 31c2, and 31c3 are connected between the output terminals of the first to third operational amplifiers 40, 41, and 42 and the inverting input terminals (−), respectively. Between the output terminals of the first and second operational amplifiers 40 and 41, the inverting input terminal (−) and the output terminal of the third operational amplifier 42, and the bias applying coil 22, respectively, are used for output matching. The resistors 31d1, 31d2, and 31d3 are connected.

  9 is connected to the inverting input terminals (−) of the first and third operational amplifiers 40 and 42, respectively, instead of the frequency characteristic compensation circuit 35 of FIG. The frequency characteristic is compensated so that the gain of the first and third operational amplifiers 40 and 42 increases as the frequency of the low-frequency component of the input digital signal passed to the other end of the coil 23 increases. The first and second frequency characteristic compensation circuits 35a and 35b are provided.

  These first and second frequency characteristic compensation circuits 35a and 35b are similar to the frequency characteristic compensation circuit 35 of the digital signal offset adjustment apparatus 20 of the first embodiment shown in FIG. In the first and third operational amplifiers 40 and 42, capacitors Cc1 and Cc2 and resistors connected between the inverting input terminals (−) and reference potential points (earth lines) of the operational amplifiers 40 and 42, respectively. It is composed of a series circuit with Rc1 and Rc2.

  That is, the signal output from the low frequency extraction coil 23 is inverted and amplified by the first operational amplifier 40, the DC signal Ddc from the DC voltage generator 25 is inverted and amplified by the second operational amplifier 41, and the first and The combined operational signal of the first and second inverted amplified signals from the output terminals of the second operational amplifiers 40 and 41 is inverted and amplified by the third operational amplifier 42, whereby the output terminal of the third operational amplifier 42 is output. To the other end of the bias applying coil 22 can be output as a combined signal of the first and second inverted amplification signals.

In this case, if the output signal Vo of the synthesis circuit 30 in FIG. 9 is under the same condition as that of the synthesis circuit 30 in FIG.
Vo = Db + Vd / 2
It becomes.

Here, if the low frequency component Db is the sum of the DC component Vdc and the AC component Vac, the output signal Vo is
Vo = Vac + (Vdc + Vd / 2)
It becomes.

  The output signal Vo is input to the other end side of the capacitor 21, that is, the output terminal 20b via the bias applying coil 22.

Therefore, the digital signal D ′ output from the output terminal 20b is
D '= Da + Vo = (Da + Vac) + (Vdc + Vd / 2)
It becomes.

  Since (Da + Vac) is an AC component and (Vdc + Vd / 2) is a DC component, the output voltage of the DC voltage generator 25 is set so that the DC component (Vdc + Vd / 2) becomes a desired value at the output terminal 20b. By setting Vd variably by the bias voltage setting unit 26, a desired bias voltage can be applied to the digital signal D ', that is, the offset of the digital signal D' can be adjusted to a desired value.

  On the other hand, the frequency range of the AC component Vac of the high frequency component Da and the low frequency component Db is determined by the capacitance C of the capacitor 21 and the inductance L of the bias applying coil 22 and the low frequency extracting coil 23.

  In this case, the capacitance C of the capacitor 21, the bias application coil 22, and the low frequency extraction coil are set so that the lower limit frequency of the frequency range of the high frequency component Da and the upper limit frequency of the AC component Vac of the low frequency component Db substantially coincide. A value of inductance L of 23 is set.

  The first and second frequency characteristic compensation circuits 35a and 35b provided in the synthesis circuit 30 are the first and third operational amplifiers 40, respectively, similarly to the frequency characteristic compensation circuit 35 shown in FIG. 42, the frequency characteristic is compensated so that the gain increases as the frequency increases with respect to the signal output from the low frequency extraction coil 23 and the first inverted amplification signal from the first operational amplifier 40. I have to.

  The first and second frequency characteristic compensation circuits 35a and 35b of FIG. 9 configured in this way are similar to the frequency characteristic compensation circuit 35 'of FIG. 6 and gain increase and bias of each operational amplifier 40 and 42, respectively. The signal attenuation (gain reduction) due to the inductance L of the application coil 22 and the low frequency extraction coil 23 has an effect of increasing the gain in the frequency band near the upper limit of the AC component Vac (peaking effect).

(Fifth embodiment)
FIG. 10 shows a circuit configuration of a digital signal offset adjusting apparatus 20 according to the fifth embodiment of the present invention.

  In FIG. 10, the same reference numerals are used for the same circuit components as those of the digital signal offset adjusting apparatus 20 of the fourth embodiment shown in FIG. 9, and the description thereof is omitted.

  That is, in the digital signal offset adjusting apparatus 20 of the fifth embodiment of the present invention shown in FIG. 10, the first and second frequency characteristic compensation circuits 35a 'and 35b' are the same as those shown in FIG. This is different from the configuration of the first and second frequency characteristic compensation circuits 35a and 35b of the digital signal offset adjusting device 20 of the embodiment.

  The first and second frequency characteristic compensation circuits 35a and 35b of the digital signal offset adjustment apparatus 20 of the fourth embodiment shown in FIG. 9 are respectively the first and third operational amplifiers 40 of the synthesis circuit 30. , 42 is constituted by a series circuit of capacitors Cc1, Cc2 and resistors Rc1, Rc2 connected between each inverting input terminal (−) of each operational amplifier 41, 42 and a reference potential point (earth line). Is the case.

  On the other hand, in the digital signal offset adjusting apparatus 20 of the fifth embodiment shown in FIG. 10, the first and second frequency characteristic compensation circuits 35 a ′ and 35 b ′ are connected to the first and third frequency characteristics of the synthesis circuit 30. Each of the operational amplifiers 40 and 42 includes a series circuit of coils Lc1 and Lc2 and resistors Rc1 and Rc2 connected between the output terminal and the inverting input terminal (−) of each operational amplifier 40 and 42, respectively. Yes.

  That is, the first and second frequency characteristic compensation circuits 35a ′ and 35b ′ in FIG. 10 are respectively similar to the frequency characteristic compensation circuit 35 shown in FIG. 1 in the first and third operational amplifiers 40 and 42. The frequency characteristics are compensated so that the gain increases as the frequency of the signal output from the low frequency extraction coil 23 and the first inverted amplification signal from the first operational amplifier 40 increases. .

  The first and second frequency characteristic compensation circuits 35a 'and 35b' of FIG. 10 configured as described above are similar to the frequency characteristic compensation circuit 35 'of FIG. 6 and gain increases of the operational amplifiers 40 and 42, respectively. And the signal attenuation (gain reduction) by the inductance L of the bias applying coil 22 and the low frequency extracting coil 23 have an effect of increasing the gain in the frequency band near the upper limit of the AC component Vac (peaking effect).

(Sixth embodiment)
FIG. 11 shows a circuit configuration of a digital signal offset adjusting apparatus 20 according to the sixth embodiment of the present invention.

  In FIG. 11, the same reference numerals are used for the same circuit components as those of the digital signal offset adjusting apparatus 20 of the fifth embodiment shown in FIG. 10, and the description thereof is omitted.

  That is, in the digital signal offset adjusting apparatus 20 of the sixth embodiment of the present invention shown in FIG. 11, the first and second frequency characteristic compensation circuits 35a ′ and 35b ′ are the same as the fifth frequency characteristic shown in FIG. This is different from the configuration of the first and second frequency characteristic compensation circuits 35a ′ and 35b ′ of the digital signal offset adjusting device 20 of the embodiment.

  In the digital signal offset adjusting apparatus 20 of the fifth embodiment shown in FIG. 10 described above, the first and second frequency characteristic compensation circuits 35 a ′ and 35 b ′ are the first and third operational amplifiers of the synthesis circuit 30. 40 and 42, respectively, are constituted by series circuits of coils Lc1 and Lc2 and resistors Rc′1 and Rc′2 connected between the output terminals and the inverting input terminals (−) of the operational amplifiers 40 and 42, respectively. This is the case.

  On the other hand, in the digital signal offset adjusting device 20 of the sixth embodiment shown in FIG. 11, the resistances of the first and second frequency characteristic compensation circuits 35a ′ and 35b ′ shown in FIG. The feedback resistors 31c1 and 31c3 of the operational amplifiers 40 and 42 are also used by the Rc1 and Rc2, and the coils Lc1 and Lc2 are connected in series between the resistors Rc1 and Rc2 and the inverting input terminals (−) of the operational amplifiers 40 and 42. It is configured to be inserted into.

  That is, the first and second frequency characteristic compensation circuits 35a 'and 35b' in FIG. 11 are respectively similar to the frequency characteristic compensation circuit 35 shown in FIG. 1 in the first and third operational amplifiers 40 and 42. The frequency characteristics are compensated so that the gain increases as the frequency of the signal output from the low frequency extraction coil 23 and the first inverted amplification signal from the first operational amplifier 40 increases. .

  The first and second frequency characteristic compensation circuits 35a 'and 35b' shown in FIG. 11 configured as described above are similar to the frequency characteristic compensation circuit 35 'shown in FIG. The signal attenuation (gain reduction) due to the inductance L of the bias applying coil 22 and the low frequency extracting coil 23 has an effect of increasing the gain in the frequency band near the upper limit of the AC component Vac (peaking effect).

  Therefore, according to the first to sixth embodiments of the present invention as described above, the problems due to the prior art are solved, and for example, a wideband digital signal including a high frequency component from a low frequency component of several hundred Hz to a GHz band. Can be correctly transmitted without causing waveform distortion.

(Seventh embodiment)
FIG. 12 shows a circuit configuration of a pulse pattern generator 100 of the seventh embodiment using the digital signal offset adjusting apparatus 20 of the first embodiment shown in FIG. 1 described above.

  The pulse pattern generator 100 according to the seventh embodiment of the present invention shown in FIG. 12 is basically a digital signal having a wideband frequency characteristic including a low frequency component, a direct current component and a high frequency component, and has the same bit. The digital signal output unit 101 outputs a digital signal having a desired pulse pattern including a data pattern in which data is continuous, and a digital signal offset adjustment device 20 connected to the digital signal output unit 101.

  Then, the digital signal offset adjusting device 20 receives a digital signal of a desired pulse pattern having a wide frequency characteristic including a low frequency component, a direct current component and a high frequency component output from the digital signal output unit 101 as an input digital signal. Input terminal 20a, a DC voltage generator 25 that outputs a desired DC bias voltage, and a DC voltage generator 25 that outputs a low frequency component, a DC component, and a high frequency component of an input digital signal input to the input terminal 20a. The output terminal 20b for outputting the output digital signal to which the DC bias voltage is applied is connected between the input terminal 20a and the output terminal 20b, and the high frequency component of the input digital signal input to the input terminal 20a is One end of the capacitor 21 is passed through the output terminal and the input terminal 20a is connected to the input terminal. A first coil 23 that passes the low-frequency component and direct-current component of the tall signal to the other end side, a second coil 22 that is connected to the output terminal 20 b at one end side, and a second coil 22 that is connected to the other end side of the first coil 23. 1 is connected, a second input terminal is connected to the DC voltage generator 25, an output terminal is connected to the other end of the second coil 22, and the first and second input terminals are input. A synthesized signal obtained by synthesizing the low frequency component and DC component of the input digital signal passed to the other end of the first coil 23 and the DC bias voltage output from the DC voltage generator 25 is output to the output terminal. To the output terminal 20b through the other end of the second coil 22, and between the second input terminal of the operational amplifier 31a and the reference potential point (earth line) or the second Connected between the input end and the output end of the first And a frequency characteristic compensation circuit 35 for compensating the frequency characteristic such that the gain of the frequency higher component operational amplifier 31a of the low-frequency component of the input digital signal is passed to the other end of the coil is increased.

  Specifically, as shown in FIG. 12, the pulse pattern generator 100 according to the seventh embodiment includes a digital signal output unit 101 and a pulse pattern of a digital signal output by the digital signal output unit 101. The pulse pattern designating unit 102 for designating and the digital signal offset adjusting device 20 of the first embodiment shown in FIG. 1 for adjusting the offset of the digital signal output by the digital signal output unit 101 are configured. Yes.

  In FIG. 12, the same reference numerals are used for the same circuit components as those of the digital signal offset adjusting apparatus 20 of the first embodiment shown in FIG. 1, and the description thereof is omitted.

A digital signal output unit 101 shown in FIG. 12 is used as a digital signal output unit mounted on, for example, an MP1761C pulse pattern generator manufactured by Anritsu Co., Ltd. and used for testing various devices used in a communication system. 8M bit length including a digital signal having a wideband frequency characteristic including a low frequency component, a direct current component and a high frequency component, including a digital signal of a predetermined random pattern including a data pattern in which the same bit data continues. Program pattern (corresponding to 6 frames of STM-64 / STM-192) Digital pulse signals of various patterns such as PRBS pattern, alternate pattern, zero insertion pattern from 2 ⁷ -1 to 2 ³¹ -1 Pulse pattern by designator 102 Can be output in accordance with the designation of the screen.

  The digital signal offset adjusting device 20 connected to the output terminal of the digital signal output unit 101 has the low frequency component output from the digital signal output unit 101 according to the designation of the pulse pattern by the pulse pattern designating unit 102, A digital signal having a desired pulse pattern having a wide frequency characteristic including a direct current component and a high frequency component is input as an input digital signal.

  That is, the pulse pattern generator 100 according to the seventh embodiment of the present invention shown in FIG. 12 is configured to output the low frequency component and the direct current component output from the digital signal output unit 101 according to the designation of the pulse pattern by the pulse pattern designating unit 102. In addition, the digital signal offset adjustment device 20 according to the first embodiment described above is used by the digital signal offset adjustment device 20 in which a digital signal having a desired pulse pattern having a wide frequency characteristic including a high frequency component is input to the input terminal 20a as an input digital signal. As in the case of the apparatus 20, for example, a wideband digital signal including a direct current component and a low frequency component of several hundred Hz to a GHz band to a high frequency component can be correctly transmitted without causing waveform distortion. Appropriately test various equipment used in Ukoto can.

(Eighth embodiment)
FIG. 13 shows a circuit configuration of a pulse pattern generator 100 according to an eighth embodiment of the present invention that uses the digital signal offset adjusting apparatus 20 according to the second embodiment shown in FIG.

  In FIG. 13, the same circuit components as those of the digital signal offset adjusting apparatus 20 of the second embodiment shown in FIG. 6 and the pulse pattern generator 100 of the seventh embodiment shown in FIG. The description will be omitted using the same reference numerals.

  Similarly to the pulse pattern generator 100 of the seventh embodiment of the present invention shown in FIG. 12 described above, the pulse pattern generator 100 of the eighth embodiment of the present invention shown in FIG. A digital signal of a desired pulse pattern having a wide frequency characteristic including the low frequency component, the direct current component, and the high frequency component, which is output according to the designation of the pulse pattern by the pulse pattern designating unit 102, is input to the input terminal 20a as an input digital signal. As with the case of the digital signal offset adjusting device 20 of the second embodiment described above, for example, the input digital signal offset adjusting device 20 converts a high frequency component from a direct current component and a low frequency component of several hundred Hz to a GHz band. Including wideband digital signals including waveform distortion It is possible to correctly transmit and testing of various devices for use in a digital communication system can be appropriately performed.

(Ninth embodiment)
FIG. 14 shows a circuit configuration of the pulse pattern generator 100 of the ninth embodiment according to the present invention using the digital signal offset adjusting device 20 of the third embodiment shown in FIG.

  In FIG. 14, the same circuit components as those of the digital signal offset adjusting device 20 of the third embodiment shown in FIG. 8 and the pulse pattern generator 100 of the seventh embodiment shown in FIG. The description will be omitted using the same reference numerals.

  Similarly to the pulse pattern generator 100 according to the seventh embodiment of the present invention shown in FIG. 12, the pulse pattern generator 100 according to the ninth embodiment of the present invention shown in FIG. A digital signal of a desired pulse pattern having a wide frequency characteristic including the low frequency component, the direct current component, and the high frequency component, which is output according to the designation of the pulse pattern by the pulse pattern designating unit 102, is input to the input terminal 20a as an input digital signal. In the same manner as the digital signal offset adjusting device 20 of the third embodiment described above, for example, the input digital signal offset adjusting device 20 converts a high frequency component from a DC component and a low frequency component of several hundred Hz to a GHz band. Including wideband digital signals including waveform distortion It is possible to correctly transmit and testing of various devices for use in a digital communication system 厶 can be appropriately performed.

(Tenth embodiment)
FIG. 15 shows a circuit configuration of a pulse pattern generator 100 according to the tenth embodiment of the present invention that uses the digital signal offset adjusting apparatus 20 according to the fourth embodiment shown in FIG.

  In FIG. 15, the same circuit components as those of the digital signal offset adjusting device 20 of the fourth embodiment shown in FIG. 9 and the pulse pattern generator 100 of the seventh embodiment shown in FIG. The description will be omitted using the same reference numerals.

  Similarly to the pulse pattern generator 100 of the seventh embodiment of the present invention shown in FIG. 12 described above, the pulse pattern generator 100 of the tenth embodiment of the present invention shown in FIG. A digital signal of a desired pulse pattern having a wide frequency characteristic including the low frequency component, the direct current component, and the high frequency component, which is output according to the designation of the pulse pattern by the pulse pattern designating unit 102, is input to the input terminal 20a as an input digital signal. As with the case of the digital signal offset adjusting device 20 of the fourth embodiment described above, for example, the input digital signal offset adjusting device 20 converts a high frequency component from a direct current component and a low frequency component of several hundred Hz to a GHz band. Generate wideband digital signals including waveform distortion It can be transmitted Ku correctly, including testing of various devices for use in a digital communication system can be appropriately performed.

(Eleventh embodiment)
FIG. 16 shows a circuit configuration of a pulse pattern generator 100 according to an eleventh embodiment of the present invention using the digital signal offset adjusting apparatus 20 according to the fifth embodiment shown in FIG.

  In FIG. 16, the same circuit components as those of the digital signal offset adjusting device 20 of the fifth embodiment shown in FIG. 10 and the pulse pattern generator 100 of the seventh embodiment shown in FIG. The description will be omitted using the same reference numerals.

  The pulse pattern generator 100 according to the eleventh embodiment of the present invention shown in FIG. 16 also uses the digital signal output unit 101 as in the pulse pattern generator 100 according to the seventh embodiment of the present invention shown in FIG. A digital signal of a desired pulse pattern having a wide frequency characteristic including a low frequency component, a direct current component, and a high frequency component, which is output according to the designation of the pulse pattern by the pulse pattern designation unit 102, is input to the input terminal 20a as an input digital signal. In the same manner as the digital signal offset adjusting device 20 of the fifth embodiment described above, the digital signal offset adjusting device 20 includes, for example, a direct current component and a high frequency component from a low frequency component of several hundred Hz to a GHz band. Wideband digital signal without waveform distortion It is possible to lay transmission, such as testing of the various apparatus used in a digital communication system can be appropriately performed.

(Twelfth embodiment)
FIG. 17 shows a circuit configuration of a pulse pattern generator 100 of the twelfth embodiment using the digital signal offset adjusting apparatus 20 of the sixth embodiment shown in FIG. 11 described above.

  In FIG. 17, the same circuit components as those of the digital signal offset adjusting device 20 of the sixth embodiment shown in FIG. 11 and the pulse pattern generator 100 of the seventh embodiment shown in FIG. The description will be omitted using the same reference numerals.

  The pulse pattern generator 100 according to the twelfth embodiment of the present invention shown in FIG. 17 also uses the digital signal output unit 101 as in the pulse pattern generator 100 according to the seventh embodiment of the present invention shown in FIG. A digital signal of a desired pulse pattern having a wide frequency characteristic including a low frequency component, a direct current component, and a high frequency component, which is output according to the designation of the pulse pattern by the pulse pattern designation unit 102, is input to the input terminal 20a as an input digital signal. In the same way as the digital signal offset adjusting device 20 of the sixth embodiment described above, the digital signal offset adjusting device 20 includes, for example, a direct current component and a high frequency component from a low frequency component of several hundred Hz to a GHz band. Wideband digital signal without waveform distortion It is possible to lay transmission, such as testing of the various apparatus used in a digital communication system can be appropriately performed.

  Therefore, according to the pulse pattern generator 100 of the seventh to twelfth embodiments of the present invention using the digital signal offset adjusting device 20 of the first to sixth embodiments of the present invention as described above, there are problems with the prior art. For example, various devices used in a digital communication system by appropriately transmitting a wideband digital signal including a low frequency component from a low frequency component of several hundred Hz to a high frequency component without causing waveform distortion are properly performed. It is possible to provide a pulse pattern generator that can be used.

  As described above, according to the digital signal offset adjusting apparatus according to the present invention, a capacitor is included among the frequency components included in the digital signal input to the input terminal as a digital signal for testing various devices used in the digital communication system. A low frequency component and a DC component that cannot pass are extracted by a low frequency extraction coil, combined with a bias DC signal, and supplied to the output terminal via the bias application coil to compensate for a gain reduction in a specific frequency region. Therefore, each frequency component of the input digital signal can be uniformly transmitted to the output terminal without using a large-capacity capacitor or large inductance coil as in the past, and a wide-band waveform with little distortion. Transmission is possible, and the digital signal offset adjustment device as a whole can be made inexpensive. It has the effect that the kill.

  Moreover, according to the pulse pattern generator using the digital signal offset adjusting device as described above, there is an effect that various devices used in the digital communication system can be appropriately tested.

  Therefore, the digital signal offset adjusting device and the pulse pattern generator using the same according to the present invention are useful as a digital signal offset adjusting device for testing a communication device or the like and a pulse pattern generator using the same.

Claims (20)

An input terminal to which an input digital signal having a broadband frequency characteristic including a low frequency component, a direct current component and a high frequency component is input;
A DC voltage generator for outputting a desired DC bias voltage;
An output terminal for outputting an output digital signal in which the DC bias voltage output from the DC voltage generator is added to the low-frequency component, DC component, and high-frequency component of the input digital signal input to the input terminal When,
A capacitor connected between the input terminal and the output terminal, and allowing a high-frequency component of the input digital signal input to the input terminal to pass through the output terminal;
A first coil having one end connected to the input terminal and passing the low frequency component and direct current component of the input digital signal to the other end;
A second coil having one end connected to the output terminal;
A first input end is connected to the other end side of the first coil, a second input end is connected to the DC voltage generator, and an output end is connected to the other end side of the second coil. The low frequency component and the direct current component of the input digital signal that is passed to the other end side of the first coil that is input to the first and second input ends are output from the direct current voltage generator. An operational amplifier that outputs a synthesized signal obtained by synthesizing the DC bias voltage to the output terminal from the output end via the other end side of the second coil;
The operational amplifier is connected between the second input end and a reference potential point or between the second input end and the output end, and passes through the other end side of the first coil. A frequency characteristic compensation circuit for compensating the frequency characteristic so that the gain of the operational amplifier increases as the frequency of the low frequency component of the input digital signal increases,
A digital signal offset adjustment apparatus comprising: When the first and second input terminals of the operational amplifier are a non-inverting input terminal and an inverting input terminal, respectively.
An input matching resistor having a predetermined value is connected between the non-inverting input terminal of the operational amplifier and the reference potential point.
A feedback resistor is connected between the output terminal and the inverting input terminal of the operational amplifier,
A resistor for output matching having a predetermined value is connected between the output end of the operational amplifier and the other end side of the second coil.
A resistance for DC input having a predetermined value is connected between the inverting input terminal of the operational amplifier and the DC voltage generator,
The low frequency component and the direct current component of the input digital signal passed to the other end side of the first coil input to the inverting input terminal of the operational amplifier and the non-inverting input terminal of the operational amplifier A subtracted synthesized signal obtained by subtracting and synthesizing the DC bias voltage from the input DC voltage generator with the operational amplifier is passed from the output end of the operational amplifier to the other end side of the second coil. The digital signal offset adjusting device according to claim 1, wherein the digital signal offset adjusting device outputs to the output terminal. The DC input resistor connected between the inverting input terminal of the operational amplifier and the DC voltage generator has a predetermined value between the output terminal and the inverting input terminal of the operational amplifier. Having a value equal to the value of the feedback resistor connected;
3. The digital circuit according to claim 2, wherein the frequency characteristic compensation circuit includes a capacitor and a resistor connected in series between the inverting input terminal of the operational amplifier and the reference potential point. 4. Signal offset adjustment device. The frequency characteristic compensation circuit includes a series circuit of a coil and a resistor connected between the output terminal and the inverting input terminal of the operational amplifier, and
The DC input resistor connected between the inverting input terminal of the operational amplifier and the DC voltage generator has the feedback resistor of the operational amplifier and the resistor of the frequency characteristic compensation circuit as the predetermined value. The digital signal offset adjusting device according to claim 2, wherein the digital signal offset adjusting device has a value equal to a parallel combined resistance value of the digital signal offset. The frequency characteristic compensating circuit also serves as the feedback resistor connected between the output terminal and the inverting input terminal of the operational amplifier by the resistor of the frequency characteristic compensating circuit, and also serves as the feedback resistor. It is composed of a resistor and a coil connected in series between the inverting input terminal,
The resistance value of the resistor of the frequency characteristic compensation circuit that also serves as the feedback resistor of the operational amplifier is set to be equal to the resistance value of the DC input resistor from the DC voltage generator. The digital signal offset adjusting device according to claim 4. An input terminal to which an input digital signal having a broadband frequency characteristic including a low frequency component, a direct current component and a high frequency component is input;
A DC voltage generator for outputting a desired DC bias voltage;
An output terminal for outputting an output digital signal in which the DC bias voltage output from the DC voltage generator is added to the low-frequency component, DC component, and high-frequency component of the input digital signal input to the input terminal When,
A capacitor connected between the input terminal and the output terminal, and allowing a high-frequency component of the input digital signal input to the input terminal to pass through the output terminal;
A first coil having one end connected to the input terminal and passing the low frequency component and direct current component of the input digital signal to the other end;
A second coil having one end connected to the output terminal;
The first input terminal is connected to the other end of the first coil, the second input terminal is connected to a reference potential point, and the input digital is passed to the other end of the first coil. A first operational amplifier that outputs a first inverted amplified signal obtained by inverting and amplifying the low frequency component and the DC component of a signal from an output end;
A first input terminal is connected to the DC voltage generator, a second input terminal is connected to the reference potential point, and is obtained by inverting and amplifying the DC bias voltage output from the DC voltage generator. A second operational amplifier that outputs an inverted amplified signal of 2 from the output end;
A first input terminal is commonly connected to the output terminals of the first and second operational amplifiers, a second input terminal is connected to the reference potential point, and the first and second inverted amplified signals are supplied to the first and second operational amplifiers. A third operational amplifier that inverts and amplifies the combined signal obtained by combining and outputs the resultant signal from the output end to the other end of the second coil;
Between each first input terminal of each of the first and third operational amplifiers and the reference potential point, or between each first input terminal and each output terminal of the first and third operational amplifiers. So that the gain of the first and third operational amplifiers increases as the frequency of the low-frequency component of the input digital signal that passes through the other end of the first coil increases. First and second frequency characteristic compensation circuits for compensating the frequency characteristic;
A digital signal offset adjustment apparatus comprising: When the first and second input terminals of the first to third operational amplifiers are an inverting input terminal and a non-inverting input terminal, respectively.
Respective non-inverting input terminals of the first to third operational amplifiers are connected to the reference potential point,
An input matching resistor having a predetermined value is connected between the inverting input terminal of the first operational amplifier and the reference potential point,
First to third feedback resistors are connected between the output terminals and the inverting input terminals of the first to third operational amplifiers, respectively.
A DC input resistor having a predetermined value is connected between the inverting input terminal of the second operational amplifier and the DC voltage generator,
Between each output terminal of the first and second operational amplifiers and the inverting input terminal of the third operational amplifier, there are first and second output matching resistors each having a predetermined value. Connected,
A third output matching resistor having the predetermined value is connected between the output end of the third operational amplifier and the other end side of the second coil.
The output of the third operational amplifier that inverts and amplifies the added combined signal obtained by adding and combining the first and second inverted amplified signals output from the output terminals of the first and second operational amplifiers. The digital signal offset adjusting apparatus according to claim 6, wherein the digital signal offset adjusting device outputs the signal from one end to the output terminal via the other end side of the second coil. The DC input resistor connected between the inverting input terminal of the second operational amplifier and the DC voltage generator has the predetermined value and the output terminal of the second operational amplifier as the inversion. Having a value equal to the value of the second feedback resistor connected to the input terminal;
The first and second frequency characteristic compensation circuits are configured by a capacitor and a resistor connected in series between each inverting input terminal of the first and third operational amplifiers and the reference potential point, respectively. The digital signal offset adjusting device according to claim 7, wherein the digital signal offset adjusting device is a digital signal offset adjusting device. The DC input resistor connected between the inverting input terminal of the second operational amplifier and the DC voltage generator has the predetermined value and the output terminal of the second operational amplifier as the inversion. Having a value equal to the value of the second feedback resistor connected to the input terminal;
Each of the first and second frequency characteristic compensation circuits includes a series circuit of a coil and a resistor connected between each output terminal and each inverting input terminal of each of the first and third operational amplifiers. 8. The digital signal offset adjusting apparatus according to claim 7, wherein The first and second frequency characteristic compensation circuits are connected to the output terminals and the inverting input terminals of the first and third operational amplifiers by the resistors of the first and second frequency characteristic compensation circuits, respectively. Both the first and third feedback resistors connected in between, the resistors also serving as the first and third feedback resistors, and the inverting input terminals of the first and third operational amplifiers, The digital signal offset adjusting device according to claim 9, wherein the digital signal offset adjusting device comprises a coil connected in series between the two. A digital signal output unit for outputting a digital signal having a desired pulse pattern including a data pattern in which the same bit data is continuous, which is a digital signal having a wideband frequency characteristic including a low frequency component, a direct current component and a high frequency component; ,
A digital signal offset adjusting device connected to the digital signal output unit,
The digital signal offset adjusting device is
An input terminal for inputting a digital signal of a desired pulse pattern having a wide frequency characteristic including the low frequency component, direct current component and high frequency component output from the digital signal output unit as an input digital signal;
A DC voltage generator for outputting a desired DC bias voltage;
An output terminal for outputting an output digital signal in which the DC bias voltage output from the DC voltage generator is added to the low-frequency component, DC component, and high-frequency component of the input digital signal input to the input terminal When,
A capacitor connected between the input terminal and the output terminal, and allowing a high-frequency component of the input digital signal input to the input terminal to pass through the output terminal;
A first coil having one end connected to the input terminal and passing the low frequency component and direct current component of the input digital signal to the other end;
A second coil having one end connected to the output terminal;
A first input end is connected to the other end side of the first coil, a second input end is connected to the DC voltage generator, and an output end is connected to the other end side of the second coil. The low frequency component and the direct current component of the input digital signal that is passed to the other end side of the first coil that is input to the first and second input ends are output from the direct current voltage generator. An operational amplifier that outputs a synthesized signal obtained by synthesizing the DC bias voltage to the output terminal from the output end via the other end side of the second coil;
Connected between the second input end of the operational amplifier and a base potential point or between the second input end and the output end, and passes through the other end of the first coil. A frequency characteristic compensation circuit for compensating the frequency characteristic so that the gain of the operational amplifier increases as the frequency of the low frequency component of the input digital signal increases,
A pulse pattern generator comprising: When the first and second input terminals of the operational amplifier of the digital signal offset adjusting device are a non-inverting input terminal and an inverting input terminal, respectively.
An input matching resistor having a predetermined value is connected between the non-inverting input terminal of the operational amplifier and a reference potential point,
A feedback resistor is connected between the output terminal and the inverting input terminal of the operational amplifier,
A resistor for output matching having a predetermined value is connected between the output end of the operational amplifier and the other end side of the second coil.
A resistance for DC input having a predetermined value is connected between the inverting input terminal of the operational amplifier and the DC voltage generator,
The low frequency component and the direct current component of the input digital signal passed to the other end side of the first coil input to the non-inverting input terminal of the operational amplifier and the inverting input terminal of the operational amplifier A subtracted synthesized signal obtained by subtracting and synthesizing the DC bias voltage from the input DC voltage generator with the operational amplifier is passed from the output end of the operational amplifier to the other end side of the second coil. 12. The pulse pattern generator according to claim 11, wherein the pulse pattern generator outputs to the output terminal. The DC input resistor connected between the inverting input terminal of the operational amplifier and the DC voltage generator has a predetermined value between the output terminal and the inverting input terminal of the operational amplifier. Having a value equal to the value of the feedback resistor connected;
13. The pulse according to claim 12, wherein the frequency characteristic compensation circuit includes a capacitor and a resistor connected in series between the inverting input terminal of the operational amplifier and the reference potential point. Pattern generator. The frequency characteristic compensation circuit includes a series circuit of a coil and a resistor connected between the output terminal and the inverting input terminal of the operational amplifier, and
The DC input resistor connected between the inverting input terminal of the operational amplifier and the DC voltage generator has the feedback resistor of the operational amplifier and the resistor of the frequency characteristic compensation circuit as the predetermined value. The pulse pattern generator according to claim 12, wherein the pulse pattern generator has a value equal to a parallel combined resistance value. The frequency characteristic compensating circuit also serves as the feedback resistor connected between the output terminal and the inverting input terminal of the operational amplifier by the resistor of the frequency characteristic compensating circuit, and also serves as the feedback resistor. It is composed of a resistor and a coil connected in series between the inverting input terminal,
The resistance value of the resistor of the frequency characteristic compensation circuit that also serves as a feedback resistor of the operational amplifier is set to be equal to the resistance value of the DC input resistor from the DC voltage generator. Item 15. The pulse pattern generator according to Item 14. A digital signal output unit for outputting a digital signal having a desired pulse pattern including a data pattern in which the same bit data is continuous, which is a digital signal having a wideband frequency characteristic including a low frequency component, a direct current component and a high frequency component; ,
A digital signal offset adjusting device connected to the digital signal output unit,
The digital signal offset adjusting device is
An input terminal for inputting a digital signal of a desired pulse pattern having a wide frequency characteristic including the low frequency component, direct current component and high frequency component output from the digital signal output unit as an input digital signal;
A DC voltage generator for outputting a desired DC bias voltage;
An output terminal for outputting an output digital signal in which the DC bias voltage output from the DC voltage generator is added to the low-frequency component, DC component, and high-frequency component of the input digital signal input to the input terminal When,
A capacitor connected between the input terminal and the output terminal, and allowing a high-frequency component of the input digital signal input to the input terminal to pass through the output terminal;
A first coil having one end connected to the input terminal and passing the low frequency component and direct current component of the input digital signal to the other end;
A second coil having one end connected to the output terminal;
The first input terminal is connected to the other end of the first coil, the second input terminal is connected to a reference potential point, and the input digital is passed to the other end of the first coil. A first operational amplifier that outputs a first inverted amplified signal obtained by inverting and amplifying the low frequency component and the DC component of a signal from an output end;
A first input terminal is connected to the DC voltage generator, a second input terminal is connected to the reference potential point, and is obtained by inverting and amplifying the DC bias voltage output from the DC voltage generator. A second operational amplifier that outputs an inverted amplified signal of 2 from the output end;
A first input terminal is commonly connected to the output terminals of the first and second operational amplifiers, a second input terminal is connected to the reference potential point, and the first and second inverted amplified signals are supplied to the first and second operational amplifiers. A third operational amplifier that inverts and amplifies the combined signal obtained by combining and outputs the resultant signal from the output end to the other end of the second coil;
Between each first input terminal of each of the first and third operational amplifiers and the reference potential point, or between each first input terminal and each output terminal of the first and third operational amplifiers. So that the gain of the first and third operational amplifiers increases as the frequency of the low-frequency component of the input digital signal that passes through the other end of the first coil increases. First and second frequency characteristic compensation circuits for compensating the frequency characteristic;
A pulse pattern generator comprising: When the first and second input terminals of the first to third operational amplifiers of the digital signal offset adjusting device are an inverting input terminal and a non-inverting input terminal, respectively.
Each non-inverting input terminal of the first to third operational amplifiers is connected to the reference potential point,
An input matching resistor having a predetermined value is connected between the inverting input terminal of the first operational amplifier and the reference potential point,
First to third feedback resistors are connected between the output terminals and the inverting input terminals of the first to third operational amplifiers, respectively.
A DC input resistor having a predetermined value is connected between the inverting input terminal of the second operational amplifier and the DC voltage generator,
Between each output terminal of the first and second operational amplifiers and the inverting input terminal of the third operational amplifier, there are first and second output matching resistors each having a predetermined value. Connected,
A third output matching resistor having the predetermined value is connected between the output end of the third operational amplifier and the other end side of the second coil.
The output of the third operational amplifier that inverts and amplifies the added combined signal obtained by adding and combining the first and second inverted amplified signals output from the output terminals of the first and second operational amplifiers. 17. The pulse pattern generator according to claim 16, wherein the pulse pattern generator outputs from the end to the output terminal via the other end side of the second coil. The DC input resistor connected between the inverting input terminal of the second operational amplifier and the DC voltage generator has the predetermined value and the output terminal of the second operational amplifier as the inversion. Having a value equal to the value of the second feedback resistor connected to the input terminal;
The first and second frequency characteristic compensation circuits are constituted by a capacitor and a resistor connected in series between each inverting input terminal of the first and second operational amplifiers and the reference potential point, respectively. The pulse pattern generator according to claim 17, wherein the pulse pattern generator is provided. The DC input resistor connected between the inverting input terminal of the second operational amplifier and the DC voltage generator has the predetermined value and the output terminal of the second operational amplifier as the inversion. Having a value equal to the value of the second feedback resistor connected to the input terminal;
Each of the first and second frequency characteristic compensation circuits includes a series circuit of a coil and a resistor connected between each output terminal and each inverting input terminal of each of the first and third operational amplifiers. The pulse pattern generator according to claim 17, wherein: The first and second frequency characteristic compensation circuits are connected to the output terminals and the inverting input terminals of the first and third operational amplifiers by the resistors of the first and second frequency characteristic compensation circuits, respectively. Both the first and third feedback resistors connected in between, the resistors also serving as the first and third feedback resistors, and the inverting input terminals of the first and third operational amplifiers, The pulse pattern generator according to claim 19, comprising a coil connected in series between the two.

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