JP2009100025A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing an increase in area and deterioration in distortion characteristics of an LNA (low noise amplifier), and achieving input impedance compensation. <P>SOLUTION: The semiconductor device 10 includes: a mode selecting section 14 for selecting a high gain mode and a low gain mode; a first amplifier 11 operating when the mode selecting section selects the high gain mode; a second amplifier 12 operating when the mode selecting section selects the low gain mode; and an impedance adjustment section 13 having a compensating element C131 for compensating the input capacity of the first amplifier 11, a switch SW132 for turning ON the compensating element C131 when the mode selecting section 14 selects the low gain mode, and a linear element C133 for releasing the distortion characteristics of the compensating element C131. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that switches a gain of an amplifier used in a communication device such as a wireless communication system.

  In order to realize highly accurate communication in a wireless communication system such as a portable terminal or a wireless LAN, it is necessary to accurately amplify and modulate / demodulate a signal to be transmitted / received. Therefore, each circuit block constituting the wireless communication system is good. It is important to satisfy proper NF characteristics and distortion characteristics.

  In general, the signal accuracy when a large signal is input depends mainly on the linearity of each circuit block. Therefore, the output signal level is adjusted so that the subsequent circuit block is not distorted by the large signal. There is a need. For example, in a low noise amplifier (hereinafter referred to as “LNA”), it is necessary to switch the gain so as to satisfy good NF characteristics.

  Conventional high-frequency circuit gain switching methods include a method 1 for switching an output current ratio flowing through a cascode stage in a cascode amplifier, a method 2 for changing the size of a degenerate inductor, and a method 3 for changing a circuit configuration according to a gain mode. and so on.

  Method 1 is applied to an amplifier having a cascode configuration. However, in Method 1, since the linearity mainly depends on the non-linearity of the transconductance (Gm) of the source grounded circuit of the input stage, the linearity itself does not change at high gain / low gain, and good NF Although characteristics can be obtained, there is a problem that the linearity when a large signal is input is impaired.

  Method 2 can improve the linearity. However, in Method 2, since it is necessary to perform input impedance compensation that compensates for fluctuations in input impedance caused by gain switching, there is a problem in that loss and the like increase due to the addition of a compensation circuit and NF characteristics deteriorate.

  In Method 3, several circuit configurations can be considered. For example, a configuration in which a common source circuit is used at high gain and a common gate circuit is used at low gain is conceivable. However, Method 3 has a large capacity for the purpose of ensuring an independent bias for each gain mode and making the effects of noise generated on the block side for the low gain mode invisible in the high gain mode. Since it is necessary to cut the signal path using a switch, the area increases, input impedance compensation is required, and it is easy to be affected by the nonlinearity of the switch, resulting in degradation of distortion characteristics on the low gain mode side. is there.

For example, Patent Document 1 discloses Method 3 for changing the circuit configuration in accordance with the gain mode. However, Patent Literature 1 does not realize input impedance compensation and does not suppress non-linearity in a switch situation.
JP 2002-124842 A

  An object of the present invention is to provide a semiconductor device that suppresses an increase in area and deterioration of distortion characteristics of an LNA and realizes input impedance compensation.

  According to the first aspect of the present invention, a mode selection unit that selects a high gain mode and a low gain mode, a first amplifier that operates when a high gain mode is selected by the mode selection unit, and the mode selection unit A second amplifier that operates when the low gain mode is selected by the first amplifier, a compensation element that compensates for the input capacitance of the first amplifier, and the compensation element is turned on when the low gain mode is selected by the mode selection unit. And a impedance adjustment unit having a linear element that relaxes the distortion characteristics of the compensation element.

  According to the present invention, it is possible to suppress an increase in area and deterioration of distortion characteristics of an LNA and realize input impedance compensation.

  Embodiments of the present invention will be described below with reference to the drawings. The following examples are one embodiment of the present invention and do not limit the scope of the present invention.

  First, Example 1 of the present invention will be described.

  FIG. 1 is a circuit diagram showing a circuit configuration of a semiconductor device 10 according to the first embodiment of the present invention.

  The semiconductor device 10 according to the first embodiment of the present invention includes a first amplifier (hereinafter referred to as “LNA”) 11, a second LNA 12, an impedance adjustment unit 13, and a mode selection unit 14.

  The first LNA 11 is an amplifier that operates when the high gain mode is selected by the mode selection unit 14. The first LNA 11 includes a capacitor C111, a MOS transistor M112, an inductor L113, and a switch SW114. The MOS transistor M112 is a common source circuit.

  The second LNA 12 is an amplifier that operates when the low gain mode is selected by the mode selection unit 14. The second LNA 12 includes a capacitor C121, a MOS transistor M122, a resonance circuit 123, and a switch SW124. The MOS transistor M122 is a gate ground circuit.

  The resonant circuit 123 includes an LC parallel resonant circuit including an inductor and a capacitor, an inductor, and a transistor so that the impedance is sufficiently high in a desired frequency band.

  In the semiconductor device 10 of FIG. 1, since the first LNA 11 is configured with a source grounded circuit including a MOS transistor M112 and the second LNA 12 is configured with a gate grounded circuit including a MOS transistor M122, the first LNA 11 is grounded in the high gain mode. The second LNA 12 operates as a gate ground circuit in the low gain mode.

  The impedance adjustment unit 13 includes a compensation element C131, a switch SW132, and a linear element C133.

  The compensation element C131 is an element for compensating the input capacitance (hereinafter referred to as “input impedance”) of the first LNA 11. The element value of the capacitance for compensating the input impedance of the compensation element C131 is set to be equal to the element value of the capacitor C111 which is the input impedance of the MOS transistor M112 of the first LNA11.

  The switch SW132 turns on the compensation element C131 when the mode selection unit 14 selects the low gain mode.

  The mode selection unit 14 selects a high gain mode and a low gain mode. The mode selection unit 14 includes switches SW141 and 142. When selecting the high gain mode, the mode selection unit 14 turns on the switch SW141 and turns off the switch SW142. When selecting the low gain mode, the mode selection unit 14 turns off the switch SW141 and turns on the switch SW142 so that the input impedance of the first LNA 11 becomes zero. The mode selection unit 14 makes the gate-source potential of the transistor M112 of the first LNA 11 or the transistor M122 of the second LNA 12 sufficiently low when switching between the high gain mode and the low gain mode.

  2A to 2C are schematic diagrams illustrating the operation of the semiconductor device 10 according to the first embodiment of the invention.

  2A partially shows the first LNA 11, the second LNA 12, and the impedance adjustment unit 13 of the semiconductor device 10 of FIG. The block A is the capacitor C121, the MOS transistor M122, and the resonance circuit 123 of the second LNA 12.

  FIG. 2B shows a state of the semiconductor device 10 of FIG. 2A in the high gain mode. As shown in FIG. 2B, the semiconductor device 10 according to the first embodiment of the present invention turns on the switch SW114 of the first LNA 11 and turns off the switch SW124 of the second LNA 12 and the switch SW132 of the impedance adjustment unit 13 in the high gain mode. So that only the source grounding circuit operates.

  FIG. 2C shows a state of the semiconductor device 10 of FIG. 2A in the low gain mode. 2C, in the semiconductor device 10 according to the first embodiment of the present invention, in the low gain mode, the switch SW124 of the second LNA 12 and the switch SW132 of the impedance adjustment unit 13 are turned on and the switch SW114 of the first LNA 11 is turned off. So that only the gate grounding circuit operates.

  Next, the input impedance of the semiconductor device 10 according to the first embodiment of the present invention will be described.

The input impedance Z _in of the first LNA 11 _in FIG. As shown in Equation 1, the real part of the input impedance Z _in is expressed as G _m L _s / C _gs .

The semiconductor device 10 according to the first embodiment of the present invention, when taking input matching for the desired characteristic impedance Z ₀ at the time of the high gain mode, in order to compensate for the input impedance change when switching the gain, the real part of the input impedance of the 2LNA12 also operate the MOS transistor M122 of the 2LNA12 such that _{Z 0.}

  According to the first embodiment of the present invention, the compensation element C131 having the same element value as the capacitor C111 of the first LNA 11 and the switch SW132 are connected in series to the linear element C133 connected between the gate and the source of the first LNA 11. The impedance adjustment unit 13 having a configuration in which blocks having the same configuration are connected in parallel can achieve a reduction in loss and a reduction in nonlinearity of the switch SW132 as compared with the prior art, and consequently an increase in area and distortion of the LNA. It is possible to suppress deterioration of characteristics and achieve input impedance compensation.

  Next, a second embodiment of the present invention will be described. The first embodiment of the present invention is an example of a semiconductor device including a second amplifier (hereinafter referred to as “LNA”) including a block including a capacitor, a MOS transistor, and a resonance circuit, but the second embodiment of the present invention includes an attenuator. It is an example of a semiconductor device provided with the 2nd LNA containing. In addition, the description about the content similar to Example 1 of this invention is abbreviate | omitted.

  FIG. 3 is a circuit diagram showing a circuit configuration of the semiconductor device 20 according to the second embodiment of the present invention.

  The semiconductor device 20 according to the second embodiment of the present invention includes a first LNA 21, a second LNA 22, an impedance adjustment unit 23, and a mode selection unit 24.

  The first LNA 21 is an amplifier that operates when the high gain mode is selected by the mode selection unit 24. The first LNA 21 includes a capacitor C211, a MOS transistor M212, an inductor L213, and a switch SW214. The MOS transistor M is a source grounding circuit.

  The second LNA 22 is an amplifier that operates when the low gain mode is selected by the mode selection unit 24. The second LNA 22 includes an attenuator ATT 221 and a switch SW 224. The second LNA 22 operates as a source ground circuit in the high gain mode, and operates to attenuate the gain by the attenuator ATT 221 in the low gain mode.

  The impedance adjustment unit 23 includes a compensation element C231, a switch SW232, and a linear element C233.

  The compensation element C231 is an element for compensating the input capacitance (hereinafter referred to as “input impedance”) of the first LNA 21. The element value of the capacitance for compensating the input impedance of the compensation element C231 is set to be equal to the element value of the capacitor C211 which is the input impedance of the MOS transistor M212 of the first LNA 21.

  The switch SW232 turns on the compensation element C231 when the low gain mode is selected by the mode selection unit 24.

  The mode selection unit 24 selects a high gain mode and a low gain mode. The mode selection unit 24 turns on a switch (not shown) when selecting the high gain mode. When selecting the low gain mode, the mode selection unit 24 turns off a switch (not shown) so that the input impedance of the first LNA 21 becomes zero.

  In the semiconductor device 20 according to the second embodiment of the present invention, in the high gain mode, the switch 214 of the first LNA 21 is turned on, the switch SW224 of the second LNA 22 and the switch SW232 of the impedance adjustment unit 23 are turned off, and only the source grounding circuit operates. Like that.

  In the semiconductor device 20 according to the second embodiment of the present invention, in the low gain mode, the switch SW214 of the first LNA 21 is turned off so that only the attenuator ATT221 of the second LNA 22 operates.

  FIG. 4 is a circuit diagram showing a configuration example of the attenuator ATT 221 of FIG.

  The attenuator ATT 221 in FIG. 3 is a π-type attenuator composed of elements 221A to 221C as shown in FIG. 4, for example. The attenuator ATT 221 is connected to the ground GND through the switch SW and controls to be turned on in the low gain mode. The attenuator ATT 221 performs control so that when the low gain mode is selected by the mode selection unit 24, the input impedance is the same as the real part (resistance component) when the high gain mode is selected.

  Note that the elements 221A to 221C may be capacitors or resistors.

The semiconductor device 20 according to the second embodiment of the present invention, when taking input matching for the desired characteristic impedance Z ₀ at the time of the high gain mode, in order to compensate for the input impedance change when switching the gain, the real part of the input impedance of the 2LNA22 also adjust the input impedance of the attenuator ATT221 of the 2LNA22 such that _{Z 0.}

  Further, when only the attenuator ATT 221 is inserted into the signal path and operated, only an isolation amount equivalent to the attenuation amount can be secured. For this reason, the attenuation is set such that an isolation amount that does not affect the circuit operation can be secured.

  According to the second embodiment of the present invention, even when the second LNA 22 is configured by the attenuator ATT221, the same effect as that of the first embodiment of the present invention can be obtained.

  Next, Embodiment 3 of the present invention will be described. The first embodiment of the present invention is an example of a semiconductor device including a second amplifier (hereinafter referred to as “LNA”) including a block including a capacitor, a MOS transistor, and a resonance circuit, but the third embodiment of the present invention includes a filter. It is an example of a semiconductor device provided with the 2nd LNA containing. In addition, the description about the content similar to Example 1, 2 of this invention is abbreviate | omitted.

  FIG. 5 is a circuit diagram showing a circuit configuration of the semiconductor device 30 according to the third embodiment of the present invention.

  The semiconductor device 30 according to the third embodiment of the present invention includes a first LNA 31, a second LNA 32, an impedance adjustment unit 33, and a mode selection unit 34.

  The first LNA 31 is an amplifier that operates when the high gain mode is selected by the mode selection unit 34. The first LNA 31 includes a capacitor C311, a MOS transistor M312, an inductor L313, and a switch SW314. The MOS transistor M312 is a source grounded circuit.

  The second LNA 32 is an amplifier that operates when the low gain mode is selected by the mode selection unit 34. The second LNA 32 includes a capacitor C321, a MOS transistor M322, a switch SW324, an inductor L325, and a tank 326. The MOS transistor M322 is a gate ground circuit.

  The filter composed of the inductor L325 and the tank 236 is controlled so that when the low gain mode is selected by the mode selection unit 34, the input impedance is the same as the real part (resistance component) when the high gain mode is selected. To do.

  In the semiconductor circuit 30 of FIG. 5, since the first LNA 31 is configured by a source grounded circuit including a MOS transistor M312 and the second LNA 32 is configured by a gate grounded circuit including a MOS transistor M322, the first LNA 31 is grounded in the high gain mode. The second LNA 32 operates as a gate ground circuit in the low gain mode.

  The impedance adjustment unit 33 includes a compensation element C331, a switch SW332, and a linear element C333.

  The compensation element C331 is an element for compensating the input capacitance (hereinafter referred to as “input impedance”) of the first LNA 31. The element value of the capacitance for compensating the input impedance of the compensation element C331 is set to be equal to the element value of the capacitor C311 that is the input impedance of the MOS transistor M312 of the first LNA 31.

  The switch SW332 turns on the compensation element C331 when the low gain mode is selected by the mode selection unit 34.

  The mode selection unit 34 selects a high gain mode and a low gain mode. The mode selection unit 34 includes switches SW341 and 342. When selecting the high gain mode, the mode selection unit 34 turns on the switch SW341 and turns off the switch SW342. When selecting the low gain mode, the mode selection unit 34 turns off the switch SW341 and turns on the switch SW342 so that the input impedance of the first LNA 31 becomes zero. The mode selector 34 makes the gate-source potential of the transistor M312 of the first LNA 31 or the transistor M322 of the second LNA 32 sufficiently low when switching between the high gain mode and the low gain mode.

The semiconductor device 30 according to the third embodiment of the present invention, when taking input matching for the desired characteristic impedance Z ₀ at the time of the high gain mode, in order to compensate for the input impedance change when switching the gain, the real part of the input impedance of the 2LNA32 also operate the MOS transistor M322 of the 2LNA32 such that _{Z 0.} Further, in the second LNA 32, an inductor L325 having the same element value as that of the inductor L313 that becomes invisible when the switch SW314 of the first LNA 31 is turned off is inserted between the terminals Y ′ to Z ′.

  The operation of the semiconductor device 30 according to the third embodiment of the present invention is the same as the operation of the semiconductor device 10 according to the first embodiment of the present invention, and a description thereof will be omitted.

  According to the third embodiment of the present invention, even when the second LNA 32 is configured by a filter including the inductor L325 and the tank 326, the same effect as that of the first embodiment of the present invention can be obtained.

FIG. 1 is a circuit diagram showing a circuit configuration of a semiconductor device 10 according to the first embodiment of the present invention. FIGS. 4A to 4C are schematic diagrams illustrating the operation of the semiconductor device 10 according to the first embodiment of the invention. It is a circuit diagram which shows the circuit structure of the semiconductor device 20 which concerns on Example 2 of this invention. FIG. 4 is a circuit diagram showing a configuration example of an attenuator ATT 221 in FIG. 3. It is a circuit diagram which shows the circuit structure of the semiconductor device 30 which concerns on Example 3 of this invention.

Explanation of symbols

10, 20, 30 Semiconductor devices 11, 21, 31 First LNA
12, 22, 32 2nd LNA
13, 23, 33 Impedance adjustment unit 14, 24, 34 Mode selection unit

Claims (5)

A mode selector for selecting a high gain mode and a low gain mode;
A first low noise amplifier that operates when a high gain mode is selected by the mode selection unit;
A second amplifier that operates when a low gain mode is selected by the mode selection unit;
An impedance having a compensation element for compensating the input capacitance of the first amplifier, a switch for turning on the compensation element when a low gain mode is selected by the mode selection unit, and a linear element for relaxing distortion characteristics of the compensation element A semiconductor device, comprising: an adjustment unit;   The semiconductor device according to claim 1, wherein the compensation element is an element having a capacitance equal to an input capacitance of the first amplifier.   3. The semiconductor device according to claim 1, wherein the second amplifier includes an attenuator that is connected to the first amplifier and operates when a low gain mode is selected by the mode selection unit.   The semiconductor device according to claim 1, wherein the second amplifier includes a filter that is connected to the first amplifier and the impedance adjustment unit and includes an inductor and a tank.   In the second amplifier, when the low gain mode is selected by the mode selection unit, the resistance component of the input impedance is equal to the resistance component of the input impedance when the high gain mode is selected by the mode selection unit. The semiconductor device according to claim 1, wherein the semiconductor device is controlled as follows.

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