JP2006167486A - Pinball game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine, capable of time control of timing, which is the same as before even if a CPU enters interrupt inhibit state. <P>SOLUTION: In a main control board and a put-out control board constituting a pachinko machine, at the time of backup operation due to power failure, the counter value DW of a counter 70 in a one-chip microcomputer is obtained, and every time the counter value DW reaches a predetermined value n1, switch detecting processing is performed to grasp the number of prize balls and the number of dispensed balls. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a ball game machine such as a pachinko machine, and more particularly to a game machine capable of managing the same time as before even when a CPU is in an interrupt disabled state.

  In general, a ball game machine such as a pachinko machine has a symbol start port provided on the game board, a symbol display means for stopping a plurality of symbols after changing them for a predetermined time, a prize winning means for driving the opening and closing plate, etc. It is configured with. When the detection switch provided at the symbol start port detects the passing of the game ball, the symbol display means causes the display symbols to fluctuate for a predetermined time, and then the special winning symbol functions when the special symbols are aligned and stopped. A profit state advantageous to the player is generated.

  In this type of gaming machine, the jackpot counter CT is realized by software, and when the jackpot probability is 1 / N, the jackpot counter CT is circulated within a numerical range of 0 to N-1. The value of the jackpot counter CT is extracted as a lottery random value RND on condition that the detection switch at the symbol start opening detects a game ball, and the extracted lottery random value RND matches the jackpot winning value Hit. In this case, control is performed so that the special symbols are arranged in a stopped state after the symbol display means is changed.

  In such a gaming machine, for the purpose of updating the jackpot counter CT at regular intervals, the value of the jackpot counter CT is updated in the interrupt control program by the timer interrupt, and a substantial part of the game control operation is performed. All are handled by the interrupt control program. Typically, as shown in FIG. 14, the game control program for realizing the game operation includes an infinite loop process ST41 repeated in an infinite loop, and an interrupt signal INT by a timer interrupt during the execution of the infinite loop process ST41. It consists of an interrupt process ST42 executed in response.

  By the way, there is a possibility that the power supply to the gaming machine may be suddenly cut off due to a power failure, etc., so in response to the drop in power supply voltage, we can effectively deal with such an unexpected situation and resume the game normally after power is restored. It is conceivable to apply a highest priority interrupt NMI (Non Maskable Interrupt) to a CPU (hereinafter referred to as a Z80 CPU equivalent) and save the game state in the interrupt processing program. In such an invention, necessary data is stored in the RAM area by interrupt processing in response to the NMI, the backup power is supplied to the RAM area to maintain the contents, and when the power supply voltage is restored, the backed up data is read. The game operation before the interruption is reproduced.

  Such an invention is excellent in that it can accurately reproduce a game interrupted by a power failure or the like, but further improvement is desired. In other words, when the highest priority interrupt NMI is applied to the CPU in response to the drop in the power supply voltage, the interrupt process is started regardless of the operating state of the CPU (except in a special case where the BUSREQ terminal is at the L level). On the other hand, since the subsequent CPU is in an interrupt disabled state, the problem is that time management by the timer interrupt INT cannot be performed in the interrupt processing program.

  Although it is possible to provide a dedicated hardware timer to deal with such problems, it is reasonable to add a dedicated timer circuit for a very rare situation such as a power outage. Not.

  The present invention has been made in view of such a problem, and even if the CPU is in an interrupt disabled state without adding another circuit element, it is possible to perform time management at the same timing as before. It is an object to provide a gaming machine.

  In order to solve the above problems, the present invention provides a payout control board for controlling a payout device for paying out a game ball to a player, a main control board for centrally controlling game operations, and the payout control board and the main control. Power supply monitoring means for monitoring the power supply voltage supplied to the substrate; backup means for storing information necessary for resuming the game operation by interrupting the game operation on condition that the power supply monitoring means detects an abnormal state; The main control board and / or the payout control board are equipped with a memory storing a game control program, a CPU that operates based on the control program, and a counter that circulates within a predetermined numerical range. In the main control board and / or the payout control board, during the operation of the backup means, the count value of the counter is acquired and the game ball passing is determined based on the acquired value. So that out perform the operation.

  During a game operation, it is preferable to perform a game ball passage detection operation in response to an interrupt signal generated from the counter every time the count value reaches a predetermined value. In addition, before or after the operation of detecting the passing of the game ball, it is typical to execute a process of waiting for the value to reach a predetermined value while acquiring the count value.

  As described above, according to the present invention, it is possible to realize a gaming machine capable of managing time at the same timing as before even when the CPU is in an interrupt disabled state without adding other circuit elements. .

  Hereinafter, an embodiment of the present invention will be described based on a card-type ball game machine which is an embodiment of the present invention. FIG. 1 is a perspective view showing a pachinko machine 2 according to the present embodiment, and FIG. 2 is a side view of the pachinko machine 2.

  The pachinko machine 2 shown in FIG. 1 is a rectangular frame-shaped wooden outer frame 3 that is detachably mounted on the island structure and a hinge H that is fixed to the outer frame 3 before being pivotably mounted. It consists of a frame 4. A plurality of pachinko machines 2 are arranged in the length direction of the island structure of the pachinko hall while being electrically connected to the card-type ball lending machine 1.

  A game board 5 is detachably attached from the back side to the front frame 4 pivotally attached to the outer frame 3 via a hinge H, and a glass door 6 having a window portion and a front side corresponding to the front side of the game board 5. A face plate 7 is pivotally attached to each other so as to be freely opened and closed. The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and launching means 10 at the lower part of the front frame 4. And a firing handle 11 are provided.

  The launching means 10 includes a launching handle 11 that can be rotated, and a launching motor that launches a game ball with a striking rod 12 (FIG. 4) with a striking force corresponding to the pivoting angle of the launching handle 11. . On the right side of the upper plate 8, there is provided an operation panel 13 for a ball lending operation for the card-type ball lending machine 1, and on this operation panel 13, a card remaining amount display portion 13a for displaying the remaining amount of the card with a three-digit number. And a ball lending switch 13b for instructing lending of game balls for a predetermined amount, and a return switch 13c for instructing to return the card at the end of the game.

  As shown in FIG. 3, the game board 5 is provided with a guide rail 15 made of a metal outer rail and an inner rail in a substantially annular shape, and a color liquid crystal is provided in the game area 5 a inside the guide rail 15. Display 16, symbol starting means (symbol starting and winning means) 17, open / close type winning means (large winning means) 18, a plurality of normal winning means 19 (in addition to the upper normal winning means 19, both the left and right sides of the opening / closing type winning means 18 Six normal winning means 19) and two gates 20 (passage openings) are arranged at predetermined positions.

  The liquid crystal display 16 functions as a first symbol display means 22 that displays a changing symbol and also displays a background image, moving images of various characters, and the like. The first symbol display means 22 displays background images and characters in an animated manner, and has three (left, middle, and right) symbol display portions 22a to 22c arranged in the left-right direction. On the condition that the ball wins, the display symbols of the symbol display units 22a to 22c are variably displayed (scrolled) for a predetermined time, and based on the lottery result corresponding to the winning timing of the game ball to the symbol starting means 17. Stop at the determined stop symbol pattern.

  A normal winning means 19 and a second symbol display means 23 are provided immediately above the liquid crystal display 16. The second symbol display means 23 has a normal symbol display unit for displaying one normal symbol. When a game ball that has passed through the gate 20 is detected, the display symbol of the normal symbol display unit fluctuates for a predetermined time, A stop symbol determined by a random number for lottery drawn at the time the game ball passes through the gate 20 is displayed and stopped. The symbol starting means 17 is an electric tulip having a pair of left and right opening and closing claws 17a that can be opened and closed. When the stop symbol after the change of the second symbol display means 23 hits and the symbol is displayed, the opening and closing claws 17a It is easy to win a prize by opening for a predetermined time.

  The open / close-type winning means 18 includes an opening / closing plate 18a that can be opened forward, and when the stop symbol after the fluctuation of the first symbol display means 22 is a winning symbol such as “777”, a special game called “big hit” is started. The opening / closing plate 18a is opened to the front side. There is a specific area 18b inside the openable winning means 18, and when the winning ball passes through the specific area 18b, the special game is continued. Here, the special game state corresponds to a state advantageous to the player.

  After the opening / closing plate 18a of the open / close winning means 18 is opened, when a predetermined time elapses, or when a predetermined number (for example, 10) of gaming balls wins and the opening / closing plate 18a is closed, the gaming ball is in the specific area 18b. If it has not passed, the special game ends. However, if it has passed the specific area 18b, the special game is continued up to, for example, 16 times, and is controlled in a state advantageous to the player.

  As shown in FIG. 4, on the back side of the front frame 4, a back mechanism plate 30 that presses the game board 5 from the back side is detachably mounted. The back mechanism plate 30 has an opening 30a formed on the top side thereof. A prize ball tank 33 and a tank rail 34 extending from the prize ball tank 33 are provided. Dispensing means 35 connected to the tank rail 34 is provided on the side of the back mechanism plate 30. A passage unit 36 connected to 35 is provided. The game balls paid out from the payout means 35 are paid out to the upper plate 8 from the upper plate discharge port 8a (FIG. 1) via the passage unit 36.

  The opening 30a of the back mechanism plate 30 is fitted with a back cover 37 mounted on the back side of the game board 5 and a winning ball discharge basket (not shown) for discharging the winning game balls to the winning means 17-19. Are combined. A main control board 39 is disposed inside a case 38 attached to the back cover 37, and a symbol control board 40 is disposed on the front side thereof (FIG. 2). Below the main control board 39, a lamp control board 42 is provided in a case 41a attached to the back cover 37, and a sound control board 43 is provided in a case 41b adjacent to the case 41a.

  A power supply board 45 and a payout control board 46 are provided inside the case 44 mounted on the back mechanism plate 30 below the cases 41a and 41b. As shown in FIG. 3, a power switch 80 and an initialization switch 85 are arranged on the power board 45. Cases 44 are notched at portions corresponding to these switches 80 and 85, and each of the switches 80 and 85 can be operated simultaneously with a finger.

  A launch control board 48 is provided inside the case 47 attached to the rear side of the launch means 10. These control boards 39 to 40, 42 to 43, 45 to 46, and 48 are independent boards, and the control boards 39, 40, 42, 43, and 46 excluding the power supply board 45 and the launch control board 48 have one chip. A computer circuit including a microcomputer is mounted, and the main control board 39 and the other control boards 40, 42, 43, 46 are electrically connected via a connector with a plurality of signal lines.

  As shown in FIG. 5, the main control board 39 and the other control boards 40, 42, 43, 46 are electrically connected via a connector with a plurality of signal lines, and each control board is connected to the main control board 39. A control command for executing a predetermined game operation can be transmitted to 40, 42, 43, and 46 by one-way communication. By adopting the one-way communication of the control command, fraud can be surely prevented, the control load on the main control board 39 can be remarkably reduced, and transmission control can be simplified.

  The main control board 39 is supplied with game board information such as a switch signal from the normal winning opening 19, the starting winning opening 17, and the gate 20 via a relay board (circuit board for relaying signals) (not shown). On the other hand, the payout control board 46 is supplied with signals of a ball lending counting switch, a prize ball counting switch, a lower tray switch, and an out-of-supply detection switch via the relay board 50. Among these, the signal of the prize ball counting switch is also supplied to the main control board 39 via the relay board 50. The payout control board 46 drives a game ball payout motor M via the relay board 50.

  FIG. 6 is an exploded perspective view of the payout cassette CA for paying out game balls, and specifically illustrates the payout means 35 shown in FIG. As shown in the figure, the payout cassette CA (the payout means 35) includes a payout motor M, a payout rotating body 51 rotated by the payout motor M, and a switching blade 52 that is switched according to whether the ball is in a lending state or a winning ball state. It consists of left and right ball lending counting switches 53a and 53b, left and right prize ball counting switches 54a and 54b, and the like. The game balls that have moved on the left and right guide paths 55 a and 55 b are captured by the left and right holding portions H of the payout rotator 51, and are led to the upper plate 8 according to the rotation of the payout rotator 51.

  FIG. 7 illustrates a state in which the switching blade 52 is positioned on the prize ball side, and the number of prize balls is counted by the prize ball counting switch 54. Note that the game balls on the left and right guide paths 55a and 55b are derived in accordance with the rotation of the payout rotating body 51 and normally pass the position of the counting switch 54 within 100 mS. The passing of the game ball is counted by the left and right counting switches 54a and 54b, respectively, and then the state of FIG. 7 (a) is shifted to the state of FIG. 7 (b) when the prize ball operation is completed. The ball lending operation is the same. As shown in FIG. 8, the lending ball number is counted by the ball lending counting switch 53 in the state where the switching blade 52 is located on the ball lending side. The game balls on the left and right guide paths 55a and 55b are counted by the left and right counting switches 53a and 53b, respectively. Thereafter, when the ball lending operation is completed, the state of FIG. 8 (a) is shifted to the state of FIG. 8 (b).

  Since all of the control boards 39, 40, 42, 53, and 46 shown in FIG. 5 have substantially the same circuit configuration, the main control board 39 will be described as a representative. FIG. 9 is a block diagram showing a circuit configuration of the main control board 39. As shown in the figure, the main control board 39 includes a CPU circuit 60 composed of a one-chip microcomputer, a system clock generator 61 that generates a clock signal having a frequency that is an integral multiple of the system clock CK supplied to the CPU, A decode circuit 62 that generates a chip select signal for each part based on an address signal, an output port circuit 63 for outputting data from the CPU, an input port circuit 64 for the CPU to capture external data, and each control board An output drive circuit 65 that outputs commands and the like, and a switch input circuit 66 that inputs ON / OFF states of switches of each part of the game board are mainly configured.

  Specifically, the one-chip microcomputer 60 includes a CPU equivalent to Z80 (Zilog), a ROM (Read Only Memory), a RAM (Random Access memory), a counter unit, and the like. FIG. 10A illustrates a specific configuration of the counter unit built in the one-chip microcomputer 60. As shown in FIG. 10A, the counter unit of the one-chip microcomputer 60 receives a clock pulse Φ having a pulse period τ and decrements (−1) and holds a preset value N of the down counter 70. An initial value register 71, an interrupt control unit 72 that outputs an interrupt signal INT to the CPU when the count value DW (8-bit length) of the down counter reaches zero, an interface unit 73 that is a relay unit to the CPU, and the like. Configured.

  In this embodiment, the preset value N is set to 125, and the pulse period τ of the clock pulse Φ is set to 16 μS. Therefore, when T = τ × N = 16 × 125 μS = 2 mS has elapsed from the start of the operation of the down counter 70, the counter value DW of the down counter 70 becomes zero, and a timer interrupt is applied to the CPU inside the one-chip microcomputer. In this embodiment, the game control operation is intermittently executed every T (= 2 mS) using this interrupt signal INT (Maskable Interrupt). Note that after the value of the down counter 70 becomes zero, the preset value N (= 125) is reset and the countdown operation is continued.

  As shown in the figure, the down counter 70 and the CPU are connected via the interface unit 73, so that the CPU can read the count value DW of the down counter 70 with an IN command or an LD command as necessary. Therefore, even after the CPU is in the interrupt disabled state, the CPU can perform time management by grasping the value of the down counter 70. That is, since the pulse period τ of the clock pulse Φ is 16 μS, it is possible to grasp that the time of M × τ has elapsed by the transition amount (decrease number M) of the count value DW of the down counter 70 read by the CPU. Time management is possible without providing a hardware timer.

  For example, when it is desired to repeat the processing of the processing time P (shown by the shaded square in FIG. 10) at regular time intervals (T), the CPU always monitors the count value DW of the down counter 70 and counts the count value DW. May wait until the value reaches the specific value n1, and the processing may be started when the counter value DW reaches n1. FIG. 10B illustrates this state. Even in the interrupt signal acceptance prohibited state, the CPU starts processing of the processing time P at the timing when the count value DW becomes n1. This indicates that the process can be executed at regular time intervals T (= 2 mS). n1 is an arbitrary integer equal to or smaller than N, but when n1 = 1, the process can be started at almost the same timing as the interrupt process by the interrupt signal INT. Note that although N × τ = T, the processing time P of processing repeated at a constant interval T needs to satisfy the relationship of (N−n1) × τ> P−n1 × τ. <N × τ must be satisfied.

  FIG. 11 illustrates the contents of the interrupt processing program executed by the main control board 39 in response to the NMI interrupt, and is executed when the power supply voltage drops due to a power failure or the like. A detection circuit for detecting a power supply abnormality is provided on the power supply board 45, and an NMI signal from the detection circuit is transmitted to the CPU of each control board. Since the interrupt of NMI (Non Maskable Interrupt) is the highest priority interrupt, even if the CPU is in INT (Maskable Interrupt) interrupt at that time, the processing of FIG. 11 is started. Maskable Interrupt) signal is not accepted.

  In the NMI interrupt process, first, the contents of each register (AF, I, BC, DE, HL) are pushed to the stack area (ST20). However, since the value of the I register cannot be pushed directly to the stack area, it is substituted by executing the instruction of PUSH AF after executing the instruction of LDA, I.

  Next, the value of the stack pointer SP after execution of the PUSH instruction in step ST20 is stored in the SP storage area of the RAM (ST21). Data is held in a predetermined area of the RAM including this SP storage area by supplying backup power such as a battery even after the energization is stopped. While the game is in progress, various data are temporarily stored in the work area (work area) of the RAM, and these data are also held by a backup power source.

  Subsequently, the CPU substitutes 105 for a variable NT (ST22). This process is for repeatedly detecting the state of the prize ball counting switch for a certain period of time (specifically, 210 mS) because there is a case where the prize ball is being paid out at the time of the NMI interruption. When the initial setting of the variable NT is completed, the CPU acquires the count value DW of the down counter 70 from the counter unit inside the one-chip microcomputer (ST23). Then, it waits for the count value DW to reach a predetermined value (1 in this example) (ST24, ST23).

  As described above, the down counter 70 changes in the order of 125 → 124 →... → 1 → (0 → 125) →... In this embodiment in every pulse cycle τ = 16 μS. ) Is started at the timing of the counter value DW = 1, standby processing of steps ST23 and ST24 is provided. Thereafter, when the counter value DW becomes 1, the CPU acquires the signals of the left and right prize ball switches 54a and 54b, and stores necessary data in the corresponding area of the RAM based on the recognized number of prize balls (ST25). . Of course, this stored data is backed up even during a power failure.

  Thereafter, the variable NT is decremented (ST26), and the processes of steps ST23 to ST27 are repeated until NT = 0. As described above, the process of step ST25 is started at the timing when the counter value DW of the down counter 70 reaches 1, but the timing at which the counter value DW reaches 1 is every fixed time T (= 2 mS). Occurs (see FIG. 10B). Therefore, the switch input process can be executed at the same interval T (= 2 mS) as the interrupt process (FIG. 13) described later, even though the CPU is in the interrupt disabled state.

  The switch input process (ST25) is repeated a total of 105 times and proceeds to the next process after 105 × 2 mS = 210 mS. Normally, game balls passing at 100 mS are monitored over 210 mS. Reading over is prevented. This point will be specifically described with reference to FIGS. The processing of FIG. 11 is started by the main control board 39 by the NMI interruption, and the same processing is also started by the payout control board 46, so that the payout rotating body 51 stops its operation.

  For example, the payout rotator 51 stops in the state of FIG. 7A, and the game ball sent out shifts to the state of FIG. 7B after a predetermined time has elapsed from the state of FIG. 7A. . When the NMI processing is started, the switch processing synchronized with the INT interrupt cannot be performed, but in this embodiment, the switch input processing is repeated for a predetermined time (= 210 mS) in synchronization with the value DW of the down counter. Therefore, there is no fear of reading out several prize balls shown in FIG.

  After the number of prize balls being paid out is accurately grasped as described above, the flag value 5AH is stored in the RAM area of the backup flag BFL (ST28). Thereafter, access to the RAM is prohibited and the power supply voltage drops. It waits for the CPU to become inoperative (ST29). After that, the CPU becomes non-operating, but since the backup power is supplied to the RAM, the backed up data continues to be stored as it is.

  The NMI interrupt processing program in the main control board 39 has been described above. In the case of the payout control board 46, the value of the ball lending count switch is managed in addition to the prize ball coefficient switch. The processing content in response to the NMI interrupt is the same as in FIG. 11, and the movement of the game ball is monitored for 210 ms, so even if a power failure occurs during ball lending or award balls, There is no mistake.

  FIG. 12 is a flowchart showing a main routine of the game control program executed on the main control board 39. In the main routine, first, the CPU sets itself to an interrupt disabled state (DI), and initializes each part of the one-chip microcomputer 60 including the CPU (ST1). There are two patterns when the power is turned on, such as when the initialization switch 85 is turned off and the power is turned on, such as when recovering from a power failure, and when the pachinko hall is opened. As described above, the initialization switch 85 may be turned on and the power supply may be turned on.

  Thereafter, the CPU determines the value of the RAM clear signal (ST2). The RAM clear signal is a signal indicating whether or not the RAM area is set to an initial value, and has a value corresponding to the ON / OFF state of the initialization switch 85. Assuming that the pachinko hall is open and the initialization switch 85 is turned on and the power is turned on, the determination in step ST2 is Yes, the RAM work area is initialized, and other RAM areas are cleared to zero. (ST4). Then, the CPU is set to an interrupt permission state (EI) (ST4), and thereafter, random number generation processing is performed in an infinite loop (ST5). Note that the process of step ST5 is a process for determining what aspect of the out-of-game is to be produced when the out-of-game state is determined by a determination such as a jackpot determination process described later.

  On the other hand, when the initialization switch 85 is in the OFF state as in the case of recovery from the power failure state, the content of the backup flag BFL is determined following the determination in step ST2 (ST3). The backup flag BFL is data indicating whether or not the backup data at the time of the interruption operation saved in the NMI process is restored to the original state. In this embodiment, the backup flag BFL is processed in the process of step ST28. Is set to 5AH and is cleared to zero in the process of step ST10.

  Assuming a recovery from a power failure state, the content of the backup flag BFL is 5AH. Therefore, the CPU processing shifts from step ST3 to step ST6, and writes the 16-bit data read from the SP storage area of the RAM to the stack pointer SP of the CPU (ST6).

  Next, the data held by the backup power source is read out, and a process for restoring the interrupted command is performed (ST7). Here, the command is a command transmitted from the main control board to each control board, and is used to excite the game by an image or sound or to pay out a prize ball. Create necessary commands by reading. Next, the CPU executes a POP instruction to restore the value of each register (BC, DE, HL) excluding the AF register from the stack area (ST8). When this process is completed, the data in the SP storage area is cleared to zero (ST9).

  As a result of the above processing, the recovery processing from the power failure is completed for the time being, so the backup flag BFL is cleared to zero to indicate that (ST10). In the present embodiment, the restoration of the AF register is not completed, but the data in the SP storage area is cleared to zero and the backup flag BFL is cleared to zero because the processing of ST9 and ST10 only uses the A register. This is because if the processing of ST9 and ST10 is postponed, the data of the A register that has been restored is broken.

  Therefore, in this embodiment, the restoration processing of the I register and AF register is performed after the backup flag BFL is cleared to zero. Specifically, first, a POPAF instruction is executed to restore the contents of the I register to the F register (ST11). Since the NMI interrupt processing program loads the value of the I register into the A register and pushes the value of the A register, the POP instruction causes the P / V flag of the F register to receive an interrupt enable flip-flop inside the CPU. The value of the IFF is stored.

  Here, when the P / V flag is 1, the CPU at the time of NMI processing is in an interrupt enabled state. Conversely, when the P / V flag is 0, the CPU at the time of NMI processing is prohibited from interrupting. It was in a state. Therefore, if the P / V flag is 0, the POP instruction is executed again to restore the value of the AF register, and the RET instruction is executed with the interrupt disabled state (ST13, ST14). On the other hand, if the P / V flag is 1, the POP instruction is executed again to restore the value of the AF register, and the interrupt enable state is changed to execute the RET instruction (ST15 to ST17). In any case, when the RET instruction is executed, the value of the PC (program counter) at the time of the PUSH processing being restored in the stack area is restored, and the processing suspended due to a power failure or the like is resumed. Become.

  FIG. 13 is a flowchart showing the contents of an interrupt processing program of a timer interrupt INT (Maskable Interrupt disableable interrupt) that occurs every 2 ms during the infinite loop processing (ST5) of the main routine (FIG. 12). When a timer interrupt occurs, the contents of each register are saved in the stack area, and random number generation processing, switch input management processing, error management processing, and the like are performed (ST30). The switch input management process is a determination as to whether or not a game ball has passed through a gate or an electric tulip, and the error management process is a determination as to whether an abnormality has occurred inside the device. The random number generation process means a process for acquiring a hit random number value or a jackpot random value that is updated in hardware.

  Thereafter, the value of the process division counter is determined, and the corresponding process from ST32 to ST36 is performed. The above error management and switch management should be repeated at short time intervals. On the other hand, the processing related to the pachinko game production is complicated and sophisticated according to the player's needs, and therefore requires a certain amount of processing time. It will be. Therefore, in this embodiment, not all the game control operations are completed by one interrupt process, but are divided into five types of processes, and each divided process is divided and executed for each interrupt. Yes. Therefore, a processing division counter that circulates in the range of 0 to 4 is provided to perform processing according to the value of the processing division counter.

  More specifically, when the processing division counter is 0, processing relating to the opening of the big prize opening is performed (ST32), and when the processing division counter is 1, whether the winning state (electric tulip is open) or not. Normal symbol processing is performed (ST33), and when the processing division counter is 2, processing relating to whether or not a big hit state is performed (ST34). When the process division counter is 3, timer management processing related to the opening / closing timing of the electric tulip and the big prize opening and command creation processing transmitted from the main control board to each control board are performed (ST35). If the process division counter is 4, information output and error display command creation processing is performed (ST36).

  When any of steps ST32 to ST36 is completed, the value of the process division counter is updated (ST37), and the generated command is transmitted to each control board (ST38). Further, the value of each register is restored and changed to the interrupt enabled state, and the routine returns from the interrupt processing routine to the main routine (ST39).

  Although one embodiment of the present invention has been described above, the specific technical contents do not particularly limit the present invention. That is, in the embodiment, the specific description has been made on the assumption that the CPU is a Z80 CPU equivalent, but it is natural that other CPUs may be used. Also, the specific configuration of the counter unit does not particularly limit the present invention, and it goes without saying that an up counter may be used instead of the down counter.

It is a perspective view of the pachinko machine concerning an example. It is a side view of the pachinko machine of FIG. It is a front view of the pachinko machine of FIG. It is a rear view of the pachinko machine of FIG. It is a circuit block diagram of the pachinko machine of FIG. A payout cassette CA (payout means) is specifically illustrated. The award ball movement is illustrated. The ball lending operation is illustrated. It is a block diagram which shows the circuit structure of a main control board. It is a block diagram which shows the circuit structure of the timer part in a one-chip microcomputer. It is a flowchart of the NMI interruption processing program implemented at the time of a power failure. It is a flowchart of the main routine of the game control program which concerns on an Example. It is a flowchart of the INT interruption processing program in the timer interruption. It is a flowchart explaining operation | movement of a conventional apparatus.

Explanation of symbols

2 Ball game machines (pachinko machines)
46 Discharge control board 39 Main control board 70 Counter (down counter)
ST20-29 Backup means (NMI processing)
Count value of DW counter CA Dispensing device (dispensing cassette)

Claims (9)

A payout control board for controlling a payout device for paying out a game ball to a player, a main control board for centrally controlling game operations, and a power supply monitor for monitoring a power supply voltage supplied to the payout control board and the main control board Means and backup means for storing information necessary for resuming the game operation by interrupting the game operation on condition that the power supply monitoring unit detects an abnormal state, and the main control board and / or the payout The control board includes a memory storing a game control program, a CPU that operates based on the control program, and a counter that circulates in a predetermined numerical range.
In the main control board and / or the payout control board, the count value of the counter is acquired at the time of operation of the backup means, and a game ball passing detection operation is performed based on the acquired value. A ball game machine to play. In the main control board and / or the payout control board, a game ball passage detection operation is performed in response to an interrupt signal generated from the counter every time the count value reaches a predetermined value during a game operation. The bullet ball game machine according to claim 1, wherein: In the main control board and / or the payout control board, during the operation of the backup means, a process of waiting for the value to reach a predetermined value while acquiring the count value before or after the game ball passage detection operation The ball game machine according to claim 1, wherein the ball game machine is executed. The bullet ball according to claim 1, wherein the power monitoring means is provided on a separately provided power supply board, and the backup means is provided on the main control board and / or the payout control board. Gaming machine. 5. The interrupt signal with the highest priority is supplied to the CPU of the main control board and / or the payout control board when the power supply monitoring unit detects an abnormal state. The bullet ball game machine described. 6. The ball game machine according to claim 1, wherein the main control board grasps the number of prize balls based on the passage of game balls detected during operation of the backup means. 6. The payout control board ascertains the number of winning balls and / or the number of balls lent based on the passing of a game ball detected during operation of the backup means. Ball game machine. The ball game machine according to any one of claims 1 to 7, wherein the memory, the CPU, and the counter are integrated into a single electronic component. The ball game machine according to any one of claims 1 to 8, wherein the backup means completes the operation after detecting a predetermined number of passages of the game ball.

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