JP2010259837A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine allowing a reduction in storage capacity of storage means by reducing program codes more than ever before. <P>SOLUTION: The game machine includes the storage means having at least a first storage area accessible from a CPU via an I/O space. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a game machine represented by a slot machine or a pachinko machine.

  A conventional game table (for example, a pachinko machine) is a game in which a player has a predetermined profit by launching a ball toward a game area by a launching device and causing the ball to enter a predetermined winning opening provided in the game area. Is configured to earn.

  In order to reduce the storage capacity of a storage means such as a ROM, a gaming table in which a part of a lottery table for winning combinations is shared is proposed as one of such conventional gaming tables (for example, Patent Documents). 1).

JP-A-9-168640

  However, in the gaming machine described in Patent Document 1, although the storage capacity corresponding to the lottery table can be reduced, the program code cannot be reduced, so there is a limit to the reduction of the storage capacity.

  The present invention has been made to solve such problems, and it is an object of the present invention to provide a game machine capable of reducing the program code and reducing the storage capacity of the storage means as compared with the prior art. To do.

  The present invention is a gaming machine comprising a RAM for temporarily storing data, and a CPU for performing game control using the data stored in the RAM, wherein the RAM is a register of the CPU. When the data is transferred from the CPU to the RAM, the memory mapped memory, which is a second storage area in which the data can be written via the memory space by the LD instruction, and the CPU register to the RAM When transferring 1-byte data, the first storage area in which the 1-byte data can be written via the I / O space by an OUT instruction having a smaller program code amount than the LD instruction. And an I / O mapped memory. The CPU passes the memory space to the second storage area of the RAM via the LD instruction. It writes data, in the first storage area of the RAM, and wherein the data writing is performed via the I / O space by different the OUT instruction with the LD instruction is the amusement machine.

  According to the gaming machine according to the present invention, the program code can be reduced more than before, and the storage capacity of the storage means can be reduced.

It is the external appearance perspective view which looked at the pachinko machine from the front side (player side). It is the schematic front view which looked at the game board from the front. (A) An example of a special display stop display mode is shown. (B) An example of a decorative design is shown. (C) An example of a normal stop display mode is shown. The circuit block diagram of a control part is shown. It is the block diagram which showed the principal part of the basic circuit of the main control part. (A) It is the figure which showed an example of the memory space accessible by CPU of a main control part. (B) It is the figure which showed an example of the I / O space accessible by CPU of a main control part. (C) It is the figure which showed the correspondence of the area allocated to RAM of the memory space, and the area allocated to the I / O space. It is an example of the time chart which shows the relationship between a clock signal, an address signal, an IO request signal, a write signal, and a data signal in writing by I / O mapped memory. It is an example of a time chart showing the relationship among a clock signal, an address signal, an IO request signal, a read signal, and a data signal in reading by an I / O mapped memory. It is a flowchart which shows the flow of a main control part main process. It is a flowchart which shows the flow of a main control part timer interruption process. (A) It is a flowchart which shows the flow of a timer update process. (B) It is a flowchart which shows the flow of a 1-byte timer update process. (C) It is a flowchart which shows the flow of a 2-byte timer update process. It is the figure which showed an example of the program of 1 byte timer update process and 2 byte timer update process. FIG. 5 is a diagram comparing the number of states (number of clocks) required for an IN instruction, an OUT instruction, and an LD instruction of a CPU, and the amount of program code by reading and writing to an I / O mapped memory and reading from and writing to a memory mapped memory. (A) It is a flowchart which shows the flow of a sub control part main process. (B) It is a flowchart which shows the flow of command input processing. (C) It is a flowchart which shows the flow of a fluctuation pattern selection process. (D) It is a flowchart which shows the flow of a symbol stop process. (E) It is a flowchart which shows the flow of a strobe interruption process. (F) It is a flowchart which shows the flow of a chance button interruption process. (G) It is a flowchart which shows the flow of a variable update interruption process. An external perspective view of the slot machine is shown. The circuit block diagram of the main control part of the slot machine is shown.

  Hereinafter, a pachinko machine (game table) according to Embodiment 1 of the present invention will be described in detail with reference to the drawings.

  <Overall configuration>

  First, the overall configuration of the pachinko machine 100 will be described with reference to FIG. In addition, the figure is the external appearance perspective view which looked at the pachinko machine 100 from the front side (player side).

  The pachinko machine 100 includes a game board (board surface) 102, which will be described later, disposed so as to be visible on the back side of a door member 156 made of a transparent plate member 152 made of glass or resin and a transparent member holding frame (glass frame) 154. ing.

  Further, below the launcher 138 and the launcher 140, an operation handle 148 for controlling the launcher 138 and operating the launch intensity of the sphere toward the game area 104 is disposed. Below the 144, a lower plate 150 is provided for storing overflow balls that cannot be stored in the storage plate 144.

  FIG. 2 is a schematic front view of the game board 102 as viewed from the front. The game board 102 is provided with an outer rail 106 and an inner rail 108, and a game area 104 in which a game ball (hereinafter sometimes simply referred to as “ball”) can roll is defined.

  In the center of the game area 104, an effect device 200 is provided. In the effect device 200, a horizontally long decorative symbol display device 110 is arranged at substantially the center, and a normal symbol display device 112, a special symbol display device 114, a normal symbol hold lamp 116, and a special symbol hold around the periphery thereof. A lamp 118 and a high-probability medium lamp 120 are provided. Hereinafter, the normal symbol may be referred to as “general symbol” and the special symbol may be referred to as “special symbol”.

  The rendering device 200 performs rendering by operating the movable part, and details will be described later. The decorative symbol display device 110 is a display device for displaying various images used for decorative symbols and effects. In the present embodiment, the decorative symbol display device 110 is configured by a liquid crystal display device (Liquid Crystal Display). The decorative symbol display device 110 is divided into four display areas, a left symbol display area 110a, a middle symbol display area 110b, a right symbol display area 110c, and an effect display area 110d, and the left symbol display area 110a and the middle symbol display area 110b. The left symbol display area 110c displays different decorative symbols, and the effect display area 110d displays an image used for the effect. Further, the positions and sizes of the display areas 110a, 110b, 110c, and 110d can be freely changed within the display screen of the decorative symbol display device 110. The decorative symbol display device 110 employs other display devices such as a dot matrix display device, a 7-segment display device, an EL (ElectroLuminescence) display device, a drum display device, and a leaf display device instead of the liquid crystal display device. May be.

  The general map display device 112 is a display device for displaying a general map, and is configured by a 7-segment LED in this embodiment. The special figure display device 114 is a display device for displaying a special figure, and is constituted by a 7-segment LED in this embodiment.

  The general figure hold lamp 116 is a lamp for indicating the number of the general figure variable games that are on hold. In this embodiment, it is possible to hold up to two common figure variable games. The special figure hold lamp 118 is a lamp for indicating the number of special figure variable games that are on hold. In this embodiment, up to four special figure variable games can be held. The high-probability lamp 120 is a lamp for indicating that the gaming state is a high probability state (a gaming state in which a winning probability of a jackpot game described later is set higher than a normal probability), or a high probability state. Yes, when the game state is changed from a low probability state (a game state in which the winning probability of a big hit game described later is set to a normal probability) to a high probability state, and turned off when changing from a high probability state to a low probability state . In this embodiment, the high-accuracy medium lamp 120 is turned on also when shifting to a mission time described later, and the high-accuracy medium lamp 120 is turned off when the mission time is finished.

  Further, around the effect device 200, a general winning opening 122, a general drawing starting opening 124, a first special drawing starting opening 126, a second special drawing starting opening 128, and a variable winning opening 130 are arranged. ing. In this embodiment, a plurality of general winning holes 122 are provided on the game board 102. When a predetermined ball detecting sensor (not shown) detects a ball entering the general winning holes 122 (in the general winning holes 122). In the case of winning, a payout device 552 described later is driven, and a predetermined number (10 in this embodiment) of balls is discharged as a prize ball to the storage tray 144. The ball discharged to the storage tray 144 can be freely taken out by the player, and with these configurations, the prize ball is paid out to the player based on the winning. The ball that has entered the general winning opening 122 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side. In this embodiment, a ball to be paid out to a player as a consideration for winning is sometimes referred to as a “prize ball”, and a ball lent to a player is sometimes referred to as “rental ball”. They are called “balls (game balls)”.

  The normal start port 1124 is configured by a device called a gate or a through chucker for determining whether or not a ball has passed through a predetermined area of the game area, and in this embodiment, on the left side of the game board 102. One is arranged. Unlike the ball that has entered the general winning opening 122, the ball that has passed through the normal start port 124 is not discharged to the amusement island side. When the predetermined ball detection sensor detects that the ball has passed through the usual figure starting port 124, the pachinko machine 100 starts the usual figure variable game by the usual figure display device 112.

  In the present embodiment, only one first special figure starting port 126 is disposed at the center of the game board 102. When a predetermined ball detection sensor detects a ball entering the first special figure starting port 126, a payout device 552 to be described later is driven to store a predetermined number (three in this embodiment) of balls as prize balls. While discharging to the plate 144, the special figure display game by the special figure display device 114 is started. The ball that has entered the first special figure starting port 126 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side.

  The second special figure starting port 128 is called an electric tulip (electric chew), and in the present embodiment, only one second special figure starting port 128 is disposed directly below the first special figure starting port 126. This second special figure starting port 128 is provided with wings that can be opened and closed to the left and right. While the wings are closed, it is impossible to enter a sphere. Is stopped and displayed, the blades open and close at a predetermined time interval and a predetermined number of times. When a predetermined ball detection sensor detects a ball entering the second special figure starting port 128, a payout device 552, which will be described later, is driven, and a predetermined number (5 in this embodiment) of balls will be described later as prize balls. While discharging to the storage tray 144, the special figure display game by the special figure display device 114 is started. The ball that has entered the second special figure starting port 128 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side.

  The variable winning opening 130 is called a big winning opening or an attacker, and in this embodiment, only one variable winning opening 130 is arranged below the center of the game board 102. This variable winning opening 130 has a door member that can be freely opened and closed. When the door member is closed, it is impossible to enter a ball, and the special figure display device 114 stops displaying the jackpot symbol. In this case, the door member opens and closes at a predetermined time interval (for example, an opening time of 29 seconds and a closing time of 1.5 seconds) and at a predetermined number of times (for example, 15 times). When a predetermined ball detection sensor detects a ball entering the variable winning opening 130, a payout device 552, which will be described later, is driven, and a predetermined number (15 balls in this embodiment) of balls is discharged to the storage tray 144 as a prize ball. To do. The ball that has entered the variable prize opening 130 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side.

  Further, a plurality of disk-shaped hitting direction changing members 132 and game nails 134 called windmills are arranged in the vicinity of these winning openings and starting openings, and at the bottom of the inner rail 108, An out port 136 is provided for guiding a ball that has not won any prize opening or starting port to the back side of the pachinko machine 100 and then discharging it to the game island side.

  The pachinko machine 100 supplies the ball stored in the storage tray 144 by the player to the launch position of the launch rail 142, drives the launch motor 602 with strength according to the operation amount of the player's operation handle 148, The launcher 138 and the launcher 140 are passed through the outer rail 106 and the inner rail 108 to launch into the game area 104. Then, the ball that has reached the upper part of the game area 104 falls downward while changing the advancing direction by the hitting direction changing member 132, the game nail 134, etc., and a winning opening (general winning opening 122, variable winning opening 130) or starting opening (First special figure start port 126, second special figure start port 128), or the out port 136 without winning any of the winning port and start port, or just passing the normal start port 124 To reach.

  <Director>

  Next, the rendering device 200 of the pachinko machine 100 will be described. A warp device 230 and a stage are arranged on the front side of the effect device 200, and a decorative symbol display device 110 and a shielding means 250 are arranged on the back side of the effect device 200. That is, in the rendering device 200, the decorative symbol display device 110 and the shielding means 250 are located behind the warp device 230 and the stage.

  The warp device 230 discharges the game ball that has entered the entrance 232 provided at the upper left of the effect device 200 to the front stage 234 below the front surface of the effect device 200, and the game ball discharged to the front stage 234 is the front surface. When the player enters the second entrance 236 provided at the rear of the center of the stage 234, the game ball is discharged from the outlet 238 provided in the lower center of the stage device 200 above the first special figure starting port 126. It is discharged toward the first special figure starting port 126. The game ball discharged from the discharge port 238 is easy to enter the special figure starting port 126.

  The shielding means 250 includes a lattice-like left door 250a and right door 250b, and is disposed between the decorative symbol display device 110 and the front stage 234. Belts wound around two pulleys (not shown) are respectively fixed to the upper portions of the left door 250a and the right door 250b. That is, the left door 250a and the right door 250b move to the left and right with the operation of the belt driven by the motor via the pulley. When the left and right doors 250a and 250b are closed, the shielding means 250 covers the inner end portions of the doors 250a and 250b so that it is difficult for the player to visually recognize the decorative symbol display device 110. In the state where the left and right doors 250a and 250b are opened, each inner end portion slightly overlaps the outer end portion of the display screen of the decorative symbol display device 110, but the player can visually recognize all of the displays on the decorative symbol display device 110. . Further, the left and right doors 250a and 250b can be stopped at arbitrary positions, for example, only a part of the decorative design is shielded so that the player can identify which decorative design the displayed decorative design is. You can do that. Note that the left and right doors 250a and 250b may make it possible to visually recognize a part of the decorative pattern display device 110 behind the lattice hole, or block the shoji part of the lattice hole with a translucent lens body to decorate the rear. The display by the symbol display device 110 may be vaguely visible to the player, or the shoji part of the lattice holes may be completely blocked (shielded), and the decorative symbol display device 110 at the rear may be completely invisible. .

  <Type of design>

  Next, with reference to FIGS. 3A to 3C, the special drawing display device 114, the decorative symbol display device 110, and the special drawing display device 112 of the pachinko machine 100 will be described with respect to the special drawing and the type of the common drawing. To do.

  FIG. 4A shows an example of a special display stop display mode. There are three types of special display stop display modes according to the present embodiment: “Special Figure 1” which is a jackpot symbol, “Special Figure 2” which is a special jackpot symbol, and “Special Figure 3” which is a missed symbol. . When the special figure variation game is started on the condition that a predetermined ball detection sensor detects that a ball has won the first special figure start port 126 or the second special figure start port 128, the special figure display device 114 Performs “variable display of special figure” by repeating all lighting of seven segments and lighting of one central segment. Then, when the variation time determined before the start of the special figure elapses, in order to notify the winning of the special figure variable game, “Special Figure 1” or “Special Figure 2” is stopped and displayed. In the case of notifying the disconnection, “Special Figure 3” is stopped and displayed. In addition, the white part in a figure shows the location of the segment which turns off, and the black part shows the location of the segment which lights up.

  FIG. 2B shows an example of a decorative design. There are 10 types of decoration patterns of the present embodiment: “Decoration 1” to “Decoration 10”. The left symbol display area 110a of the decorative symbol display device 110, the middle symbol, on condition that a predetermined ball detection sensor detects that a ball has won the first special symbol start port 126 or the second special diagram start port 128 In the respective symbol display areas of the display area 110b and the right symbol display area 110c, “decoration 1” → “decoration 2” → “decoration 3” →... “Decoration 9” → “decoration 10” → “decoration 1” → Perform “decorative symbol variation display” to switch the display in the order. When notifying the jackpot, a symbol combination corresponding to the jackpot in the symbol display areas 110a to 110c (in this embodiment, a combination of decorative symbols having the same number (for example, “decoration 2—decoration 2—decoration 2”). )) Is stopped and a special jackpot is notified, a combination of symbols corresponding to the special jackpot (in this embodiment, a combination of decorative symbols of the same odd-numbered numbers (for example, “decoration 1-decoration 1-decoration”). 1 ”)) is stopped and displayed. When the symbol combination corresponding to the jackpot is stopped and displayed, the jackpot game or the special jackpot game is started, and when the symbol combination corresponding to the special jackpot is stopped and displayed, the special jackpot game is started. In the case of notifying a detachment, if there is a variation display of a decorative symbol that is put on hold after the symbol combination other than the symbol combination corresponding to the jackpot is stopped and displayed in the symbol display areas 110a to 110c, the variation display is performed. To start.

  FIG. 2C shows an example of a normal stop display mode. In the present embodiment, there are two types of stoppage display modes of the normal figure, “general figure 1” which is a winning symbol and “general figure 2” which is a missed symbol. In the case where a general-purpose display game is started on the condition that a predetermined ball detection sensor detects that a ball has passed through the general-purpose start opening 124, the general-purpose display device 112 displays that all seven segments are turned on. Then, the “variable display of the usual map” is performed by repeatedly turning on one central segment. Then, when notifying the winning of the common figure variable game, the “general figure 1” is stopped and displayed, and when notifying the usual figure variable game being lost, the “normal figure 2” is stopped and displayed.

  <Control unit>

  Next, the circuit configuration of the control unit of the pachinko machine 100 will be described in detail with reference to FIG. This figure shows a circuit block diagram of the control unit.

  The control unit of the pachinko machine 100 can be broadly classified according to a main control unit 300 that controls the central part of the game and a command signal (hereinafter simply referred to as “command”) transmitted by the main control unit 300. A sub-control unit 400 that controls effects, a payout control unit 550 that mainly performs control related to payout of game balls in response to commands transmitted by the main control unit 300, and a launch control unit 600 that controls the launch of game balls. And a power management unit 650 that controls the power supplied to the pachinko machine 100.

  <Main control unit>

  First, the main control unit 300 of the pachinko machine 100 will be described.

  The main control unit 300 includes a basic circuit 302 that controls the entire main control unit 300. The basic circuit 302 includes a CPU 304, a ROM 306 for storing control programs and various data, and temporary data. RAM 308 for storing data, I / O 310 for controlling input / output of various devices, and counter timer 312 for measuring time, number of times, and the like. Note that other storage means may be used for the ROM 306 and the RAM 308, and this is the same for the sub-control unit 400 described later. The CPU 304 of the basic circuit 302 operates by inputting a clock signal of a predetermined period output from the crystal oscillator 314 as a system clock.

  The basic circuit 302 includes a counter circuit 316 that is used as a hardware random number counter that changes a numerical value in the range of 0 to 65535 every time a clock signal output from the crystal oscillator 314a is received, and the counter circuit 316. Receives and amplifies signals output from various sensors 318 including a latch circuit 317 that acquires and holds a hardware random number generated by the ball, and a ball detection sensor provided in each start opening, winning opening and variable winning opening A sensor circuit 320 for outputting a result and a comparison result with a reference voltage (for example, a ball detection signal to be described later) to the latch circuit 317 and the basic circuit 302, and a display circuit for performing display control of the special figure display device 114 322, a display circuit 324 for performing display control of the general map display device 112, and various status display units 326 (general map hold lamps) 16, special figure holding lamp 118, high-accuracy medium lamp 118, etc.), and various solenoids 330 for opening and closing the second special figure starting port 128, variable winning port 130, etc. For this purpose, a solenoid circuit 332 is connected.

  Further, an information output circuit 334 is connected to the basic circuit 302, and the main control unit 300 is connected to an information input circuit 652 provided in an external hall computer (not shown) or the like via the information output circuit 334. The game information (for example, game state) of the machine 100 is output.

  The main control unit 300 includes an output interface for transmitting a command to the sub-control unit 400 and an output interface for transmitting a command to the payout control unit 550. With this configuration, the sub-control unit 400 In addition, communication with the payout control unit 550 is enabled. Information communication between the main control unit 300, the sub control unit 400, and the payout control unit 550 is one-way communication, and the main control unit 300 can transmit signals such as commands to the sub control unit 400 and the payout control unit 550. However, the sub-control unit 400 and the payout control unit 550 are configured such that signals such as commands cannot be transmitted to the main control unit 300.

  <Sub control unit>

  Next, the sub control unit 400 of the pachinko machine 100 will be described.

  The sub-control unit 400 includes a basic circuit 402 that controls the entire sub-control unit 400 mainly based on commands transmitted from the main control unit 300. The basic circuit 402 includes a CPU 404, a control program, ROM 406 for storing various data, RAM 408 for temporarily storing data, I / O 410 for controlling input / output of various devices, and counter timer 412 for measuring time and frequency It is installed. The CPU 404 of the basic circuit 402 operates by inputting a clock signal of a predetermined period output from the crystal oscillator 414 as a system clock.

  The basic circuit 402 drives a sound source IC 418 for controlling the speaker 416 (and amplifier), a display circuit 422 for controlling various lamps 420, a movable body for rendering of the rendering device 200, and the like. An effect driving device control circuit 426 for controlling various effect driving devices 424 including a solenoid or a motor as a driving device, and a decorative symbol display device (liquid crystal display device) 110 and a shielding means 250 are controlled. The sub-control unit 500 is connected to a chance button detection circuit 380 that detects the pressing of the chance button 146 and outputs a signal.

  <Discharge control unit, launch control unit, power supply management unit>

  Next, the payout control unit 550, the launch control unit 600, and the power supply management unit 650 of the pachinko machine 100 will be described.

  The payout control unit 550 controls the payout device 552 mainly based on a signal such as a command transmitted from the main control unit 300, and the payout of the winning ball or the rental ball is completed based on a control signal output from the payout sensor 554. It is detected whether or not the card unit 654 is provided separately from the pachinko machine 100 via the interface unit 556.

  The firing control unit 600 determines the amount of operation of the launch handle 148 by the player, which is output from the control signal instructing permission or stop of launch output from the payout control unit 550, or the launch intensity output circuit provided in the operation handle 148. Based on the control signal instructing the corresponding launch intensity, the launch motor 602 that drives the launcher 138 and the launcher 140 is controlled, and the ball feeder 604 that supplies the ball from the storage plate 144 to the launch rail 142 is controlled. .

  The power management unit 650 converts the AC power supplied from the outside to the pachinko machine 100 into a direct current, converts it into a predetermined voltage, and controls the control units such as the main control unit 300 and the sub control unit 400, and the devices such as the dispensing device 552. To supply. Further, the power management unit 650 supplies a power storage circuit (for example, a power supply circuit) for supplying power to a predetermined part (for example, the RAM 308 of the main control unit 300) for a predetermined period (for example, 10 days) even after the external power supply is cut off. Capacitor).

  <Basic circuit of main control unit>

  Next, the basic circuit 302 of the main control unit 300 will be described in detail with reference to FIG. This figure is a block diagram showing the main part of the basic circuit of the main control unit.

  The CPU 304 included in the basic circuit 302 includes 16 address buses A0 to A15, 8 data buses D0 to D7, one memory request output terminal MREQ, and one IO request output terminal IORQ. The 16 address buses A0 to A15 are connected to the address input terminal of the RAM 308 via the address converter 340, and the 8 bits assigned to the lower 8 bits of the address among the 16 address buses A0 to A15. The address buses A0 to A7 are further connected to an address input terminal of the address decoder 342. The eight data buses D0 to D7 are connected to the data input terminals of the RAM 308 and are also connected to the data input terminals of the buffer ICs 344 and 346, respectively. The memory request output terminal MREQ terminal is connected to the request terminal of the RAM 308 via the OR circuit 348. The IO request output terminal IORQ is connected to the request terminal of the address decoder 342.

  The output terminal OUT of the address decoder 342 is connected to the input terminal IN of the address converter 340 and to the input terminal of the OR circuit 348.

  The chip select output terminal CS1 of the address decoder 342 is connected to the chip select terminal of the buffer 344, and the chip select output terminal CS2 of the address decoder 342 is connected to the chip select terminal of the buffer 346. When a chip select signal is input from the chip select output terminal CS1 of the address decoder 342, the buffer 344 has a start port 1 (first special figure start port 126), start port 2 (second special figure start port 128), large The state of the ball detection signal input from the winning port 2 (variable winning port 130) is latched inside and can be output to data buses D0 to D7 connected to the CPU 304. Further, when a chip select signal is input from the chip select output terminal CS2 of the address decoder 342, the buffer 346 receives an electric chew solenoid (driving means for the second special figure starting port 128) and a big winning port solenoid (variable winning port 130). The signal input from the data bus D0 to D7 of the CPU 304 can be output to the payout strobe (signal to the payout control unit 550).

  <I / O mapped memory>

  6A is a diagram showing an example of a memory space accessible by the CPU 304 of the main control unit 300, and FIG. 6B is an example of an I / O space accessible by the CPU 304 of the main control unit 300. FIG. FIG. 3C shows the correspondence between the area allocated to the RAM in the memory space and the area allocated to the I / O space.

  The CPU 304 of the main control unit 300 has a 64-Kbyte memory space from address 0000 to FFFF and a 256-byte I / O space from address 00 to FF. As shown in FIG. 6A, the memory space of the CPU 304 includes a storage area of the ROM 306, a storage area corresponding to the memory space of the RAM 308 (in this example, a storage area of 480 bytes at addresses 2820 to 29FF of the memory space), Chip select output terminals CS0 to CS26 connected to peripheral ICs such as buffer ICs 344 and 336, and internal function registers of the CPU 304 are assigned. Each function assigned to the memory space can be arbitrarily assigned by the user by changing the setting of the internal function register provided in the CPU 304, and is not limited to the example shown in the present embodiment.

  For example, the CPU 304 writes information into a predetermined storage area of the RAM 308 corresponding to a memory space (an I / O space corresponding storage area 2800 to 281F, which will be described later, a storage area of 280 bytes from address 2820 to address 29FF). When performing, the CPU 304 writes information in the address corresponding to the memory space allocated to the RAM 308 (in this example, addresses 2820 to 29FF).

  As a result, an address signal corresponding to the memory space corresponding storage area of the RAM 308 is output from the address bus A0 to A15 of the CPU 304, and information written in the memory space allocated to the RAM 308 is transmitted from the data bus D0 to D7 of the CPU 304. A corresponding data signal is output, and an active level (for example, low level) pulse signal for a predetermined time is output from the memory request output terminal MREQ of the CPU 304 and the write signal. At this time, the RAM 308 latches the address signal input to the address input terminal at the falling edge of the request signal input from the memory request output terminal MREQ, and then inputs data at the rising edge of the request signal input from the memory request output terminal MREQ. The data signal input to the terminal is latched, and the data indicated by the data signal is stored in a predetermined storage area specified by the address signal. In this specification, the writing of data to the memory through such a memory space may be referred to as “writing to the memory-mapped memory”. In this embodiment, “memory map” is executed by an LD instruction provided in the CPU 304. Write to the memory ”is realized.

  On the other hand, when the CPU 304 reads out information from a predetermined storage area of the RAM 308 corresponding to the memory space (addresses 2820 to 29FF), the CPU 304 reads the memory space (address 2820) allocated to the RAM 308. The information is read out from the address corresponding to the address ~ 29FF.

  As a result, the address signal corresponding to the memory space corresponding storage area of the RAM 308 is output from the address bus A0 to A15 of the CPU 304, and the data signal corresponding to the address signal is input to the data bus D0 to D7 of the CPU 304. An active level (for example, low level) pulse signal for a predetermined time is output from the memory request output terminal MREQ and the read signal of the CPU 304. At this time, the RAM 308 latches the address signal input to the address input terminal at the falling edge of the request signal input from the memory request output terminal MREQ, and before the rising edge of the request signal input from the memory request output terminal MREQ. Then, data is read from the storage area designated by the address signal, and this data is output as a data signal to the data buses D0 to D7. In this specification, reading data from the memory through such a memory space may be referred to as “reading from a memory-mapped memory”. In this embodiment, “memory map” is executed by an LD instruction included in the CPU 304. "Reading from memory" is realized.

  Further, in the I / O space of the CPU 304, as shown in FIG. 6B, a storage area corresponding to the I / O space of the RAM 308 (in this example, a 32-byte storage area from the addresses 2800 to 281F of the RAM 308), Chip select output terminals CS0 to CS26 connected to peripheral ICs such as buffer ICs 344 and 336 are assigned. Each function assigned to the I / O space can be arbitrarily assigned by the user by changing the setting of the internal function register included in the CPU 304, and is not limited to the example shown in this embodiment. In addition, regarding which range of the storage area of the RAM 308 is allocated to the I / O space, the user can freely allocate it by changing the setting of the internal function register. In the example shown in this embodiment, It is not limited.

  For example, when the CPU 304 writes information in a predetermined storage area of the RAM 308 corresponding to the I / O space (addresses 2800 to 281F), the CPU 304 uses the I / O space allocated to the RAM 308 (this In the example, information is written to an address corresponding to address 00 to address 1F (for example, address 00 in the I / O space corresponding to address 2800 in RAM 308).

  As a result, as shown in the time chart of FIG. 7, the address signals corresponding to the I / O space corresponding storage area of the RAM 308 are output from the lower 8 bits A0 to A7 of the address buses A0 to A15 of the CPU 304. The data signal corresponding to the information written in the I / O space allocated to the RAM 308 is output from the data bus D0 to D7 of the CPU 304, and the active level for a predetermined time is output from the IO request output terminal IOREQ and the write signal W0 of the CPU 304. A pulse signal (for example, low level) is output. Further, the address decoder 342 outputs a signal to the address converter 340 and the OR circuit 348 in response to the input of the request signal from the IO request output terminal IOREQ, inputs the request signal to the RAM 308, and inputs the request signal of the memory space to the address input terminal of the RAM 308. An address signal (28h in this example) corresponding to the upper 8 bits of the address assigned to the RAM 308 is input. At this time, the RAM 308 latches the address signal input to the address input terminal at the falling edge of the request signal from the OR circuit 348, and then the data signal input to the data input terminal at the rising edge of the request signal from the OR circuit 348. And the data indicated by the data signal is stored in a predetermined storage area designated by the address signal. In this specification, such data writing to the memory via the I / O space may be referred to as “writing to the I / O mapped memory”. In this embodiment, the OUT included in the CPU 304 is provided. “Write to I / O mapped memory” is realized by the instruction. Further, as an instruction corresponding to the OUT instruction, for example, an OUTD instruction, an OUTDR instruction, an OUTI instruction, an OUTIR instruction, or the like can be applied.

  On the other hand, when the CPU 304 reads information from a predetermined storage area of the RAM 308 corresponding to the I / O space (addresses 2800 to 281F), the CPU 304 reads the I / O space (00 The information is read from the address corresponding to the address (address 1F).

  As a result, as shown in the time chart of FIG. 8, from the lower 8 bits A0 to A7 of the address bus A0 to A15 of the CPU 304, an address corresponding to a predetermined storage area of the I / O space corresponding storage area of the RAM 308 is obtained. A signal is output, a data signal corresponding to the address signal is input to the data buses D0 to D7 of the CPU 304, and an active level (for example, a low level) for a predetermined time from the IO request output terminal IOREQ and the read signal R0 of the CPU 304. The pulse signal is output. Further, the address decoder 342 outputs a signal to the address converter 340 and the OR circuit 348 in response to the input of the request signal from the IO request output terminal IOREQ, inputs the request signal to the RAM 308, and the RAM 308 of the memory space to the address bus of the RAM 308. An address signal (28h in this example) corresponding to the upper 8 bits of the address assigned to is input. At this time, the RAM 308 latches the address signal input to the address input terminal at the falling edge of the request signal from the OR circuit 348 and is designated by the address signal before the rising edge of the request signal from the OR circuit 348. Data is read out from the storage area and output as data signals to the data buses D0 to D7. In the present specification, such data reading from the memory via the I / O space may be referred to as “reading from the I / O mapped memory”. In this embodiment, the IN instruction provided in the CPU 304 is provided. Thus, “reading from the I / O mapped memory” is realized. In addition, as an instruction corresponding to the IN instruction, for example, an IND instruction, an INDR instruction, an INI instruction, an INIR instruction, or the like can be applied.

  In this embodiment, a signal output to the OR circuit 348 based on the input of the request signal from the IO request output terminal IOREQ is a memory access signal. However, the memory access signal is not limited to this configuration. Any signal may be used as long as it is output based on a request signal from the IOREQ and is a signal for accessing the memory. For example, the request signal from the IOREQ may be input indirectly without being directly input, or may be output indirectly without being directly output to the storage unit.

  The address decoder 342 outputs a memory access signal if the address input to the address decoder 342 is a predetermined address, and outputs another signal if it is not a predetermined address. This predetermined address can be changed by setting the internal function register as described above.

  <Main control unit main processing>

  Next, main control unit main processing executed by the CPU 304 of the main control unit 300 will be described with reference to FIG. This figure is a flowchart showing the flow of main processing of the main control unit.

  As described above, the main control unit 300 is provided with the start signal output circuit (reset signal output circuit) 338 that outputs the start signal (reset signal) when the power is turned on. The CPU 304 of the basic circuit 302 to which this activation signal has been input starts reset by a reset interrupt and executes processing in accordance with a control program stored in advance in the ROM 306.

  In step S101, initial setting 1 is performed. In this initial setting 1, memory space and I / O space allocation setting by the internal function register of the CPU 304, stack initial value setting to the stack pointer (SP) of the CPU 304, interrupt mask setting, initial setting of the I / O port 310 Setting, initial setting of various variables stored in the RAM 308, operation permission to the WDT 313, setting of initial values, and the like are performed. In this embodiment, a numerical value corresponding to 32.8 ms is set as an initial value in WDT 313.

  In step S102, the value of the counter of WDT 313 is cleared, and the time measurement by WDT 313 is restarted.

  In step S103, whether or not the low voltage signal is on, that is, the voltage value of the power supply that the voltage monitoring circuit 336 supplies from the power management unit 650 to the main control unit 300 is a predetermined value (in this embodiment, 9v), it is monitored whether or not a low voltage signal indicating that the voltage has dropped is output. If the low voltage signal is on (when the CPU 304 detects that the power supply has been shut off), the process returns to step S102. If the low voltage signal is off (if the CPU 304 has not detected the power supply being cut off), the process proceeds to step S102. The process proceeds to S104.

  In step S104, initial setting 2 is performed. In this initial setting 2, a process for setting a numerical value for determining a cycle for executing a main control unit timer interrupt process, which will be described later, to the counter / timer 312, a predetermined port of the I / O 310 (for example, a test output port, Processing for outputting a clear signal from the output port to the sub-control unit 400, setting for permitting writing to the RAM 308, and the like are performed.

  In step S105, it is determined whether or not to return to the state before the power interruption (before the power interruption), and the state before the power interruption is not restored (when the basic circuit 302 of the main control unit 300 is set to the initial state). ) Proceeds to step S107. Similarly, when the power status information indicates information other than “suspend”, the process proceeds to step S108.

  Specifically, first, a RAM clear signal transmitted when a store clerk or the like of the game shop operates the operation unit provided on the power supply board is turned on (indicating that there is an operation), that is, It is determined whether or not RAM clear is necessary, and if the RAM clear signal is on (RAM clear is necessary), the process proceeds to step S107 to set the basic circuit 302 to the initial state. On the other hand, when the RAM clear signal is OFF (when the RAM clear is not necessary), the power status information stored in the power status storage area provided in the RAM 308 is read, and whether the power status information is information indicating suspend. Determine whether or not. If the power status information is not information indicating suspend, the process proceeds to step S107 to set the basic circuit 302 to the initial state. If the power status information is information indicating suspend, a predetermined area of the RAM 308 is set. A checksum is calculated by adding all the 1-byte data stored in (for example, all areas) to a 1-byte register whose initial value is 0, and the calculated checksum results in a specific value (for example, 0) (whether or not the checksum result is normal). If the checksum result is a specific value (eg, 0) (if the checksum result is normal), the process proceeds to step S106 to return to the state before the power interruption, and the checksum result is a specific value. If it is other than a value (for example, 0) (if the result of the checksum is abnormal), the process proceeds to step S107 in order to set the pachinko machine 100 to the initial state. Similarly, if the power status information indicates information other than “suspend”, the process proceeds to step S107.

  In step S106, power recovery processing is performed. In this power recovery process, the stack pointer stored in the stack pointer save area provided in the RAM 308 at the time of power failure is read and reset to the stack pointer. In addition, the value of each register stored in the register save area provided in the RAM 308 at the time of power interruption is read out, reset to each register, and then the interrupt permission is set. Thereafter, as a result of the CPU 304 executing the control program based on the reset stack pointer and registers, the pachinko machine 100 returns to the state when the power is turned off. That is, the processing is resumed from the instruction next to the instruction (predetermined in steps S108 and S109) performed immediately before branching to the timer interrupt processing (described later) immediately before the power interruption.

  In step S107, initialization processing is performed. In this initialization processing, interrupt prohibition setting, stack initial value setting to the stack pointer, initialization of all storage areas of the RAM 308, and the like are performed.

  In step S108, after setting for interrupt inhibition, basic random number initial value update processing is performed. In this basic random number initial value update process, two initial value generation random number counters (hardware random numbers) for generating the initial values of the normal winning random number counter and the special figure random number counter, and the normal timer random number value The two random number counters (hardware random numbers) for generating the special figure timer random number values are updated. For example, if the range of values that can be taken as normal timer random numbers is 0 to 20, a value is acquired from a random number counter storage area for generating a normal timer random value provided in the RAM 308, and 1 is added to the acquired value. Then, it is stored in the original random number counter storage area. At this time, if the result of adding 1 to the acquired value is 21, 0 is stored in the original random number counter storage area. Other initial value generation random number counters and random number counters are similarly updated. Further, after this basic random number initial value update process is completed, an interrupt permission is set, and the process proceeds to step S109.

  In step S109, effect random number update processing is performed. In this effect random number update process, a random number counter for generating an effect random number used by the main control unit 300 is updated.

  The main control unit 300 repeatedly executes the processes of steps S108 and S109 except during a timer interrupt process that starts every predetermined period.

  <Main controller timer interrupt processing>

  Next, main control unit timer interrupt processing executed by the CPU 304 of the main control unit 300 will be described with reference to FIG. This figure is a flowchart showing the flow of main controller timer interrupt processing.

  The main control unit 300 includes a counter / timer 312 that generates a timer interrupt signal at a predetermined cycle (in this embodiment, about once every 1 ms), and the main control unit timer interrupt processing is triggered by this timer interrupt signal. Start with a predetermined period.

  In step S201, timer interrupt start processing is performed. In this timer interrupt start process, a process of temporarily saving the value of each register of the CPU 304 to the stack area is performed.

  In step S202, the WDT is periodically restarted so that the count value of the WDT 313 exceeds the initial setting value (32.8 ms in this embodiment) and a WDT interrupt does not occur (so as not to detect a processing abnormality). Do.

  In step S203, input port state update processing is performed. In this input port state update process, an open sensor for detecting whether the above-described glass frame 154 is in an open state or a closed state via the input port of the I / O 310, the above-described lower plate 150 is provided. A detection signal of various sensors 318 including a bottom plate full sensor for detecting whether or not the ball is full and a plurality of ball detection sensors is input to monitor the presence or absence of the detection signal. The signal state is stored in a signal state storage area. In this embodiment, information on the presence or absence of the detection signal of each sphere detection sensor detected in the timer interruption process of the last time (about 2 ms before) is stored in the RAM 308 for each previous sphere detection sensor. This information is read from the area, this information is stored in the RAM 308 in the detection signal storage area provided in advance for each sphere detection sensor, and the detection of each sphere detection sensor detected in the previous timer interruption process (about 1 ms before) Information on the presence or absence of a signal is read from the current detection signal storage area provided in the RAM 308 for each sphere detection sensor, and this information is stored in the previous detection signal storage area. Further, the detection signal of each sphere detection sensor detected this time is stored in the above-described current detection signal storage area.

  In step S204 and step S205, basic random number initial value update processing and basic random number update processing are performed. In these basic random number initial value update processing and basic random number update processing, the value of the initial value generation random number counter performed in step S110 is updated, and then the normal winning random number value and special value used in the main control unit 300 are updated. The two random number counters for generating the figure random number values are updated. For example, if the range of values that can be taken as a random number value for a normal winning number is 0 to 100, a value is acquired from a random number counter storage area for generating a normal winning random number value provided in the RAM 308, and 1 is added to the acquired value. Then, it is stored in the original random number counter storage area. At this time, if the result of adding 1 to the acquired value is 101, 0 is stored in the original random number counter storage area. If it is determined that the random number counter has made one round as a result of adding 1 to the acquired value, the value of the initial value generating random number counter corresponding to each random number counter is acquired and stored in the storage area of the random number counter. set.

  In step S206, effect random number update processing is performed. In this effect random number update process, a random number counter (hardware random number) for generating an effect random number used by the main control unit 300 is updated.

  In step S207, timer update processing is performed. As will be described in detail later, in this timer update process, the normal symbol display symbol update device for measuring the time for the symbol to be changed / stopped on the normal symbol display device 112, and the symbol to be changed / stopped to be displayed on the special symbol display device 114. Various timers including a special figure display symbol update timer for timing the time to perform, a timer for timing a predetermined winning effect time, a predetermined opening time, a predetermined closing time, a predetermined end effect period, etc. are updated. .

  In step S208, winning prize counter updating processing is performed. In this winning opening counter updating process, when there is a winning (winning) in the winning opening (the general winning opening 122, the first and second special figure starting openings 126, 128, and the variable winning opening 130), The value of the winning ball number storage area provided for each winning opening is read, and 1 is added to set the original winning ball number storage area.

  In step S209, a winning acceptance process is performed. In this winning acceptance process, if it is determined that the first and second special figure starting ports 126 and 128 are winning, and the number of special figure variable games held is less than four, the winning starting port is displayed. The corresponding hardware random number is acquired as a special figure winning random value. In addition, when it is determined that the winning of the general drawing start opening 124 is won, and the number of the pending variable floating games is less than two, the hardware random number corresponding to the winning starting opening is set as the normal winning random number value. Acquired and stored in a random value storage area different from that for the above-mentioned special figure provided in the RAM 308.

  In step S210, a payout request number transmission process is performed. The output schedule information and the payout request information output to the payout control unit 550 are composed of 1 byte, strobe information in bit 7 (indicating that data is set when on), and power supply in bit 6 Input information (when ON, indicates that this is the first command transmission after power-on), bits 4-5 indicate the current processing type (0-3), and bits 0-3 indicate the number of payout requests after processing I am doing so.

  In step S211, a normal state update process is performed. This normal state update process performs one of a plurality of processes corresponding to the normal state. For example, in a general diagram state update process during a normal map change (a general-purpose general-purpose timer value to be described later is 1 or more), on / off drive control for repeatedly turning on and off the 7-segment LED constituting the general map display device 112 is performed. Do.

  Also, in the normal state update process at the timing when the normal map change display time has elapsed (the timing when the value of the general map display symbol update timer has changed from 1 to 0), if the hit flag is on, When the 7-segment LED constituting the general-purpose display device 112 is turned on / off so as to be in the first mode, and the hit flag is off, the normal diagram is displayed as in the above-described normal mode. The 7-segment LED constituting the device 112 is controlled to be turned on / off, and then stored in a routine stop time management timer provided in the RAM 308 to maintain the display for a predetermined stop display period (for example, 500 msec). Information indicating the stop period is set in the area. With this setting, the usual figure is stopped and the result of the usual figure variable game is notified to the player.

  Further, in the normal state update process that starts at the timing when the predetermined stop display period ends (when the value of the normal stop time management timer value changes from 1 to 0), if the hit flag is on, the predetermined state is displayed. During the opening period (for example, 2 seconds), a signal for holding the blade member in an open state is output to the solenoid 330 for opening and closing the blade member of the second special figure starting port 128, and the blade opening time management provided in the RAM 308 is controlled. Information indicating the release period is set in the storage area of the timer.

  In the usual state update process that starts at the timing when the predetermined opening period ends (the timing when the value of the blade opening time management timer is changed from 1 to 0), the blade member has a predetermined closing period (for example, 500 milliseconds). A signal for holding the blade member in a closed state is output to the opening / closing drive solenoid 330, and information indicating the closing period is set in the storage area of the blade closing time management timer provided in the RAM 308.

  In the normal state update process that starts at the timing when a predetermined closing period has elapsed (the timing when the value of the blade closing time management timer changes from 1 to 0), the normal state is set to inactive. In the normal state update process when the normal state is inactive, the process proceeds to the next step S212 without doing anything.

  In step S212, a general drawing related lottery process is performed. In this general map-related lottery process, the open / close control of the general map variable game and the second special map start port 128 is not performed (the state of the general map is not in operation), and the pending general map variable game is not held. When the number is 1 or more, it is decided whether to win or not to win the result of the variable figure game by random lottery based on the random number value stored in the random number value storage area. When the winning judgment is made and the winning is made, the winning flag provided in the RAM 308 is set to ON. If unsuccessful, turn off the winning flag. Regardless of the result of the hit determination, next, the value of the random number counter for generating the normal figure timer random value is acquired as the normal figure timer random number value, and a plurality of fluctuation times are obtained based on the acquired general figure timer random number value. One time for displaying the variable map on the general map display device 112 is selected from among them, and this variable display time is stored in the general map variable time storage area provided in the RAM 308 as the normal map variable display time. In addition, the number of pending general figure variable games is stored in the usual figure pending number storage area provided in the RAM 308, and from the number of pending custom figure variable games each time a hit determination is made. The value obtained by subtracting 1 is re-stored in the usual figure number-of-holds storage area. Also, the random number value used for the hit determination is deleted.

  In step S213, special figure state update processing is performed. In the special figure state update process, one of the following eight processes is performed according to the state of the special figure. For example, in special figure state update processing during special figure fluctuation (the value of a special figure general-purpose timer to be described later is 1 or more), on / off drive control for repeatedly turning on and off the 7-segment LED constituting the special figure display device 112 is performed. Do.

  Also, in the special figure state update process that starts at the timing when the special figure change display time has elapsed (when the special figure display symbol update timer value changes from 1 to 0), the jackpot flag is on and the probability change flag is off In the special figure display device 114, the above-mentioned special figure 1, when the big hit flag is on and the probability variation flag is on, the special figure display device 114, and when the above special figure 2, the big hit flag is off, In order to maintain the display for a predetermined stop display period (for example, 500 msec) while performing the lighting / extinguishing drive control of the 7-segment LED constituting the special figure display device 112 so as to be in the above-described special figure 3 mode. The information indicating the stop period is set in the storage area of the special figure stop time management timer provided in the RAM 308. With this setting, the special figure is stopped and displayed, and the result of the special figure variable game is notified to the player. Further, 02H is additionally stored as transmission information (general information) in the transmission information storage area described above in order to execute the general command rotation stop setting transmission process in the command setting transmission process (step S215).

  Further, in the special figure state update process that starts at the timing when the predetermined stop display period ends (the timing at which the special figure stop time management timer value changes from 1 to 0), if the jackpot flag is on, a predetermined value is displayed. A special figure waiting time management timer provided in the RAM 308 for waiting for a period during which an image for notifying the player that a big hit by the decorative symbol display device 110 is started, that is, a bonus winning period (for example, 3 seconds) is displayed. Information indicating the winning effect period is set in the storage area. Further, 04H is additionally stored as transmission information (general information) in the transmission information storage area described above in order to execute the general command winning effect setting transmission process in the command setting transmission process (step S215).

  Also, in the special figure state update process that starts at the timing when the predetermined winning effect period ends (the timing when the special figure standby time management timer value changes from 1 to 0), a predetermined release period (for example, 29 seconds or A signal for holding the door member in an open state is output to the solenoid 330 for opening and closing the door member of the variable prize opening 130 (until a winning of a game ball of a predetermined number (for example, 10 balls) is detected in the variable prize opening 130). At the same time, information indicating the opening period is set in the storage area of the door opening time management timer provided in the RAM 308. Further, 10H is additionally stored as transmission information (general information) in the above-described transmission information storage area in order to execute the general command big prize opening release setting transmission process in the command setting transmission process (step S215).

  In the special figure state update process that starts at the timing when the predetermined opening period ends (the timing when the door opening time management timer value changes from 1 to 0), the predetermined closing period (for example, 1.5 seconds) is variable. A signal for holding the door member in the closed state is output to the solenoid 330 for opening and closing the door member of the winning opening 130, and information indicating the closing period is set in the storage area of the door closing time management timer provided in the RAM 308. To do. Further, 20H is additionally stored as transmission information (general information) in the above-described transmission information storage area in order to execute the general command big prize opening closing setting transmission process in the command setting transmission process (step S215).

  Further, in the special figure state update processing which is repeated at predetermined timing (for example, 15 rounds) and this door member opening / closing control is repeated a predetermined number of times (for example, 15 rounds), a predetermined end effect period (for example, 3 seconds), that is, by the decorative symbol display device 110 Information indicating the effect standby period is set in the storage area of the effect standby time management timer provided in the RAM 308 in order to set to wait for a period during which an image for informing the player that the jackpot is to be ended is displayed. Further, 08H is additionally stored as transmission information (general information) in the above-described transmission information storage area in order to execute the general command end effect setting transmission process in the command setting transmission process (step S215).

  Further, in the special figure state update process which starts at the timing when the predetermined end production period ends (the timing when the production standby time management timer value changes from 1 to 0), the special figure state is set to inactive. . In the special figure state update process when the special figure is in a non-operating state, nothing is done and the process proceeds to the next step S214.

  In step S214, special drawing related lottery processing is performed. In this special drawing-related lottery process, the opening / closing control of the special drawing variable game and the variable winning opening 130 is not performed (the state of the special drawing is inactive), and the number of the special drawing variable games held is 1 In the case described above, the jackpot determination is first performed among various lotteries using the jackpot determination table, the high probability state transition determination table, the timer number determination table, and the like. Specifically, it is determined whether or not the special figure winning random number value stored in the random value storage area in step S203 is within the numerical range of the lottery data for the first special figure starting port in the jackpot determination table. When the random number value is within the numerical range of the lottery data for the first special figure start opening, information indicating that the special figure variable game is won and the jackpot flag storage area provided in the RAM 308 is a big hit is set. (Here, setting the jackpot information in the RAM 308 is referred to as setting the jackpot flag to ON). On the other hand, when the special figure winning random number value is outside the numerical range of the lottery data for the first special figure starting port, it is determined that the special figure variable game is out of the game, and the jackpot flag storage area provided in the RAM 308 is out of the storage area. (In this case, setting outlier information in the RAM 308 is setting the jackpot flag off). Note that the number of special figure variable games held is stored in the special figure hold number storage area provided in the RAM 308. Each time a hit determination is made, the number of special figure variable games held is determined. The value obtained by subtracting 1 is stored again in this special figure reservation number storage area. In addition, the random number value used for the hit determination is deleted.

  If the jackpot flag is set to ON, then the probability variation transition determination is performed. Specifically, it is determined whether or not the special figure random value stored in the random value storage area in step S209 is within the numerical range of the transition determination random number, and when the special figure random value is within the numerical range of the lottery data. Sets information indicating the start of a special jackpot game in the storage area of the probability variation (probability variation) flag provided in the RAM 308. (Here, setting the special jackpot game start information in the RAM 308 is referred to as turning on the probability variation flag). On the other hand, if the special figure random number value is outside the numerical range of the lottery data, information indicating that the jackpot game is started is set in the storage area of the probability variation flag (here, the information on the start of the jackpot game is set). Setting in the RAM 308 is referred to as setting the probability variation flag off).

  Regardless of the result of the jackpot determination, the process for determining the timer number is performed next. Specifically, the value of the random counter for generating the special figure timer random value described above is acquired as the special figure timer random value. A timer number corresponding to the value of the jackpot flag and the timer random number range including the acquired special figure timer random number value is selected and stored in a predetermined timer number storage area provided in the RAM 308. Further, the fluctuation time corresponding to the timer number is stored as the special figure fluctuation display time in the special figure display symbol update timer, and the general command rotation start setting transmission process is executed in the command setting transmission process (step S215). For this reason, 01H is additionally stored as transmission information (general information) in the transmission information storage area described above, and the process ends.

  In step S215, command setting transmission processing is performed. The output schedule information (command) transmitted to the sub-control unit 400 is composed of 16 bits, bit 15 is strobe information (indicating that data is set when ON), bits 11 to 14 are Command type (basic command for 00H, symbol change start command for 01H, symbol change stop command for 04H, winning effect start command for 05H, end effect start command for 06H, end effect start command for 07H A jackpot round number designation command, a power recovery command in the case of 0EH, information indicating a command type such as a RAM clear command in the case of 0FH), and bits 0 to 10 are command data (a predetermined data corresponding to the command type Information).

  Specifically, the strobe information is turned on and off by command transmission processing. If the command type is a symbol variation start command, the command data includes information indicating the value of the jackpot flag, the probability variation flag, the timer number selected in the special symbol related lottery process, etc. If it is a case, it includes the value of the jackpot flag, the probability variation flag, etc. If it is a winning effect command and an end effect start command, it includes the value of the probability variation flag, etc. If it is a jackpot round number designation command The value of the probability variation flag, the number of jackpot rounds, etc. are included. When the command type indicates a basic command, device information in the command data, presence / absence of winning at the first special figure starting port 126, presence / absence of winning at the second special figure starting port 128, winning of the variable winning port 130 Includes presence or absence.

  In the general command rotation start setting transmission process described above, the command type is 01H, the jackpot flag value stored in the RAM 308 as the command data, the probability variation flag value, the timer number selected in the special drawing related lottery process, the pending Information indicating the number of special figure variable games being set is set. In the general command rotation stop setting transmission process described above, 04H is set as the command type, and information indicating the value of the jackpot flag, the value of the probability variation flag, etc. stored in the RAM 308 is set as the command data. In the above-described general command winning effect setting transmission process, the effect control information to be output to the decorative symbol display device 110, various lamps 420, and the speaker 416 during the winning effect period stored in the RAM 308 as the command type and 05H as command type Information indicating the value of the flag, the number of special figure variable games that are held, and the like are set. In the general command end effect setting transmission process described above, the effect control information to be output to the decorative symbol display device 110, various lamps 420, and the speaker 416 during the effect standby period stored in the RAM 308 as the command type is stored in the command type 06H. Information indicating the value of the flag, the number of special figure variable games that are held, and the like are set. In the general command big prize opening release transmission process described above, the information indicating the command type is 07H, the number of big hits stored in the RAM 308 as the command data, the value of the probability variation flag, the number of the special figure variable games held, etc. Set. In the above-described general command big prize closing setting transmission process, the information indicating the command type is 08H, the number of jackpot rounds stored in the RAM 308 as the command data, the value of the probability variation flag, the number of the special figure variable games held, etc. Set. In the sub-control unit 400, it is possible to determine the effect control according to the change of the game control in the main control unit 300 by the command type included in the received output schedule information, and the command data included in the output schedule information Based on this information, the contents of the effect control can be determined.

  In step S216, an external output signal setting process is performed. In this external output signal setting process, the game information stored in the RAM 308 is output to the information input circuit 652 that is separate from the pachinko machine 100 via the information output circuit 334.

  In step S217, device monitoring processing is performed. In this device monitoring process, the signal states of the various sensors stored in the signal state storage area in step 203 are read out to monitor whether there is a glass frame opening error or a lower pan full error, and so on. When a full error is detected, device information indicating whether or not there is a glass frame opening error or a lower pan full error is set in the transmission information to be transmitted to the sub-control unit 400. In addition, the solenoids 330 are driven to control the opening and closing of the second special figure starting port 128 and the variable prize opening 130, and the general diagram display device 112 and the special figure display device 114 are provided via the display circuits 322, 324, and 328. The display data to be output to the various status display units 326 and the like is set in the output port of the I / O 310. Further, the output schedule information set in the payout request number transmission process (step S210) is output to the sub-control unit 400 via the output port 310.

  In step S218, it is monitored whether or not the low voltage signal is on. Then, when the low voltage signal is on (when power supply shutoff is detected), the process proceeds to step S220. When the low voltage signal is off (power supply shutoff is not detected), the process proceeds to step S219.

  In step S219, timer interrupt end processing is performed. In this timer interrupt end process, the value of each register temporarily saved in step S201 is set in each original register, or interrupt permission is set.

  In step S220, the voltage monitoring circuit that monitors the voltage value of the power supplied from the power management unit 650 to the main control unit 300 outputs a voltage drop signal indicating that the voltage has dropped when it is equal to or lower than a predetermined value. Whether or not a power-off is detected. If a power-off is detected, a specific variable or stack pointer for returning to the power-off state at the time of power recovery is displayed. The return data is saved in a predetermined area of the RAM 308, and power interruption processing such as initialization of the input / output port is performed.

  <Timer update processing>

  Next, the timer update process in the above-described main control unit timer interrupt process will be described with reference to FIG. This figure is a flowchart showing the flow of timer update processing.

  In step S251, a 1-byte timer update process (details will be described later) is performed. After that, in step S252, a 2-byte timer update process (details will be described later) is performed and the process ends.

  <1 byte timer update processing>

  Next, the 1-byte timer update process in the above-described timer update process will be described with reference to FIGS. FIG. 11B is a flowchart showing the flow of the 1-byte timer update process, and FIG. 12 is a diagram showing an example of a program for the 1-byte timer update process and the 2-byte timer update process.

  In step S261, by reading from the I / O mapped memory using the above-described IN instruction, the I / O space corresponding storage area (in this example, 00 in the RAM 308) is stored in the 1-byte (8-bit) A register of the CPU 304. The value of the 1-byte special figure display symbol update timer stored in (address) is read (see (1) in FIG. 12).

  In step S262, 1 is added to the value read to the A register in step S261 (see (2) in FIG. 12), and in step S263, writing to the I / O mapped memory using the above-described OUT instruction is performed. The value of the A register of the CPU 304 is written into the special figure display symbol update timer stored in the I / O space correspondence storage area (address 00 in this example) of the RAM 308 (see FIG. 12 (3)). As a result of the processes in steps S261 to S263 described above, one value of the 1-byte special figure display symbol update timer is added.

  Next, in step S264, by reading the I / O mapped memory using the above-described IN instruction, the I / O space corresponding storage area (in this example, address 01) of the RAM 308 is stored in the 1-byte A register of the CPU 304. The value of the 1-byte long general symbol display symbol update timer stored in () is read (see (4) in FIG. 12).

  In step S265, 1 is added to the value read into the A register in step S264 (see (5) in FIG. 12), and in step S266, writing to the I / O mapped memory using the above-described OUT instruction is performed. Then, the value of the A register of the CPU 304 is written into the general-purpose display symbol update timer stored in the I / O space correspondence storage area (in this example, address 01) of the RAM 308 (see FIG. 12 (6)). By the processing of steps S264 to S266 described above, one value of the 1-byte long general symbol display symbol update timer is added. In step S267, the other one-byte timer is updated and the process is terminated.

  <2-byte timer update processing>

  Next, the 2-byte timer update process in the above-described timer update process will be described with reference to FIG. 11C and FIG. FIG. 11C is a flowchart showing the flow of the 2-byte timer update process.

  In step S271, by reading the memory mapped memory using the above-described LD instruction, the memory area corresponding to the memory space in the RAM 308 (addresses 2820 to 2821 in this example) is stored in the 2-byte (16-bit) length HL register of the CPU 304. ), The value of the 2-byte long special figure display symbol general purpose timer is read (see (7) in FIG. 12).

  In step S272, 1 is added to the value read to the HL register in step S271 (see (8) in FIG. 12). In step S273, the RAM 308 is written by writing to the memory-mapped memory using the LD instruction. The value of the HL register of the CPU 304 is written into the special symbol display symbol general-purpose timer stored in the memory space corresponding storage area (addresses 2820 to 2821 in this example) (see (9) in FIG. 12). By the processing of steps S271 to S273 described above, one value of the 2-byte special figure display symbol general-purpose timer is added.

  Next, in step S274, the memory mapped memory area of RAM 308 (in this example, address 2822) is read into the 2-byte (16-bit) length HL register of CPU 304 by reading from the memory-mapped memory using the above-described LD instruction. The value of the general-purpose display symbol general-purpose timer having a length of 2 bytes stored at address 2823 is read (see (10) in FIG. 12).

  In step S275, 1 is added to the value written in the HL register in step S274 (see (11) in FIG. 12), and in step S276, the RAM 308 is written by writing to the memory mapped memory using the above-described LD instruction. The value of the HL register of the CPU 304 is written in the general-purpose display symbol general-purpose timer stored in the memory space corresponding storage area (addresses 2822 to 2823 in this example) (see (12) in FIG. 12). By the process of steps S274 to S276, one value of the general-purpose display symbol general-purpose timer having a 2-byte length is added. In step S277, the other 2-byte timer is updated and the process is terminated.

  FIG. 13 is a diagram comparing the number of states (number of clocks) required for the IN instruction, OUT instruction, and LD instruction of the CPU 304 and the amount of program code between reading and writing to the I / O mapped memory and reading from and writing to the memory mapped memory. .

  First, consider a case where 1-byte data is transferred from the RAM 308 to the CPU 304 register (when 1-byte data is read from the RAM 308 to the CPU 304 register). By reading the I / O mapped memory using the above-described IN instruction, the I / O space corresponding storage area of the RAM 308 (in this example, the 10th I / O space) is stored in the 1-byte A register of the CPU 304. If the 1-byte data stored in the memory space corresponding storage area of the RAM 308 (in this example, address 2810 in the memory space) is read through the memory, the number of states is 11 and the program code amount is 2 bytes. It becomes. On the other hand, by reading from the memory-mapped memory using the above-described LD instruction, the CPU 304 stores the 1-byte A register in the memory space corresponding storage area of the RAM 308 (in this example, address 2810 in the memory space). When a 1-byte data is read, the number of states is 13 and the program code amount is 3 bytes. Therefore, when reading 1-byte data stored in the RAM 308, reading from the I / O mapped memory using the above IN instruction is more effective than reading from the memory mapped memory using the above LD instruction. By adopting the latter, it is possible to reduce the number of states by 2 states and the amount of program code by 1 byte.

  Next, consider a case where 1-byte data is transferred from the register of the CPU 304 to the RAM 308 (when 1-byte data is written from the register of the CPU 304 to the RAM 308). By writing to the I / O mapped memory using the above-described OUT instruction, the 1-byte data stored in the A register of the CPU 304 is converted into an I / O space corresponding storage area (in this example, an I / O space). In the case of writing to the memory space corresponding storage area of the RAM 308 (in this example, address 2810 of the memory space) via the address 10 of the space, the number of states is 11 states and the program code amount is 2 bytes. On the other hand, by writing to the memory-mapped memory using the above-described LD instruction, the 1-byte data stored in the A register of the CPU 304 is converted into a memory space corresponding storage area of the RAM 308 (in this example, address 2810 of the memory space). ), The number of states is 13, and the amount of program code is 3 bytes. Therefore, when writing 1-byte data in the RAM 308, writing to the I / O mapped memory using the OUT instruction is more suitable than writing to the memory mapped memory using the LD instruction. By adopting the latter, it is possible to reduce the number of states by 2 states and the amount of program code by 1 byte.

  Next, consider a case where 2-byte data is transferred from the RAM 308 to the register of the CPU 304 (when 2-byte data is read from the RAM 308 to the register of the CPU 304). By reading from the I / O mapped memory using the above-described IN instruction, the I / O space corresponding storage area of the RAM 308 (in this example, the 10th to 11th I / O space is stored in the 2-byte HL register of the CPU 304. 2 bytes long data stored in the memory space corresponding storage area of the RAM 308 (in this example, addresses 2810 to 2811 in the memory space) via the The number is 30 states and the program code amount is 6 bytes. On the other hand, by reading from the memory-mapped memory using the above-described LD instruction, the CPU 304 stores the 2-byte long HL register in the memory space corresponding storage area of the RAM 308 (in this example, addresses 2810 to 2811 in the memory space). In this case, the number of states is 16 states and the amount of program code is 3 bytes. Therefore, when reading 2-byte data stored in the RAM 308, reading from the memory-mapped memory using the above-described LD instruction is more effective than reading from the I / O-mapped memory using the above-described IN instruction. By adopting the latter, it is possible to reduce the number of states by 14 states and the amount of program code by 3 bytes.

  Finally, consider the case of transferring 2-byte data from the CPU 304 register to the RAM 308 (when writing 2-byte data from the CPU 304 register to the RAM 308). By writing to the I / O mapped memory using the above-described OUT instruction, the 2-byte length data stored in the HL register of the CPU 304 is converted into an I / O space corresponding storage area (in this example, an I / O space). When the memory space corresponding storage area of the RAM 308 (in this example, addresses 2810 to 2811) is written in twice via the space 10 address to 11 address, the number of states is 30 states. The amount of program code is 6 bytes. On the other hand, by writing to the memory-mapped memory using the above-described LD instruction, the 2-byte data stored in the HL register of the CPU 304 is converted into a memory space corresponding storage area of the RAM 308 (in this example, address 2810 of the memory space). In the case where data is written at once at addresses ~ 2811), the number of states is 16 and the program code amount is 3 bytes. Therefore, when writing 2-byte data to the RAM 308, reading from the memory mapped memory using the LD instruction is more suitable than reading from the I / O mapped memory using the IN instruction. By adopting the latter, it is possible to reduce the number of states by 14 states and the amount of program code by 3 bytes.

  As an example of transferring 2-byte data from the register of the CPU 304 to the RAM 308, LD C, 10H (2 bytes, 7 states) → IN L, (C) (2 bytes, 12 states) → INC C (1 byte) (4 states) → IN H, (C) (2 bytes, 12 states) is also conceivable, but the total is 35 states, 7 bytes. The reading from the memory mapped memory using the LD instruction is more advantageous than the reading from the I / O mapped memory using the IN instruction.

  <Sub control section main processing>

  Next, the sub control unit main process executed by the CPU 404 of the sub control unit 400 will be described with reference to FIG. This figure is a flowchart showing the flow of the main process of the sub control unit.

  The sub-control unit 400 is provided with a reset signal output circuit that outputs a reset signal when the power is turned on. The CPU 404 of the basic circuit 402 to which this reset signal has been input starts reset by a reset interrupt and executes processing in accordance with a control program stored in advance in the ROM 406. First, various initial settings are performed in step S301. In this initial setting, initial setting of input / output ports, initialization of various variables, and the like are performed.

  In step S302, command input processing (details will be described later) is performed.

  In step S303, a command is output to the sub control unit 500 via the output port of the I / O 410.

  In step S304, it is determined whether the value of a timer variable storage area described later is 10 or more. When the value of the timer variable storage area is 10 or more, the process proceeds to step S305, and when the value of the timer variable storage area is less than 10, the process proceeds to step S302.

  In step S305, 0 is stored in the timer variable storage area.

  In step S306, effect data update processing is performed. In this effect data update processing, the variation number stored in the variation pattern selection processing, which will be described later, the combination of temporary stop symbols, and the type of stop symbol combination are updated, and the process since the start of variation display of the decorative symbols Based on the time, the operation control data for controlling effects by the decorative display device 110, the shielding means 250, the speaker 416, the various lamps 420, the effect movable body of the effect device 200, and the like is updated.

  In step S306, a command to be output to the sub-control unit 500 in the process of step S303 to be executed next so that the decorative symbol variation display is performed in the manner indicated by the determined presentation information (for example, stopping the decoration 7 on the left side). For example, a command for operating the shielding means 250 and a command for operating the shielding means 250) are stored in a liquid crystal command storage area provided in the RAM 408. Prepare to control. Further, whether or not to execute a predetermined effect when a predetermined condition is satisfied, for example, whether or not to perform an effect using a chance button using a hardware random number acquired from the main control unit 300 And so on.

  In step S307, sound output processing is performed. In this sound output process, the audio data to be output to the speaker 416 included in the speaker control information acquired in step S306 is set in the output port of the I / O 410, and the sound source IC 418 performs output control of the speaker 416.

  In step S308, lamp control processing is performed. In this lamp control processing, data indicating lighting / extinguishing of lamps to be output to various lamps 420 included in the information for various lamp control acquired in step S306 is set in the output port of the I / O 410, and various lamps 420 are set. The display circuit 422 is controlled to turn on and off.

  In step S309, an effect driving device control process is performed. In the effect driving device control process, data indicating the operation timing included in the control information for the effect movable body acquired in step S306 is set in the output port of the I / O 410, and the effect movable object and the like are set. The drive device 424 for effect production controls the drive device 424 for each effect to be driven.

  The sub-control unit 400 repeatedly executes the processes of steps S302 to S309 thereafter, except for interruption by strobe processing, chance button processing, or sub-control unit timer interrupt processing, which will be described later.

  <Command input processing>

  Next, the command input process (step S302) in the sub-control unit main process will be described with reference to FIG. This figure is a flowchart showing the flow of command input processing.

  In step S401, the contents of a command storage area to be described later are confirmed, and it is determined whether or not an unprocessed command remains. If an unprocessed command remains in the command storage area, the process proceeds to step S402. If an unprocessed command does not remain in the command storage area, the process ends and returns to the sub-control unit main process. .

  FIG. 14C is a flowchart showing the flow of the variation pattern selection process, and FIG. 14D is a flowchart showing the flow of the symbol stop process. In step S402, based on the type of unprocessed command to be processed next among the unprocessed commands stored in the command storage area, the variation pattern selection process shown in FIG. This is executed based on the symbol variation start command), symbol stop processing shown in FIG. There are other processes based on unprocessed commands. For example, a round start command that is output from the main control unit 300 every time the opening control of the variable winning opening 130 is started during the jackpot and includes information indicating the number of opening of the variable winning opening 130 after the jackpot start is an unprocessed command. For example, a round start process performed in some cases. Other processing is omitted here.

  In step S501 of the variation pattern selection process, the value of the jackpot flag, the probability variation flag, and the timer number included in the unprocessed command are extracted and stored in the respective storage areas of the RAM 408. In addition, referring to the above-described variation number selection table or symbol determination table, effect data (in this embodiment, variation number, temporary stop symbol / stop symbol combination, etc.) is selected and stored in a storage area provided in the RAM 408. After that, the process ends.

  In step S601 of the symbol stop process, the three decorative symbols constituting the combination of the stopped symbols stored in the symbol storage area are displayed in the three displays of the left, middle and right symbol display areas 110a to 110c of the decorative symbol display device 110. The setting is made to display in the area, and the process ends. In the round start process, information indicating the number of times the variable winning opening 130 is opened after the jackpot start included in the unprocessed command is extracted and stored in the storage area of the RAM 408.

  <Strobe interrupt processing>

  Next, the strobe interrupt process of the sub control unit 400 will be described with reference to FIG. This figure is a flowchart showing the flow of strobe interrupt processing.

  This strobe interrupt process is a process executed when the sub control unit 400 detects a strobe signal output from the main control unit 300. In step S701 of the strobe interrupt process, the command output from the main control unit 300 is stored as an unprocessed command in the command storage area provided in the RAM 408.

  <Chance button interrupt processing>

  Next, the chance button interrupt process of the sub-control unit 400 will be described with reference to FIG. This figure is a flowchart showing the flow of chance button interrupt processing.

  This chance button interruption process is a process executed when the sub control unit 400 detects an operation of the chance button 146 by the chance button detection circuit 364.

  In step S801 of the chance button interrupt process, a value is acquired from the detection counter stored in the detection counter storage area of the RAM 408 for measuring the number of times the chance button 146 is pressed, and 1 is added to the acquired value. Store in the original detection counter storage area.

  <Variable update interrupt processing>

  Next, variable update interrupt processing executed by the CPU 404 of the sub control unit 400 will be described with reference to FIG. This figure is a flowchart showing the flow of variable update interrupt processing.

  The sub-control unit 400 includes a hardware timer that generates a timer interrupt at a predetermined cycle (once every 2 ms in this embodiment), and executes the variable update interrupt processing at a predetermined cycle triggered by this timer interrupt. To do.

  In step S901 of the variable update interrupt process, 1 is added to the value of the timer variable storage area of the RAM 408 and the result is stored in the original timer variable storage area. Therefore, in step S304, the value of the timer variable is determined to be 10 or more every 20 ms (2 ms × 10).

  As described above, the pachinko machine 100 according to the first embodiment has the first storage area (for example, the I / O space corresponding storage in the RAM 308) accessible from the CPU (for example, the CPU 304) via the I / O space. The game machine is characterized by comprising storage means (for example, RAM 308) having at least an area.

  According to the pachinko machine 100 according to the first embodiment, there are cases where the program code can be reduced as compared with the conventional case and the storage capacity of the storage unit can be reduced.

  The storage unit may further include a second storage area (for example, a memory space corresponding storage area of the RAM 308) accessible from the CPU via the memory space.

  With such a configuration, the first storage area and the second storage area of the storage unit can be properly used, and the program code can be reduced as compared with the conventional case and the storage capacity of the storage unit can be reduced. There is.

  Of the information stored in the storage means, at least a part of the first data length information (for example, 1-byte data such as a special symbol display symbol update timer or a common symbol display symbol update timer) Of the information stored in one storage area and stored in the storage means, information of a second data length that is longer than the first data length (for example, a special-figure display symbol general-purpose timer or a universal symbol display symbol general-purpose timer) Etc.) may be configured so as to be stored in the second storage area.

  With such a configuration, information can be stored in an appropriate storage area in accordance with the data length, and the storage capacity of the storage unit can be reduced in some cases.

  Of the information stored in the storage unit, all the information stored in the first storage area may be information of the first data length.

  With such a configuration, the data length of the information stored in the first storage means can be made one type, and the storage means can be used efficiently, and the data read / write speed can be increased. May be able to speed up.

  In addition, among the information stored in the storage unit, all the information of the first data length may be stored in the first storage area.

  With such a configuration, the data length of the information stored in the first storage means can be made one type, and the storage means can be used efficiently, and the data read / write speed can be increased. May be able to speed up.

  Further, the CPU is configured to access a first instruction (for example, an IN instruction or an OUT instruction) for accessing the first storage area of the storage unit and the second storage area of the storage unit. And at least a second instruction (for example, an LD instruction).

  With such a configuration, it is possible to clearly indicate an instruction for accessing the first storage area and an instruction for accessing the second storage area, improving the efficiency of program development and improving the maintainability of the program. In some cases, improvement can be achieved.

  The program code amount of the first instruction may be smaller than the program code amount of the second instruction.

  With such a configuration, by using the first instruction (first storage area) more frequently than the second instruction (second storage area), the program code can be reduced more than before, and the storage means In some cases, the storage capacity can be reduced.

  The program code amount of the address part included in the first instruction (for example, 10H which is the second operand of “IN A, 10H” in assembler language) is equal to the address part included in the second instruction (for example, The program code amount of the second operand of “LD A, 2810H” in assembler language 2810H) may be used.

  With such a configuration, by using the first instruction (first storage area) more frequently than the second instruction (second storage area), the program code can be reduced more than before, and the storage means In some cases, the storage capacity can be reduced.

  In addition, the address part included in the first instruction is a direct address system that directly specifies the address of the first storage area, and the address part included in the second instruction is the second storage area. A direct address method may be used in which the address is directly specified.

  With such a configuration, information may be stored in an appropriate storage area according to the address length, and the storage capacity of the storage unit may be reduced.

  In addition, in a gaming machine equipped with storage means (for example, RAM 308) accessed based on a memory request signal output by the CPU, the storage means is accessed based on the input of the IO request signal output by the CPU. In a game machine having a memory access signal output circuit (for example, an address decoder 342) for outputting a memory access signal for performing the operation, or having a storage means accessed based on a memory request signal output by the CPU A memory access signal for accessing the storage means based on the input of the IO request signal output from the CPU and the address information output from the CPU being a predetermined address. Memory access signal output times (E.g., the address decoder 342) may further comprise a.

  With such a configuration, it is possible to use both access based on the memory request signal and access based on the IO request signal, so that the program code can be reduced as compared with the conventional case, and the storage capacity of the storage means can be reduced. There is a case.

  Further, an address change circuit (for example, an address converter 340) that changes the address information output together with the IO request signal may be further provided.

  With such a configuration, it may be easy to use access based on the memory request signal and access based on the IO request signal.

  Further, the CPU may be configured to write or read data information to or from the storage unit based on the address information and the memory access signal.

  In the above-described embodiment, an example in which the present invention is applied to the CPU 304 and the RAM 308 of the main control unit 300 has been described. However, the present invention is not limited thereto, and for example, the CPU 404 and the RAM 408 of the sub-control unit 400, the payout control unit. The present invention may be applied to CPUs and RAMs of other control units such as a CPU and RAM (not shown) of 550.

  The information stored in the storage area accessible via the I / O space may be all 1-byte information. Further, all the information stored in the storage area accessible via the I / O space may be information that the CPU does not refer to other addresses using the address where the information is stored.

  In the above embodiment, the allocation target of the I / O mapped memory (the “storage unit” in the present invention) is the RAM. However, the present invention is not limited to this, for example, a ROM, a register, a cache memory, etc. Other storage means may be used and may be internal or external.

  In the above embodiment, an example is shown in which the I / O mapped memory is accessed by the direct address method in which the address where the data is stored is directly specified. However, the present invention is not limited to this, for example, relative You may access by an address system or an indirect address system. However, information accessed by the relative address method or the indirect address method using the 16-bit address assigned to the memory space is preferably assigned to the memory space.

  In addition, the various data exemplified below may be stored in a storage area that can be read and written by the I / O mapped memory, or may be stored in a storage area that can be read and written by the memory mapped I / O. For example, watchdog timer setting data, chip select selection data, external interrupt register setting data, maximum random number setting data, random number setting data, CTC setting data, initial setting data at power-on, input port Setting data, data related to timer control, data related to 7-segment display, data used when checking a winning opening, data related to the number of payouts sent from the main control unit to the payout control unit, and a transmission request to the sub-control unit Setting data, data related to commands to the sub-control unit, data used during testing to a predetermined testing institution, data related to normal symbol data, data related to external devices (such as rendering devices), data related to symbol variation time, symbols Of lottery data, random number data used for symbol lottery, symbol Data used to determine dynamic time, random number data used to determine whether the jackpot is a normal jackpot or a probability fluctuation jackpot, power status data, stack pointer evacuation data when the power is cut off, power Determination signal of input, data to be sent to the payout control unit, data to be output to the output port, data on the lamp rendering state, data on the display state of the special symbol, data on the display state of the normal symbol, special symbol winning / Data related to non-winning, data related to the number of balls won in the grand prize opening for judging the opening / closing of the big prize opening, data relating to the number of winnings under the starting opening for judging the number of symbol fluctuations, and a special design holding ball Data on numbers, data on the number of reserved balls of normal symbols, data on winning / non-winning of normal symbols, return of power interruption is correct Data indicating whether or not the interrupt function is limited, data relating to sensor detection, data for measuring the timing for updating the special symbol display symbol, and timing for updating the normal symbol display symbol Data, data for measuring the opening time of the glass frame, data for measuring the opening time of the inner frame, data on whether or not the saucer is full, a timer generally used for symbols, checksum Data for storing values, (Payout control unit) Data relating to the number of prize balls (payout) of game balls, data relating to connection with the CR unit, data relating to communication with the CR unit, drive control data for driving the motor Numerical data to be displayed on the 7-segment, data transmitted from the main control unit, data on gaming ball lending, main control unit Data for confirming connection, data for confirming whether the main control unit is operating, data for confirming whether data has been normally sent from the main control unit, and driving the dispensing device Data to be used for.

  Further, data for temporarily storing these various types of data may be stored in a storage area that can be read and written by the I / O mapped memory, or a storage area that can be read and written by the memory mapped I / O. May be stored.

  In the above embodiment, an example is shown in which the RAM space allocation setting for the memory space and the I / O space is performed in the initial setting 1 (step S101) of the main control unit main process. However, the present invention is not limited to this. Instead, the timing for setting the RAM allocation in the I / O space may be appropriately changed according to the processing status.

  For example, after the game machine is powered on, the RAM total value (the total value of the data stored in the predetermined storage area (storage area other than the checksum storage area) of the RAM) and the check stored in the checksum storage area When comparing with the sum value, it is not necessary to set the RAM allocation in the I / O space before calculating the total RAM value (from the time the power is turned on to the comparison of the checksum value. The RAM allocation setting of the / O space is not set, or the RAM allocation setting of the I / O space may be temporarily canceled before the checksum value is compared). This is because the RAM total value is generally calculated by advancing the address one by one from the start address of the predetermined storage area of the RAM to calculate the total value of data stored in the predetermined storage area. If the RAM data allocated to the space and the RAM data allocated to the I / O space coexist, it becomes impossible to calculate the RAM total value with the same instruction structure, which hinders the simplification of the program code. This is because there is a risk of increasing.

  In addition, when clearing all RAM areas (RAM clear), it is not necessary to set the RAM allocation in the I / O space (the RAM allocation setting in the I / O space is performed until the RAM is cleared). Or the RAM allocation setting in the I / O space may be temporarily canceled before the RAM is cleared. This is because when clearing RAM, it is common to advance the address one by one from the start address of the RAM area and assign a value of 0 from the start address to the end address. This is because it becomes impossible to prevent the simplification of the program code and increase the program code. Therefore, I / O space allocation is preferably set after the RAM is cleared.

  In addition, when calculating the checksum value at the time of power interruption, it is not necessary to set the RAM allocation in the I / O space (until the checksum value is calculated, the RAM allocation setting in the I / O space). Or the allocation setting of the RAM in the I / O space may be temporarily canceled before the checksum value is calculated). This is because when calculating the checksum value, the checksum value can be calculated using the data stored in the predetermined storage area by advancing the address one by one from the start address of the predetermined storage area of the RAM. However, if RAM data allocated to the memory space and RAM data allocated to the I / O space coexist, the checksum value cannot be calculated with the same instruction structure, and the program code can be simplified. This is because the program code may be increased. Therefore, it is preferable to cancel the RAM allocation setting in the I / O space after power interruption. Further, even when the stack pointer is saved in the RAM when power is interrupted, it is preferable to cancel the RAM allocation setting in the I / O space before saving.

  Also, the RAM data checksum allocated to the memory space and the RAM data checksum allocated to the I / O space may be provided separately in each storage area, and either one of the storages may be stored. They may be provided together in a region.

  Alternatively, a checksum value may be calculated for each storage area when power is cut off, a RAM total value may be acquired for each area when the power is turned on, and the respective values may be compared.

  In addition, since the I / O mapped memory is set when the power is cut off, the checksum value is calculated for each storage area, but the RAM of the I / O space is not allocated when the power is turned on (game) The RAM allocation in the I / O space is not set until the checksum is compared after the power is turned on, or even if the RAM allocation in the I / O space is temporarily canceled before the checksum value is compared. Therefore, the total value of each storage area may be acquired with the same instruction structure, and compared with the total value of the checksum for each storage area stored at the time of power interruption.

  In the present invention, the first area and the second area are continuous addresses, but may not be continuous.

  In addition, data input / output to / from a predetermined first storage area of the RAM 308 is performed by an IN (IN) instruction and an OUT (OUT) instruction, and data is input to a predetermined second storage area of the RAM 308. Although it is possible to reduce the amount of program by performing data input / output with a load (LD) instruction, it is necessary to reduce the amount of program when accessing an external device provided separately from the basic circuit 302. Although it is better to use the / out command, it may be configured to use the load command. When an external device is accessed by a load instruction, the program amount increases as compared with an in / out instruction, but data input / output to / from a predetermined first storage area in the RAM 308 is performed. By reducing the amount of the program by the out instruction, it is possible to contribute to the reduction of the program amount as compared with the game control circuit having the conventional configuration.

  In addition, the gaming machine described in the above-described embodiment can easily improve the program check and prevent malfunctions due to human factors such as program errors by simply controlling the game by reducing the program code. In the case of performing such simple game control, the basic circuit 302 is configured to transmit and receive information using an 8-bit (1 byte) width data bus. Since the circuit configuration can be simplified compared to a high-level configuration, malfunctions due to disturbances such as noise, and malfunctions due to human factors such as program mistakes and wiring mistakes can be prevented for more reliable game control. It is easy to realize and suitable. Further, by reducing the number of signal lines for transmitting a CS (chip select) signal output from the address decoder as much as possible, the address decoder has a signal line of substantially 1 byte width as in the gaming machine described in the embodiment. In this case, it is sufficient to decode the address information input by, and the configuration may be further simplified. However, as described above, since various game devices must be controlled reliably, RAM, ROM, etc. need to have a certain size, so that the address bus is configured with a 16-bit width. Game control is a fair game control with little time bias by starting another control (for example, starting the next interrupt process) after a predetermined time from a predetermined control start opportunity (for example, the start of the previous interrupt process). Is realized. Therefore, if each process constituting the game control can be completed in a short time if possible, another process cannot be started after a predetermined time because the predetermined process is prolonged. In some cases, the risk of defects (so-called processing failures) can be reduced. That is, by reducing the data capacity and speeding up the processing, it may be possible to perform more reliable game control.

  In order to reduce the data capacity and speed up the processing, the counter information provided in the RAM 308 with a size of 2 bytes as described above is a load instruction using a register (for example, an HL register) of 2 bytes. Information may be input and output, and the counter information provided in the RAM 308 with a size of 1 byte may be input and output with an in command. However, when a plurality of 1-byte counter information is continuously provided in the RAM 308 and the update times of the plurality of counter information are the same, each of the counter information included in the plurality of counter information Each time, the address of the first or last counter information out of a plurality of counter information is once registered in a 2-byte register (for example, an HL register). ) Is set by a load instruction, and the counter information to be processed is changed by advancing or returning the value of the register of the 2-byte configuration, and the counter information is updated by updating the counter information of the 2-byte configuration loaded with the address. It may be updated via a register (for example, “INC (HL)”). In this way, there is a case where it is possible to avoid a problem such as a drop in processing by slowing down the processing in consideration of only a reduction in data capacity. This is not limited to the counter information, and the same applies to a plurality of pieces of 1-byte width information of the same type continuously arranged in the RAM 308. For example, a storage area that stores 1-byte information scheduled to be output to each of a plurality of external devices may be applied to the plurality of pieces of the same type of 1-byte width. In other words, even if the size of the information is 1 byte, when the value of the register loaded with the address is updated and the same processing is performed on the address information indicated by the register, the load instruction is used instead of the in instruction and the out instruction. In some cases, it is preferable to arrange the input / output position. A 1-byte control flag having one meaning as a whole (for example, a flag indicating ON when one or a plurality of values such as FFH, A5H, and 5AH, and OFF indicating 00H) is an in instruction and an out instruction. You may arrange | position in the position which can input / output.

  In the above embodiment, an example of a pachinko machine using a game ball as a game medium is shown. However, the present invention is not limited to this, for example, a slot machine using a medal (coin) as a game medium. It is also applicable to. Hereinafter, an example of the slot machine will be described.

  <Overall configuration>

  First, the overall configuration of the slot machine 1100 will be described with reference to FIG. This figure shows an external perspective view of the slot machine 1100.

  The slot machine 1100 includes a substantially box-shaped main body 1101 and a front door 1102 attached to the front opening of the main body 1101. Inside the center of the main body 1101 of the slot machine 1100, three reels (left reel 1110, middle reel 1111, and right reel 1112) having a plurality of types of symbols arranged on the outer peripheral surface are stored. It is configured to be able to rotate inside. Each symbol is printed on the belt-like member at an appropriate interval, and the reels 1110 to 1112 are configured by sticking this belt-like member to a predetermined circular frame member. When viewed from the player, the symbols on the reels 1110 to 1112 are generally displayed in the vertical direction from the symbol display window 1113 so that a total of nine symbols can be seen. Then, by rotating the reels 1110 to 1112, the combination of symbols that can be seen by the player varies.

  Further, on the outer frame of the symbol display window 1113, line display LEDs (not shown) for informing an effective line and a winning line, which will be described later, are arranged by lighting control such as blinking and lighting.

  Further, in the slot machine 1100, an optical sensor (not shown) including a light projecting unit and a light receiving unit is provided in the vicinity of each of the reels 1110 to 1112. The light projecting unit and the light receiving unit of this optical sensor are provided. A light-shielding piece of a certain length provided on the reel passes between them. Based on the detection result of the sensor, the position of the symbol in the rotation direction on the reel is determined, and the reels 1110 to 1112 are stopped so that the target symbol is displayed on the winning line 1114.

  The winning line display lamp 1120 is a lamp that indicates an effective winning line. An effective winning line is determined in advance by the number of medals inserted into the slot machine 1100. Of the five winning lines 1114, for example, when one medal is inserted, the middle horizontal winning line is valid, and when two medals are inserted, the upper horizontal winning line and the lower horizontal winning line are added. When three medals are inserted and three medals are inserted, the five added with the right-down winning line and the upper-right winning line become effective as the winning line. The number of winning lines 1114 is not limited to five.

  The start lamp 1121 is a lamp that informs the player that the reels 1110 to 1112 are in a state of being able to rotate. The replay lamp 1122 indicates to the player that the current game can be replayed (the medal insertion is not required) when winning a replay game that is one of the winning games in the previous game. It is a lamp to inform. The notification lamp 1123 is a lamp that informs the player that a specific winning combination (for example, a bonus such as BB (Big Bonus) or RB (Regular Bonus)) is won internally in the internal lottery. The medal insertion lamp 1124 is a lamp that notifies that a medal can be inserted. The payout number display 1125 is a display for displaying the number of medals to be paid out to the player as a result of winning a winning combination. The number-of-games display 1126 is an indicator for displaying an error display when a medal is inserted, the number of games during a big bonus game (in a BB game), the number of winnings of a predetermined winning combination, and the like. The stored number display 1127 is a display for displaying the number of medals electronically stored in the slot machine 1100. The reel panel lamp 1128 is an effect lamp.

  The medal insertion buttons 1130 and 1131 are buttons for inserting a predetermined number of medals stored electronically in the slot machine 1100. In this example, every time the medal insertion button 1130 is pressed, a maximum of three are inserted one by one, and when the medal insertion button 1131 is pressed, three are inserted. The medal slot 1134 is an slot for a player to insert a medal when starting a game. That is, the medal can be inserted electronically by the medal insertion button 1130 or 1131, or an actual medal can be inserted from the medal insertion slot 1134. The settlement button 1132 is a button for settlement of medals electronically stored in the slot machine 1100 and bet medals, and discharging them to the medal tray 1156 from the medal payout opening 1155. The medal return button 1133 is a button for pressing and removing a medal when the inserted medal is clogged.

  The start lever 1135 is a lever-type switch for performing a game start operation. That is, when a desired number of medals are inserted into the medal insertion slot 1134 and the start lever 1135 is operated, the reels 1110 to 1112 are rotated as a trigger, and the game is started. The stop buttons 1137 to 1139 are buttons for performing a stop operation on the reels 1110 to 1112 that have started rotating by the operation of the start lever 1135, and are provided corresponding to the reels 1110 to 1112. When any one of the stop buttons 1137 to 1139 is operated, one of the corresponding reels 1110 to 1112 is stopped.

  Door key hole 1140 is a hole into which a key for unlocking front door 1102 of slot machine 1100 is inserted. The medal payout exit 1155 is a payout exit for paying out medals. The medal tray 1156 is a container for collecting medals paid out from the medal payout opening 1155. The medal tray 1156 employs a tray that can emit light in the first embodiment.

  The upper lamp 1150, the side lamp 1151, the center lamp 1152, the waist lamp 1153, and the lower lamp 1154 are decorative lamps for exciting games. The effect device 1190 includes, for example, a liquid crystal display device having a door device (shutter) 1163 that can be freely opened and closed, and various information such as a small role notification is displayed on the effect device 1190. The sound hole 1160 is a hole for outputting the sound of a speaker provided inside the slot machine 1100 to the outside. On the title panel 1162, a pattern for decorating the slot machine 1100 is drawn.

  <Control unit>

  Next, the circuit configuration of the main control unit 1300 of the slot machine 1100 will be described in detail with reference to FIG. This figure shows a circuit block diagram of the main control unit 1300.

  The control unit of the slot machine 1100 is roughly divided into a main control unit 1300 that controls the central part of the game and a sub control unit 1400 that controls various devices in accordance with commands transmitted by the main control unit 1300.

  The main control unit 1300 includes a CPU 1310 that is an arithmetic processing unit for controlling the entire main control unit 1300, a data bus and an address bus for the CPU 1310 to transmit and receive signals to and from each IC and each circuit, It has the structure described below. The clock correction circuit 1314 is a circuit that divides the clock generated by the crystal oscillator 1311 and supplies it to the CPU 1310. For example, when the frequency of the crystal oscillator 1311 is 12 MHz, the divided clock is 6 MHz. The CPU 1310 operates by receiving the clock divided by the clock correction circuit 1314 as a system clock.

  The CPU 1310 is connected to a timer circuit 1315 for setting a timer interrupt processing cycle for constantly monitoring the sensor and switch states and a motor drive pulse transmission cycle via a bus. When the power is turned on, the CPU 1310 transmits the frequency dividing data stored in the predetermined area of the ROM 1312 to the timer circuit 1315 via the data bus. The timer circuit 1315 determines an interrupt time based on the received frequency division data, and transmits an interrupt request to the CPU 1310 for each interrupt time. In response to this interrupt request, the CPU 1310 executes monitoring of each sensor and transmission of drive pulses. For example, if the system clock of the CPU 1310 is set to 6 MHz, the frequency division value of the timer circuit 1315 is set to 1/256, and the data for frequency division of the ROM 1312 is set to 44, the reference time for this interrupt is 256 × 44 ÷ 6 MHz = 1. 877 ms.

  Further, the CPU 1310 stores a ROM 1312 for storing various data such as a program for controlling each IC, lottery data used in the internal lottery of a winning combination, and a reel stop position, and for storing temporary data. A RAM 1313 is connected. Note that other storage means may be used for these ROM 1312 and RAM 1313, and this is the same in the sub-control unit 1400 described later.

  Further, an input interface 1360 for receiving an external signal is connected to the CPU 1310, and a medal insertion sensor 1320, a start lever sensor 1321, a stop button sensor 1322, and a medal insertion button are connected via the input interface 1360 at every interruption time. The sensor 1323, the settlement switch sensor 1324, and the medal payout sensor 1326 are detected, and each sensor is monitored.

  The start lever sensor 1321 is a sensor for detecting the operation of the start lever 1135. The stop button sensor 1322 is a sensor for detecting which stop button is pressed when any one of the stop buttons 1137 to 1139 is pressed. The medal insertion button sensor 1323 is a sensor for detecting which medal insertion button is pressed when any of the medal insertion buttons 1130 and 1131 is pressed. The settlement switch sensor 1324 is provided on the settlement button 1132. When the settlement button 1132 is pressed once, the stored medals and the bets placed are settled and paid out.

  Further, an input interface 1361 and output interfaces 1370 and 1371 are connected to the CPU 1310 via the address decode circuit 1350 to the address bus. The CPU 1310 transmits and receives signals to and from external devices via these interfaces. An index sensor 1325 is connected to the input interface 1361, and the index sensor 1325 goes high each time a light shielding piece provided on the reels 1110 to 1112 passes. When detecting this signal, the CPU 1310 determines that the reel has made one rotation, and resets the rotational position information of the reel to zero. The output interface 1370 includes a reel motor driving unit 1330 for controlling a motor for driving the reel, a hopper motor driving unit 1331 for driving the motor of the hopper 1172, and a game lamp 1340 (winning line display lamp 1120, start A lamp 1121, a re-playing lamp 1122, a notification lamp 1123, a medal insertion lamp 1124, etc.), a 7-segment (SEG) indicator 1341 (a payout number display 1125, a game number display 1126, a stored number display 1127, etc.); An external concentration terminal board 1450 described later is connected.

  In addition, the CPU 1310 generates a counter circuit 1318 that is used as a hardware random number counter that changes a numerical value in the range of 0 to 65535 every time a clock signal output from the crystal oscillator 1316 is received, and the counter circuit 1318 generates A latch circuit 1317 that acquires and holds hardware random numbers is connected.

  Further, an output interface 1371 for transmitting a command to the sub control unit 1400 is connected to the data bus of the CPU 1310. The information communication between the main control unit 1300 and the sub control unit 1400 is a one-way communication, and the main control unit 1300 transmits a command to the sub control unit 1400, but any command or the like from the sub control unit 1400 to the main control unit 1300 Cannot be sent.

  The present invention is applied to such a slot machine 1110, and at least a first storage area (for example, an I / O space corresponding storage area of the RAM 1313) accessible from a CPU (eg, CPU 1310) via an I / O space is provided. A slot machine 1100 including storage means (for example, RAM 1313) may be used.

  According to such a slot machine 1100, there are cases where the program code can be reduced as compared with the conventional case and the storage capacity of the storage means can be reduced.

  Further, for example, a game can be executed by applying the present invention to a game program that simulates the operation of a real machine such as a pachinko machine for a home game machine.

  Note that the actions and effects described in the embodiments of the present invention only list the most preferable actions and effects resulting from the present invention, and the actions and effects according to the present invention are described in the embodiments of the present invention. It is not limited to what was done. In addition, in some cases, the contents described in one configuration among a plurality of configurations described in the embodiments may be applied to other configurations to further widen the game width.

  The gaming machine according to the present invention can be applied to gaming machines represented by slot machines and gaming machines (such as pachinko machines).

DESCRIPTION OF SYMBOLS 100 Pachinko machine 102 Game board 104 Game area 110 Ornamental symbol display device 112 Ordinary figure display device 114 Special figure display device 122 General winning opening 124 General drawing start opening 126 First special figure starting opening 128 Second special figure starting opening 130 Variable winning prize Mouth 300 Main control unit 400, 500 Sub control unit 550 Discharge control unit 600 Launch control unit 650 Power management unit

Claims (2)

RAM for temporarily storing data;
A game table including a CPU for performing game control using data stored in the RAM,
The RAM is
A memory-mapped memory that is a second storage area in which data can be written through a memory space by an LD instruction when data is transferred from the CPU register to the RAM;
When transferring 1-byte data from the CPU register to the RAM, the 1-byte data can be written via the I / O space by an OUT instruction having a smaller program code amount than the LD instruction. An I / O mapped memory that is a first storage area
The CPU
Data is written to the second storage area of the RAM via the memory space by the LD instruction, and the I / O is written to the first storage area of the RAM by the OUT instruction different from the LD instruction. A game table characterized by writing data through a space. In claim 1,
The I / O mapped memory includes
A game table, wherein only 1-byte data is stored.