JPH02297627A - System for transfer of immediate data and execution of arithmetic instruction - Google Patents

Abstract

PURPOSE:To reduce the numbers of instruction bytes in the transfer and the arithmetic operation of immediate data by setting the (m) high-order bits of the immediate data of (n) bits on a dedicated register. CONSTITUTION:An immediate register 4 to store the (m) high-order bits of the immediate data of (n) bits(m<n) is provided. A register 2 stores the data of (n) bits calculated at an ALU 7 transiently, and a register 3 stores the (n-m) low-order bits of the data of (n) bits transiently, and the immediate register 4 stores the (m) high-order bits of the immediate of (n) bits. Also, the ALU 7 sets the data of (n) bits stored in the register 2 with an immediate data arithmetic instruction which designates only the (n-m) low-order bits of the data of (n) bits and a numeric value stored in the register 3 as the low-order bits, and executes an arithmetic operation with the data of (n) bits setting the numeric value stored in the immediate register 4 as the high-order bit. In such a way, the numbers of instruction bytes in the transfer and the arithmetic instruction can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to immediate data transfer and arithmetic instruction execution methods.

[Conventional technology]

Microcomputer instructions include data transfer instructions, arithmetic operation instructions, logical operation instructions, and one branch instruction.

There are stacks, Ilo, control instructions, etc., and the number of bytes making up the instruction system varies depending on the instruction.

A conventional immediate data transfer and arithmetic instruction execution method will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing an example of a conventional immediate data transfer and arithmetic instruction execution method.

Immediate data transfer shown in FIG.

The calculation instruction execution method is 16, which is calculated in ALU7.
Registers 1.2 and 1 that temporarily store bit data
The register 3 stores 6-bit data.

Next, its operation will be explained using a simple immediate data transfer instruction and an addition instruction.

MOVI R3,9723...-(1) ADDI
R3,0147-・--+2) First, in formula (1), register 3 stores 16-bit data of 9723(H). be.

Next, in equation (2), register 1 is 9723 (H
), and register 2 is 0147.
(H) 16 and cut data are stored.

Then, the ALU 7 adds the contents of register 1 and the contents of register 2 and stores the result in register 3.

The number of instruction bytes in equation (2) is (the number of instruction codes + 2 bytes).

[Problem to be solved by the invention]

In the conventional immediate data transfer and arithmetic instruction execution method described above, when the upper 8 bits of 16-bit data are 0, the number of instruction bytes is (number of instruction codes + 1) bytes; The number of bytes is (number of instruction codes + 2) bytes.

Therefore, even if there are many transfer instructions or arithmetic instructions in which the upper 8 bits have a certain value other than 0, the number of instruction bytes is (number of instruction codes + 2) bytes, which is a drawback.

[Means to solve the problem]

The immediate data transfer and arithmetic instruction execution method of the present invention is based on an ALU that performs arithmetic operations and logical operations, and an ALU that performs arithmetic operations and logical operations.
In an n-bit processor having first and second registers for temporarily storing numerical values to be operated on in U,
Upper m bits of n-bit immediate data (m
an), the first register temporarily stores the n-bit data calculated in the ALU, and the second register stores the n-bit data calculated in the ALU. Lower bit data (
n-m) bits, the immediate register stores the upper m bits of the n-bit data, and the ALU stores the lower m bits of the n-bit data.
) The n-bit data stored in the first register by an immediate data operation instruction that specifies only bits, and the numerical value stored in the second register as lower bits, are stored in the immediate register. By executing an operation with n-bit data using a numerical value as the upper bit, the number of instruction bytes of the n-bit immediate data transfer and operation instruction is reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

Immediate data transfer shown in FIG.

The arithmetic instruction execution method uses register 1 to temporarily store the 16-bit data calculated in the ALU, register 2 to temporarily store the lower 8 bits of the 16-bit data calculated in the ALU, and register 2 to temporarily store the 16-bit data calculated in the ALU. register 3 for storing, and immediate register 4 for storing the upper 8 bits of 16-bit immediate data.
and an ALU 7 that performs arithmetic operations and logical operations.

Next, the operation will be explained using a simple transfer instruction and an addition instruction.

MOVI IM, 01)I ・ ・ ・
・(3) MOVI R3,94H---+4)A
DDI R3,7LH ・ ・ ・ ・ (5) First, in 20, immediate register 4 is 01 (H
) stores the upper 7 bits of 16-bit immediate data. The number of instruction bytes for formula 0 is (number of instruction codes +
1) It is a part-time job.

Next, in G41, the register 3 stores 16-bit data 0194 (H) whose upper 8 bits are the contents of the immediate register 4. The number of instruction bytes in equation (2) is (the number of instruction codes + 1) bytes.

In 20, register 1 stores 16-bit data of 0194 (H), and register 2 stores 16-bit data 01 with the contents of immediate register 4 as the upper 8 bits.
71 (H) is stored.

Then, ALtJ7 adds the contents of register 1 and register 2 and stores this result in register 3.

The number of instruction bytes in formula (2) is (number of instruction codes + 1) bytes.

FIG. 2 is a diagram showing a second embodiment of the present invention.

Immediate data transfer shown in FIG.

The arithmetic instruction execution system uses register 1 to temporarily store the 16 bit data calculated in the ALU, register 2 to temporarily store the lower 8 bits of the 16 bit data calculated in the ALU, and register 2 to temporarily store the 16 bit data calculated in the ALU. register 3 for storing, and immediate register 4 for storing the upper 8 bits of 16-bit immediate data.
．． 5, a multiplexer 6 for selecting either immediate register 4 or immediate register 5, and ALU 7 for performing arithmetic operations and logical operations.

Next, the operation will be explained using a simple transfer instruction and an addition instruction.

MOVI IMI, OIH・---+6)MOV
I IM2. 20H...(TMVII R3
,86H---・(81ADI2 R3,37H・
(9) First, in equation (6), the immediate register 4 stores the upper 8 bits 01 (H) of the 16-bit immediate data.

And in Part 2, Immediate Register et al.
Upper 8 bits of 16-bit immediate data2
Store 0(H).

The number of instruction bytes in equations (6) and (7) is (the number of instruction codes + 1) bytes.

Next, in the second case, multiplexer 6 selects immediate register 4, and register 3 stores 16 bit data 0186 (H) whose upper 8 bits are the contents of immediate register 4. The number of instruction bytes for 2H is (number of instruction codes + 1) bytes.

In equation (9), register 1 stores the contents of register 3, and multiplexer 6 stores the contents of register 5.
is selected, and register 2 stores 16-bit data 2037 (
H) is stored.

Then, ALU7 adds the contents of register 1 and register 2 and stores the result in register 3.
The number of instruction bytes in equation (9) is (the number of instruction codes + 1) bytes.

〔Effect of the invention〕

The immediate data transfer and arithmetic instruction execution method of the present invention reduces the number of instruction bytes for immediate data transfer and arithmetic operations by setting the upper m bits of n-bit immediate data to a dedicated register. effective.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a block diagram showing a second embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional example.

Claims (1)

[Claims] In an n-bit processor having an ALU that performs arithmetic and logical operations, and first and second registers that temporarily store numerical values calculated in the ALU, the upper m bits (m< n), the first register temporarily stores n-bit data operated on in the ALU, and the second register stores n-bit data operated on in the ALU.
Lower (n-m) of n-bit data operated on
The immediate register stores the upper m bits of the n-bit data, and the ALU stores immediate data that specifies only the lower (n-m) bits of the n-bit data. the n-bit data stored in the first register by an arithmetic instruction;
Transferring n-bit immediate data by performing an operation with n-bit data in which the lower bit is the numerical value stored in the second register and the upper bit is the numerical value stored in the immediate register. , an immediate data transfer and arithmetic instruction execution method characterized by reducing the number of instruction bytes of an arithmetic instruction.