JPH0546379A - Data transfer system - Google Patents

Abstract

PURPOSE:To simultaneously execute a transfer of plural data by providing a continuous area transfer piece number designation register and an address offset designation register, and designating that which becomes a transfer object by plural general registers. CONSTITUTION:When it is decided to be an instruction for transferring plural data from plural continuous memory areas to plural registers, an address calculating part 10 fetches an effective address. In an instruction executing part 11, the fetched effective address is designated, a register list field in the instruction is referred to and to a general register 12 designated by a bit which becomes '1' in the beginning, data is transferred by 32 bits from an external memory 14. When one data transfer is finished, a memory address of the next data is designated in the instruction executing part 11. Subsequently, the value of a continuous area transfer piece number designation register 24 is subtracted by '1', and when its value is '0', the value of an address offset register 25 is added to the head address of an initial continuous memory area and it becomes the address of a second continuous memory area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device having a data transfer function, and more particularly to a data transfer system having a function of transferring a plurality of data with one instruction.

[0002]

2. Description of the Related Art Conventionally, a data processing device has, as a basic function, an instruction for transferring data between an external memory and an internal general-purpose register. Generally, it has an instruction to transfer a single data from a memory or register as a source to a memory or register as a destination. In recent years, this instruction has become highly functional and multiple data can be transferred at high speed with one instruction. A data processing device capable of doing so has also been commercialized.

Here, as an example of such a data processing device, by having a register list field for designating a plurality of registers in an instruction, a plurality of data are transferred between a plurality of registers and a continuous memory area. Sometimes a TRO with the ability to execute with one instruction
N specification 32-bit microprocessor (M32 / 10
0 User's Manual 1989).

Instructions for transferring a plurality of data between a continuous memory area and a plurality of registers include LDM and STM. Reference numeral 1 in FIG. 9 represents a mnemonic of an instruction LDM for transferring a plurality of data in a continuous memory area to a plurality of registers. In this mnemonic 1, the operand designating section 2 which is a section for designating an operand includes a leading address designating section 2a which is a section which designates a leading address of a memory to be transferred and which is capable of various address modifications.
32-bit general-purpose register groups R0, R1, ...
.., R15, and a register list portion 2b which is a portion for designating a register to which data is transferred. The 16-bit register list field included in the instruction is shown in detail in FIG. As in this register list field 3, each bit is M
General-purpose registers R0, R1, ... from the SB side in order
・ Used to specify R15.

The transfer instruction called LDM represented by mnemonic 1 in FIG. 9 calculates the address specified by the head address specifying section (src) 2a of the operand specifying section 2 in the instruction, and transfers it in the continuous memory area to be transferred. Set the start address, then register list field 3 in the instruction with the MSB
This is an instruction that is referred to from the side in the direction of arrow 4 in FIG. 10 and sequentially transfers data to the general-purpose register indicated by the bit that is 1.

FIG. 11 shows an example of a conventional data processing device.
TRON specification 32-bit microprocessor M32 / 1
00 and a part of an external memory. In the microprocessor 7, 8 is an instruction fetch section (hereinafter referred to as IF section) including an instruction queue 30 for prefetching instructions, and 9 is a decoder 31 for decoding instructions.
An instruction decode unit (hereinafter referred to as D unit) including 10 performs operand address calculation and fetches an execution address, an operand address calculation unit (hereinafter referred to as A unit)
Is. An execution unit 11 (hereinafter, referred to as an E unit) 11 executes an instruction. The E unit 11 includes, for example, 16 general-purpose registers 12 having a 32-bit length, a micro ROM 32, an arithmetic unit 33, and the like. A bus interface unit 13 inputs and outputs data. 14 is 8 bits (1
It is an external memory with addresses in bytes) and stores instructions and data. Reference numeral 15 is an external bus having a width of 32 bits, 15a is an external address bus, and 15b is an external data bus.

Next, the operation of this conventional example will be described with reference to FIGS. When the instruction represented by mnemonic 1 in FIG. 9 is read from the external memory 14 into the IF section 8, this instruction is sent to the D section 9 and decoded. Here, this instruction is judged to be an instruction to transfer a plurality of data from the continuous memory area to a plurality of registers, and is sent to the next section A 10. In the part A 10, of the part corresponding to the operand (operand designating part 2) in the instruction, the start address (start address designating part 2
In the portion corresponding to a), address calculation is performed by various address modifications as necessary, and the effective address is fetched and sent to the next E unit 11. Next, the E section 11 refers to the register list field 3 in the instruction from the MSB side, and stores 32 bits of data from the external memory 14 to the general-purpose register designated by the bit which is 1 for the first time on the external data bus 15b. Transfer through. When the transfer of one data is completed, the address is incremented by 4 in the E section 11, and the memory address of the next data is designated via the address bus 15a. The 16-bit register list field 3 is referred to all the way up to the LSB, the above-described operation is repeated, and when the data transfer from the external memory 14 to the general-purpose register 12 ends, the instruction ends.

In the instruction STM of transferring a plurality of data from a plurality of registers to a continuous memory area by one instruction,
The opposite operation is performed. That is, when the STM instruction is read from the external memory 14 into the IF unit 8, D
It is decoded by the section 9, and it is judged here that this instruction is an instruction to transfer a plurality of data from a plurality of registers to a continuous memory area, and is sent to the next section A 10. In the part A 10, of the part corresponding to the operand in the instruction, the part corresponding to the head address of the continuous memory area to be transferred is subjected to address calculation by various address modifications as necessary, and the effective address is fetched. Then, it is sent to the E section 11. Next, the E section 11 refers to the register list field 3 in the instruction from the MSB side and first
32 bits of data are transferred from the general-purpose register 12 designated by the bit to the external memory 14 through the external data bus 15b. When the transfer of one data is completed, the address is incremented by 4 in the E section 11, and the memory address of the data to be transferred next is specified via the address bus 15a. When the 16-bit register list field 3 is referenced up to the LSB, the above operation is repeated, and when the data transfer from the general-purpose register 12 to the external memory 14 is completed, the instruction is completed.

The operation of this data processing device will be described with reference to a specific example of the LDM instruction. Consider a case where the LDM instruction 16 shown in FIG. 12 is read by the microprocessor 7. LDM prefetched by the IF unit 8
The instruction 16 is sent to the D section 9 and decoded to determine that this instruction transfers a plurality of data from the continuous memory area to a plurality of registers. Since the source addressing method directly points to the start address of the memory to be transferred, in this case, the address H'1000 of the external memory becomes the start address of the continuous memory area of the source, and the address in A section 10 is It is sent to the E section 11 without any calculation. H '
Means a hexadecimal number. Next, the E section 11 executes the instruction. The register list field in the instruction represented by the mnemonic 16 in FIG. 12 is 3a shown in FIG.
It looks like. Referring to the register list field 3a in order from the MSB side, first, the designated bit of R0 has 1, so that 32 bits of data at the address H'1000 are transferred to the general-purpose register R through the external data bus 15b.
Transfer to 0 and increment address by 4. Next, since the bit indicating R1 also has 1, the next H '
The 32-bit data at address 1004 is transferred to the general-purpose register R1. Similarly, the data at the address H'1008 is transferred to the R2 register. Referring to the register list of FIG. 13, since the bits representing R3, R4, and R5 are 0, data is not transferred to these general-purpose registers R3, R4, and R5. The data of the address H'100c is transferred for 32 bits. Although the remaining bits of the register list field 3a are also referred to, but since the remaining bits are all 0, no transfer is performed and the execution of the instruction is terminated.

[0010]

In the conventional data processing apparatus, it is possible to transfer a plurality of data between a plurality of registers and a continuous area of the memory by one instruction by operating as described above. However, in order to transfer a plurality of data between a plurality of registers and a plurality of continuous memory areas, it was necessary to combine some instructions. Therefore, if there is an interrupt request during this period, there is a problem that the process is divided. Further, there is a problem that in order to perform interrupt prohibition processing between a plurality of plural data transfer instructions, it is necessary to execute interrupt prohibition processing before and after these instructions.

The present invention has been made to solve the above-mentioned problems, and is capable of transferring a plurality of data between a plurality of registers and a plurality of continuous memory areas at one time. The purpose is to provide a scheme.

[0012]

According to the data transfer method of the first aspect of the present invention, the first memory address is calculated by processing the addressing designation field (head address designation section 22a) when executing the transfer instruction. , The second memory address is calculated by adding the address offset value designated by the second register (address offset designation register 25) to the first memory address, and is the area from the first memory address. A continuous memory area for words specified by a register (continuous area transfer number specification register 24) and a register specification field (register list section 2)
When data is transferred to / from the general-purpose register specified in 2b) and the number of general-purpose registers specified in the register specification field is larger than the number of words specified in the first register, the remaining general-purpose registers , Data is transferred between the second memory address and a continuous memory area.

A data transfer system according to the invention of claim 2 is
When executing the transfer instruction, the addressing designation field is processed to calculate the first memory address, and the second memory address is calculated by adding the address offset value designated by the second register to the first memory address. And first
Data is transferred between the continuous memory area for the word specified by the first register and the general-purpose register specified by the third register, and is specified by the third register. When the number of the general-purpose registers thus created is larger than the number of words designated by the first register, data is transferred between the remaining general-purpose registers and the memory area continuous from the second memory address.

A data transfer system according to the invention of claim 3 is
When executing the transfer instruction, the addressing designation field is processed to calculate the first memory address, and the second memory address is calculated by adding the address offset value designated by the second register to the first memory address. And first
Data from the memory address of the general register specified by the first register, which is a continuous memory area specified by the first register, and the general register specified by the third register, which is one of the general registers. When the number of general-purpose registers specified by the third register is larger than the number of words specified by the first register, the remaining general-purpose registers and a memory area continuous from the second memory address are transferred. Data is transferred between the two.

A data transfer system according to the invention of claim 4 is
When executing the transfer instruction, the addressing specification field is processed to calculate the first memory address, and the second memory address is calculated by adding the address offset value specified in the address offset specification field to the first memory address. Then, data is transferred between the continuous memory area, which is the area from the first memory address and is the word specified by the number specification field, and the general-purpose register specified by the register specification field. When the number of general-purpose registers designated by is larger than the number of words designated by the number designation field, data is transferred between the remaining general-purpose registers and the memory area continuous from the second memory address.

[0016]

According to the first aspect of the invention, when the transfer instruction is executed, the first memory address is calculated by processing the addressing designation field, and the first memory address is designated by the second register. The second memory address is calculated by adding the address offset value. Data transfer is performed between the continuous memory area for the word designated by the first register, which is the area from the first memory address, and the general-purpose register designated by the register designation field. If the number of general-purpose registers specified in the register specification field is larger than the number of words specified in the first register, data transfer is performed between the remaining general-purpose registers and the memory area continuous from the second memory address. ..

According to the second aspect of the invention, when the transfer instruction is executed, the first memory address is calculated by processing the addressing designation field, and the first memory address is designated by the second register. The second memory address is calculated by adding the address offset value. Data transfer is performed between the continuous memory area for the word designated by the first register, which is the area from the first memory address, and the general-purpose register designated by the third register. If the number of general-purpose registers specified by the third register is greater than the number of words specified by the first register, the remaining general-purpose registers and the second general-purpose register
Data is transferred from the memory address of 1 to a continuous memory area.

In the third aspect of the invention, when the transfer instruction is executed, the first memory address is calculated by processing the addressing designation field, and the first memory address is designated by the second register. The second memory address is calculated by adding the address offset value. A region from the first memory address, which is a continuous memory region for words specified by the first register, and a third memory which is one of a plurality of general-purpose registers.
Data is transferred to and from the general-purpose register specified by the register. When the number of general-purpose registers specified by the third register is larger than the number of words specified by the first register, data transfer is performed between the remaining general-purpose registers and the memory area continuous from the second memory address. Be done.

In the invention of claim 4, when the transfer instruction is executed, the first memory address is calculated by processing the addressing designation field, and this first memory address is designated by the address offset designation field. The second memory address is calculated by adding the address offset value. Data transfer is performed between a continuous memory area, which is an area starting from the first memory address and has the number of words designated by the number designation field, and the general-purpose register designated by the register designation field. If the number of general-purpose registers specified in the register specification field is larger than the number of words specified in the number specification field, data transfer is performed between the remaining general-purpose registers and the memory area continuous from the second memory address.

[0020]

【Example】

(Embodiment 1) As an embodiment of the invention of claim 1,
It has 6 general-purpose registers of 32 bit length, and it uses a register for specifying the number of continuous area transfers, a register for address offset specification, and a register list field in an instruction to store a plurality of data in one instruction and a plurality of consecutive data in a plurality of registers. A data processing device that can transfer data to and from the memory area will be described with reference to FIGS.

An instruction for transferring a plurality of data between two discontinuous memory areas and a plurality of general-purpose registers is LDM2.
And STM2. Reference numeral 21 in FIG. 1 is a mnemonic L when the data processing device of this embodiment transfers a plurality of data from a plurality of continuous memory areas to a plurality of registers with one instruction.
It represents DM2. The operand designating section 22 that is a section that designates an operand includes a head address designating section 22a that is a section that designates a head address of a continuous memory area to be transferred, which is capable of various addressing modifications.
16 32-bit general-purpose register groups R0, R1, ...
The register list section 22b, which is a section for designating which register of R15 the data is transferred to. The register list field included in the instruction is shown in detail in FIG. Like the register list field 3, each bit sequentially designates the general purpose registers R0, R1, ..., R15 from the MSB side. 2 shows a continuous area transfer number designation register (first register), and 25 an address offset designation register (second register). The continuous area transfer number designation register 24 is composed of 4 bits and
It takes a value from 1 to 15. The address offset designation register 25 has 8 bits and can take a value from 0 to 256. When the transfer instruction LDM2 is executed, it is necessary to set the values in the continuous area transfer number designation register 24 and the address offset designation register 25 in advance.

FIG. 3 is a block diagram showing a part of the microprocessor and the external memory in the data processing apparatus of this embodiment. In FIG. 3, 8 in the microprocessor 7 is an instruction fetch section (hereinafter referred to as IF section) including an instruction queue 30 for prefetching instructions, and 9 is an instruction decoding section including a decoder 31 for decoding instructions (hereinafter D Part), 10 is an operand address calculation part (hereinafter referred to as A part) that calculates an address of an operand and fetches an execution address, and 11 is an execution part (hereinafter referred to as E part) that executes an instruction. Sixteen general-purpose registers 12 having a 32-bit length, a 4-bit continuous area transfer number designation register 24, an 8-bit address offset designation register 25, a micro ROM 32, and an arithmetic unit 33.
Etc. are included. A bus interface unit 13 inputs and outputs data. 14 is 8 bits (1 byte)
It is an external memory with addresses assigned to each unit and stores instructions and data. 15 is an external bus with a width of 32 bits,
The external bus 15 is an address bus 15a and a data bus 1
It consists of 5b.

Next, the operation of this embodiment will be described with reference to FIGS. When the instruction represented by the mnemonic 21 in FIG. 1 is read from the external memory 14 into the IF section 8, this instruction is sent to the D section 9 and decoded. Here, this instruction is determined to be an instruction to transfer a plurality of data from a plurality of continuous memory areas to a plurality of registers, and is sent to the next section A 10. In part A, of the part corresponding to the operand in the instruction (operand designating part 22), the part corresponding to the start address (start address designating part 22a) of the first continuous memory area to be transferred, if necessary, Address calculation is performed by various address modifications, and the effective address is fetched and sent to the next E section 11.
Next, in the E section 11, the register list field 3 in the instruction is referenced from the MSB side, and the external memory 14 is stored in the general-purpose register 12 designated by the first bit of 1.
32 bits of data are transferred from the external data bus 15b. When the transfer of one data is completed, the address is incremented by 4 in the E section 11, and the memory address of the next data is designated via the address bus.
Next, the value of the continuous area transfer number designation register 24 is decremented by 1, the content is checked, and if it is not 0, the data transfer is continued in the same manner as above, but when the value is 0, the first continuous memory area The value of the address offset register 25 is added to the start address to form the address of the second continuous memory area. All the 16-bit register list field 3 up to the LSB is referred to, and the above operation is repeated to end the instruction when the data transfer from the external memory 14 to the general-purpose register 12 is completed.

An instruction STM for transferring a plurality of data from a plurality of registers to a plurality of continuous memory areas with one instruction
In 2, the operation opposite to the above is performed. That is, S
When the TM2 instruction is read from the external memory 14 to the IF section 8, it is decoded by the D section 9, and here it is determined that this instruction is an instruction to transfer a plurality of data from a plurality of registers to a plurality of continuous memory areas. And sent to the next section A 10. In the part A 10, of the part corresponding to the operand in the instruction, the part corresponding to the start address of the first continuous memory area to be transferred is subjected to address calculation by various address modifications as necessary, and is effective. The address is fetched and sent to the next E section 11. Next, part E 11
Then, referring to the register list field 3 in the instruction from the MSB side, only 32 bits of data are transferred from the general-purpose register 12 designated by the bit which is 1 to the external memory 14 through the external data bus 15b. .. When the transfer of one data is completed, the address is incremented by 4 in the E section 11, and the memory address of the data to be transferred next is specified via the address bus 15a. Next, the value of the continuous area transfer number designation register 24 is decremented by 1, the content is checked, and if it is not 0, the data transfer is continued in the same manner as above, but when the value is 0, the first continuous memory area The value of the address offset register 25 is added to the start address to make the address of the next data transfer destination. When the 16-bit register list field 3 is referenced up to the LSB and the above operation is repeated to complete the transfer of data from the general-purpose register 12 to the external memory 14, the instruction ends.

The operation of the data processor of this embodiment is
A specific example of the M2 instruction will be described. This will be described with reference to the flowchart of FIG. Instruction 21 as shown in FIG.
Consider the case where a is read by the multiprocessor 7. The instruction 21a prefetched by the IF unit 8 (step S1) is sent to the D unit 9 and decoded (step S2), and this instruction transfers a plurality of data from a plurality of continuous memory areas to a plurality of registers. It is judged to be a thing. Also, the source addressing method is
Since it directly points to the start address of the memory to be transferred, in this case, the address H'1000 of the external memory 14 becomes the start address of the first continuous memory area of the source, and the A section 10 calculates the address (step S3). Need not be performed, and the data is directly sent to the E section 11. Then E
The instruction is executed in the section 11. A register list field in an instruction represented by a mnemonic such as 21a in FIG. 4 is as shown in 3b shown in FIG. When the register list field 3b is sequentially referred to from the MSB side (step S4) (step S5), since the designated bit of R0 has 1 (step S6), H'100 is set.
32 bits of data at address 0, external data bus 15b
Through the general register R0 (step S7),
The address is incremented by 4 (step S
8). When the data transfer is completed once, 1 is subtracted from the value 2 of the continuous area transfer number designation register 24a (step S
9) Looking at the contents (step S10), since it is 1, nothing is done and the reference of the register list is continued (step S4). Since there is 1 in the bit designating R1, the next 32-bit data at address H'1004 is transferred to the general-purpose register R1 (step S7). Similarly, the address is incremented by 4 (step S8), 1 is subtracted from the value 1 of the continuous area transfer number designation register 24a (step S9), and the content is 0, so the first continuous memory area '1 which is the start address of
000 to the value H'4 of the address offset register 25b
0 is added (step S11) to H'1040, which is used as the effective address of the data to be transferred next.

When the address is determined, reference to the register list is continued (steps S12, S13, S14) and R2
Since the bit indicating the register is 1, the data at the address H'1040 is transferred to the R2 register (step S15). When the address is incremented by 4 (step S16) and the register list is subsequently referred to (steps S12, S13, S14), R3, R4, R
Since the bit representing 5 is 0, no data is transferred to these registers, and 32 bits of data at address H'1044 are transferred to the R6 register having 1 (step S15). Further, the address is incremented by 4 (step S16), and the remaining bits of the register list are referred to (step S12). However, since all the remaining bits are 0, the transfer is not performed and the execution of the instruction is completed.

Next, the operation will be described with reference to FIGS. Since the content of the continuous area transfer number designation register 24a in FIG. 5 is B'0010 (B 'is binary), that is, H'2, as shown in FIG. The two pieces of data are read from consecutive memory areas. Since the general-purpose registers related to the transfer are R0, R1, R2, and R6 as shown in FIG. 6, the general-purpose register R0 receives 32-bit data from the address H'1000 and the general-purpose register R1 receives 32-bit data from the address H'1004. Read. Since only two data are continuously read, the next data is the content B'1000000 of the address offset designation register 25a, that is, H'4.
0 is read from H'1040 added to the start address H'1000 (see FIG. 6).

Further, for example, the instruction is LDM2 H'1000, (R0-R5, R8, R10), and the content of the continuous area transfer number designation register is B'0.
When 011 = H'3 and the content of the address offset designation register is H'60, three pieces of data are designated as H'100 at the head address of the external memory as shown in FIG.
Data is continuously transferred from address 0, and data from the 4th data is H '
H'1040 with 1000 plus offset value H'60
Transfer from address. Then, the execution of the instruction ends.

(Embodiment 2) In the above embodiment, an instruction has a register list field for designating a plurality of general-purpose registers to be transferred, and a plurality of general-purpose registers,
The data processing device capable of transferring a plurality of data between a plurality of general-purpose registers and a plurality of continuous memory areas using the continuous area number designation register and the address offset register has been described. To
The same effect can be obtained by using a dedicated register (third register) instead of having a register list for designating a plurality of general-purpose registers in an instruction.

(Third Embodiment) Further, according to the invention of claim 3, the number of general-purpose registers relating to the transfer is reduced by one, and one general-purpose register is used to indicate a register list (third register). The same effect can be obtained when used as.

(Embodiment 4) Also, according to the invention of claim 4, a register list for designating a plurality of general-purpose registers, a field for designating the transfer number of continuous areas and a field for designating an address offset are instructed. The same effect can be obtained even if it is used.

[0032]

As described above, according to the invention of claim 1,
When executing the transfer instruction, the addressing designation field is processed to calculate the first memory address, and the second memory address is calculated by adding the address offset value designated by the second register to the first memory address. And first
Data is transferred between the continuous memory area for the word specified by the first register, which is the area from the memory address specified by the first register, and the general-purpose register specified by the register specification field, and is specified by the register specification field. When the number of general-purpose registers is larger than the number of words specified by the first register, data is transferred between the remaining general-purpose registers and the memory area continuous from the second memory address. Multiple data can be transferred between multiple registers and multiple continuous memory areas by an instruction, and interrupt input can be suppressed during this time, so a series of processing can be performed without setting a time in the interrupt mask. This can be performed by division, and thus the processing efficiency is improved.

According to the second aspect of the invention, when the transfer instruction is executed, the addressing designation field is processed to calculate the first memory address, and the first memory address is designated by the second register. The second memory address is calculated by adding the address offset value, and the continuous memory area for the word specified by the first register, which is the area from the first memory address, is specified by the third register. Data is transferred between the general-purpose registers
If the number of general-purpose registers specified by the register is larger than the number of words specified by the first register, data is transferred between the remaining general-purpose registers and the memory area continuous from the second memory address. Therefore, the same effect as above can be obtained.

According to the third aspect of the invention, when the transfer instruction is executed, the addressing designation field is processed to calculate the first memory address, and the first memory address is designated by the second register. The second memory address is calculated by adding the address offset value, and the continuous memory area for the word designated by the first register, which is the area from the first memory address, and the general-purpose register When data is transferred between general-purpose registers specified by one third register, and the number of general-purpose registers specified by the third register is greater than the number of words specified by the first register. Since the data is transferred between the remaining general-purpose registers and the continuous memory area from the second memory address, the same effect as described above can be obtained.

Further, according to the invention of claim 4, when executing the transfer instruction, the addressing designation field is processed to calculate the first memory address, and the first memory address is designated by the address offset designation field. The second memory address is calculated by adding the specified address offset value, and is a region from the first memory address, which is a continuous memory region for the word designated in the number designation field and the register designation field. When data is transferred to / from the general-purpose register and the number of general-purpose registers specified in the register specification field is larger than the number of words specified in the number specification field, the remaining general-purpose registers and the second memory address are used. Since data is transferred between continuous memory areas, the same effect as above can be obtained. .

[Brief description of drawings]

FIG. 1 is a diagram showing a mnemonic of an instruction executed by a data processing device of an embodiment according to the invention of claim 1 to transfer a plurality of data from a plurality of continuous memory areas to a plurality of general-purpose registers.

FIG. 2 is a register list field included in an instruction to transfer a plurality of data from a plurality of continuous memory areas to a plurality of general-purpose registers, which is executed by the data processing device of this embodiment, a continuous area transfer number designation register, and an address offset. It is a figure which shows each content of a designated register.

FIG. 3 is a block diagram showing a configuration of a data processing device using a data transfer system according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of an instruction executed by the data processing device of this embodiment to transfer a plurality of data from a plurality of continuous memory areas to a plurality of general-purpose registers.

5 is a diagram showing an example of each content of a register list field, a continuous area transfer number designation register, and an address offset designation register included in the instruction shown in FIG. 4 of the data processing apparatus of this embodiment.

FIG. 6 is a diagram showing a continuous memory area and a discontinuous memory area in this embodiment.

FIG. 7 is a diagram showing a continuous memory area and a discontinuous memory area in this embodiment.

FIG. 8 is a flowchart of an example of an instruction executed in this embodiment to transfer a plurality of data from a plurality of continuous memory areas to a plurality of general-purpose registers.

FIG. 9 is a diagram showing a mnemonic of an instruction executed by a conventional data processing device to transfer a plurality of data from a continuous area of a memory to a plurality of general-purpose registers.

FIG. 10 is a diagram showing a register list field included in an instruction executed by a conventional data processing device to transfer a plurality of data from a continuous area of a memory to a plurality of general-purpose registers.

FIG. 11 is a block diagram showing a configuration of a conventional data processing device.

FIG. 12 is a diagram showing an example of an instruction executed by a conventional data processing device to transfer a plurality of data from a continuous area of a memory to a plurality of general-purpose registers.

FIG. 13 is a diagram showing the contents of a register list field included in the instruction shown in FIG. 12 in a conventional example.

[Explanation of symbols]

12 general-purpose register 14 external memory 22a start address designating section (addressing designating field) 22b register list section (register designating field) 24, 24a continuous area transfer number designating register (first register) 25 address offset designating register (second register) )

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[Procedure amendment]

[Submission date] June 17, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

Next, the operation of this conventional example will be described with reference to FIGS. When the instruction represented by mnemonic 1 in FIG. 9 is read from the external memory 14 into the IF section 8, this instruction is sent to the D section 9 and decoded. Here, this instruction is judged to be an instruction to transfer a plurality of data from the continuous memory area to a plurality of registers, and is sent to the next section A 10. In the part A 10, of the part corresponding to the operand (operand designating part 2) in the instruction, the start address (start address designating part 2
In the portion corresponding to a), address calculation is performed by various address modifications as necessary, and the effective address is fetched and sent to the next E unit 11. Next, in the E section 11, the effective add of the external memory 14 fetched in the A section 10 is performed.
Address is specified via the address bus 15a, the register list field 3 in the instruction is referenced from the MSB side, and only 32 bits of data from the external memory 14 are stored in the general-purpose register specified by the bit which is 1 for the first time. Transfer through the external data bus 15b. When the transfer of one data is completed, the address is incremented by 4 in the E section 11, and the memory address of the next data is designated via the address bus 15a. The entire 16-bit register list field 3 is referenced up to the LSB, and the above operation is repeated. When the transfer of data from the external memory 14 to the general-purpose register 12 ends, the instruction ends.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

An instruction for transferring a plurality of data between two discontinuous memory areas and a plurality of general-purpose registers is LDM2.
And STM2. Reference numeral 21 in FIG. 1 is a mnemonic L when the data processing device of this embodiment transfers a plurality of data from a plurality of continuous memory areas to a plurality of registers with one instruction.
It represents DM2. The operand designating section 22 that is a section that designates an operand includes a head address designating section 22a that is a section that designates a head address of a continuous memory area to be transferred, which is capable of various addressing modifications.
16 32-bit general-purpose register groups R0, R1, ...
The register list section 22b, which is a section for designating which register of R15 the data is transferred to. The register list field included in the instruction is shown in detail in FIG. Like the register list field 3, each bit sequentially designates the general purpose registers R0, R1, ..., R15 from the MSB side. 2 shows a continuous area transfer number designation register (first register), and 25 an address offset designation register (second register). The continuous area transfer number designation register 24 is composed of 4 bits and
It takes a value from 1 to 15. The address offset designation register 25 has 8 bits and can take a value from 0 to 255 . When the transfer instruction LDM2 is executed, it is necessary to set the values in the continuous area transfer number designation register 24 and the address offset designation register 25 in advance.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

Next, the operation of this embodiment will be described with reference to FIGS. When the instruction represented by the mnemonic 21 in FIG. 1 is read from the external memory 14 into the IF section 8, this instruction is sent to the D section 9 and decoded. Here, this instruction is determined to be an instruction to transfer a plurality of data from a plurality of continuous memory areas to a plurality of registers, and is sent to the next section A 10. In part A, of the part corresponding to the operand in the instruction (operand designating part 22), the part corresponding to the start address (start address designating part 22a) of the first continuous memory area to be transferred, if necessary, Address calculation is performed by various address modifications, and the effective address is fetched and sent to the next E section 11.
Next, in the E section 11, the external memory fetched in the A section 10
Specify 14 effective addresses via address bus 15a
Then, referring to the register list field 3 in the instruction from the MSB side, the data from the external memory 14 is stored in the general-purpose register 12 designated by the bit which is 1 at the beginning.
Only 2 bits are transferred through the external data bus 15b.
When the transfer of one data is completed, the address is incremented by 4 in the E section 11, and the memory address of the next data is designated via the address bus. Next, the value of the continuous area transfer number designation register 24 is decremented by 1, the content is checked, and if it is not 0, the data transfer is continued in the same manner as above, but when the value is 0, the first continuous memory area The value of the address offset register 25 is added to the start address to form the address of the second continuous memory area. 16
All the bits up to the LSB of the register list field 3 of the bit are referenced, and the above operation is repeated to execute the external memory 1
When the data transfer from 4 to the general register 12 is completed, the instruction ends.

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 10

[Correction method] Change

[Correction content]

[Figure 10]

[Procedure Amendment 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 13

[Correction method] Change

[Correction content]

[Fig. 13]

Claims (4)

[Claims] 1. A general-purpose register having a plurality of 1-word lengths and a first register for specifying the number of words in a continuous area on a memory.
And a second register for designating an address offset value, the data processing apparatus has a transfer instruction for transferring data between the memory and the plurality of general-purpose registers, and the transfer instruction is on the memory. Addressing designation field for specifying the address of the general purpose register and a register designation field for designating one of the general-purpose registers to be transferred, and processing the addressing designation field when executing the transfer instruction. Then, the first memory address is calculated, and the second memory address is calculated by adding the address offset value designated by the second register to the first memory address.
Data is transferred between a continuous memory area, which is an area from the first memory address and is equivalent to the word designated by the first register, and a general-purpose register designated by the register designation field. The number of general-purpose registers specified in the register specification field is the first
If the number of words is larger than the number of words specified by the register, the data transfer method is characterized in that data is transferred between the remaining general-purpose register and a memory area continuous from the second memory address. 2. A general-purpose register having a plurality of 1-word lengths, and a first register for specifying the number of words in a continuous area on a memory.
Of the memory, the second register for designating an address offset value, and the third register for designating one of the general-purpose registers to be transferred. The transfer instruction has a transfer instruction for transferring data between a plurality of general-purpose registers, and the transfer instruction has an addressing designation field for specifying an address on the memory. When the transfer instruction is executed, the addressing designation field is processed. Then first
Is calculated, and the second memory address is calculated by adding the address offset value designated by the second register to the first memory address, and is the area from the first memory address. The continuous memory area for the word designated by the first register and the third memory
When data is transferred between the general-purpose registers specified by the register, and the number of general-purpose registers specified by the third register is larger than the number of words specified by the first register, the remaining general-purpose register is used. A data transfer method characterized in that data is transferred between a register and a memory area continuous from the second memory address. 3. A plurality of general-purpose registers each having a one-word length and a first register for specifying the number of words in a continuous area on a memory.
Of the general purpose registers and the second register for specifying the address offset value, the one of the plurality of general purpose registers is designated as the transfer target of the plurality of general purpose registers. Used as a third register, it has a transfer instruction for transferring data between the memory and the plurality of general-purpose registers, and the transfer instruction is
An addressing designation field for specifying an address on the memory is provided, and when the transfer instruction is executed,
The addressing specification field is processed to calculate a first memory address, the address offset value specified in the second register is added to the first memory address to calculate a second memory address, and the second memory address is calculated. Data is transferred between a continuous memory area, which is an area from the first memory address and is equivalent to the word specified by the first register, and the general-purpose register specified by the third register. When the number of general-purpose registers specified by the register is larger than the number of words specified by the first register, data transfer is performed between the remaining general-purpose registers and the memory area continuous from the second memory address. A data transfer method characterized by: 4. A data processing device having a plurality of general-purpose registers each having a one-word length, having a transfer instruction for transferring data between a memory and a plurality of general-purpose registers, wherein the transfer instructions are consecutive in the memory. A number specification field that specifies the number of words in the area, an address offset specification field that specifies the address offset value, an addressing specification field that specifies the address on the above memory, and a transfer target among the above general registers. And a register designation field for designating the address instruction designation field, when the transfer instruction is executed, the addressing designation field is processed to calculate a first memory address, and the address offset designation field is set to the first memory address. The second memory add by adding the address offset value specified in Is calculated and the data is transferred between the continuous memory area, which is the area from the first memory address and is the word designated by the number designation field, and the general-purpose register designated by the register designation field. If the number of general-purpose registers specified in the register specification field is larger than the number of words specified in the number specification field, the remaining general-purpose registers and the memory area continuous from the second memory address A data transfer method characterized in that data is transferred between them.