JP2002346189A - Pinball game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of time control of timing that is the same as before, even if a CPU(central processing unit) provides an interruption prohibiting state. SOLUTION: A primary control board and a put-out control board that structure the Pachinko machine obtain a counter value DW of a counter 70 inside a one-chip microcomputer at a backup operation followed by a service interruption, or the like, recognizing the number of prize balls or the number of balls in advance by a switch detecting process whenever the counter value DW reaches a specified value n1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ball-and-ball game machine such as a pachinko machine, and more particularly to a game machine capable of performing the same time management as before even when a CPU is in an interrupt disabled state.

[0002]

2. Description of the Related Art Generally, a ball-and-ball game machine such as a pachinko machine has a symbol start port provided on a game board, symbol display means for changing a plurality of symbols for a predetermined time and then stopping, and opening and closing plates for opening and closing. It is configured to have a large winning means. Then, when the detection switch provided at the symbol starting port detects the passage of the game ball, the symbol display means fluctuates the display symbol for a predetermined time, and thereafter, when the special symbols are aligned and stopped, the big winning means functions. A profit state advantageous to the player is generated.

In this type of gaming machine, a big hit counter C
T is realized by software and the jackpot probability is 1
In the case of / N, the big hit counter CT is circulated within the numerical range of 0 to N-1. This big hit counter C
The value of T is extracted as a random number value RND for lottery on condition that the detection switch of the symbol starting port detects a game ball, and when the extracted random number value RND for lottery matches the jackpot winning value Hit, The special symbols are controlled so as to be aligned in the stopped state after the symbol display means changes.

In such a gaming machine, the value of the big hit counter CT is updated in an interrupt control program by a timer interrupt for the purpose of updating the big hit counter CT at fixed time intervals, and the game control operation is substantially performed. All the necessary parts are processed by the interrupt control program. Typically, as shown in FIG. 14, a game control program for realizing a game operation includes an infinite loop process ST41 repeated in an infinite loop and an infinite loop process S
Interrupt signal INT due to timer interrupt during execution of T41
And an interrupt process ST42 executed in response to the request.

By the way, since there is a possibility that the power supply to the gaming machine is suddenly cut off due to a power failure or the like, the power supply voltage is reduced so that the unexpected situation can be effectively dealt with and the game can be resumed normally after the power is restored. CPU (hereinafter Z8)
0CPU), the highest priority interrupt NMI (Non Mas
It is possible to save the game state in the interrupt processing program by applying kable interrupt). In such an invention, necessary data is stored in the RAM area by interrupt processing in response to the NMI, backup power is supplied to the RAM area to maintain the contents, and when the power supply voltage is restored, the backup data is read. To reproduce the game operation before the interruption.

[0006]

Such an invention is excellent in that it can accurately reproduce a game interrupted by a power failure or the like, but further improvement is desired. That is, when the highest priority interrupt NMI is applied to the CPU in response to the drop of the power supply voltage, the interrupt process is started in any operation state of the CPU (except in a special case where the BUSREQ terminal is at the L level). On the other hand, since the subsequent CPU is in the interrupt disabled state, there is a problem that time management by the timer interrupt INT cannot be performed in the interrupt processing program.

Although it is possible to provide a dedicated hardware timer to cope with such a problem, it is not necessary to add a dedicated timer circuit for extremely rare situations such as the occurrence of a power failure. Not appropriate as a measure.

The present invention has been made in view of such a problem, and has been made without any additional circuit elements.
It is an object of the present invention to provide a gaming machine capable of managing the time at the same timing as before even when the PU is in the interrupt disabled state.

[0009]

In order to solve the above-mentioned problems, the present invention provides a payout control board for controlling a payout device for paying out game balls to a player, and a main control board for mainly controlling a game operation. Power supply monitoring means for monitoring a power supply voltage supplied to the payout control board or the main control board; and interrupting the game operation and restarting the game operation on condition that the power supply monitoring means detects an abnormal state. Backup means for storing necessary information, wherein the main control board and / or the payout control board have a memory storing a game control program, and a CPU operating based on the control program;
The main control board and / or the dispensing control board acquire a count value of the counter when the backup means operates, and based on the acquired value, when the backup means operates. To detect the passage of the game ball.

During the game operation, it is preferable to perform a game ball passage detecting operation in response to an interrupt signal generated from the counter each time the count value reaches a predetermined value. Also,
Prior to or after the operation of detecting the passage of the game ball, a process of obtaining the count value and waiting for the value to reach a predetermined value is typically performed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described based on a card-type ball game machine which is one embodiment of the present invention. FIG. 1 is a perspective view showing the pachinko machine 2 of the present embodiment, and FIG. 2 is a side view of the pachinko machine 2.

A pachinko machine 2 shown in FIG. 1 has a rectangular wooden outer frame 3 detachably mounted on an island structure, and an outer frame 3.
And a front frame 4 that is pivotally attached to be openable and closable via a hinge H fixed to the front frame 4. In addition, this pachinko machine 2
A plurality of pachinko parlors are arranged in the length direction of the island structure while being electrically connected to the card-type ball lending machine 1.

A game board 5 is detachably mounted on the front frame 4 pivotally attached to the outer frame 3 via the hinge H from the back side, and a glass door having a window corresponding to the front side of the game board 5. The front panel 6 and the front panel 7 are pivotally connected to each other so as to be freely opened and closed. An upper plate 8 for storing game balls for firing is attached to the front plate 7, and a front frame 4 is provided.
The lower part 9 is provided with a lower plate 9 for storing game balls overflowing or withdrawn from the upper plate 8 and a firing handle 11 of a firing means 10.

The firing means 10 includes a firing handle 11 which can be rotated and a firing motor for firing a game ball with a hitting hammer 12 (FIG. 4) with a hitting force corresponding to the turning angle of the firing handle 11. Have. On the right side of the upper plate 8,
An operation panel 13 for ball lending operation for the card-type ball lending machine 1 is provided. The operation panel 13 has a card balance display section 13a for displaying the card balance with three digits, and a game ball for a predetermined amount. Ball lending switch 1 for ball lending
3b and a return switch 13c for instructing a return of the card at the end of the game.

As shown in FIG. 3, the game board 5 is provided with a substantially annular guide rail 15 composed of an outer rail and an inner rail made of metal. Color liquid crystal display 16, symbol starting means (symbol starting and winning means) 17, opening and closing winning means (large winning means) 18, a plurality of normal winning means 19 (open and closed winning means 18 in addition to the normal winning means 19 in the upper stage) 6) normal winning means 19) on the left and right sides of the two gates 20
(Passing ports) are respectively provided at predetermined positions.

The liquid crystal display 16 functions as first symbol display means 22 for displaying a variable symbol and displaying a background image and moving images of various characters. The first symbol display means 22 displays the background image and the character in an animated manner, and displays three (left,
(Medium, right) symbol display sections 22a to 22c, and on the condition that a game ball wins in the symbol starting means 17, the display symbols of the symbol display sections 22a to 22c fluctuate for a predetermined time (scroll display). Then, the game stops in the stop symbol pattern determined based on the lottery result according to the timing of winning the game ball to the symbol starting means 17.

Immediately above the liquid crystal display 16, ordinary winning means 19 and second symbol display means 23 are provided. The second symbol display means 23 has an ordinary symbol display unit for displaying one ordinary symbol, and when a game ball passing through the gate 20 is detected, the symbol displayed on the ordinary symbol display unit fluctuates for a predetermined time, When the game ball passes through the gate 20, a stop symbol determined by the random number for the lottery selected by the lottery is displayed and stopped. The symbol starting means 17 is an electric tulip having a pair of left and right opening and closing claws 17a which can be freely opened and closed. When the stopped symbol after the change of the second symbol display means 23 hits and the symbol is displayed, the opening and closing claw 17a is It is opened only for a predetermined time and it becomes easy to win a prize.

The open / close prize unit 18 has an open / close plate 18a which can be opened forward. When the stop symbol after the change of the first symbol display unit 22 is a hit symbol such as "777", a "big hit" is set.
Is started, and the opening / closing plate 18a is opened to the front side. The specific area 1 is provided inside the opening / closing prize means 18.
8b, and when the winning ball passes through the specific area 18b, the special game is continued. Here, the special game state corresponds to a state advantageous to the player.

After the opening and closing plate 18a of the opening and closing winning means 18 is opened, a predetermined time has elapsed or a predetermined number (for example, 10
) Game balls win and the open / close plate 18a closes,
If the game ball does not pass through the specific area 18b, the special game is terminated, but if the game ball passes through the specific area 18b, the special game is continued up to, for example, 16 times at maximum, and is controlled in a state advantageous to the player. Is done.

As shown in FIG. 4, on the back side of the front frame 4, a back mechanism plate 30 for pressing the game board 5 from the back side is detachably mounted, and the back mechanism plate 30 has an opening 30a formed therein. A prize ball tank 33 and a tank rail 34 extending from the prize ball tank 33 are provided on the upper side thereof. Dispensing means 35 connected to the tank rail 34 is provided on a side portion of the back mechanism plate 30, and is provided below the back mechanism plate 30. Is provided with a passage unit 36 connected to the dispensing means 35. Dispensing means 35
Are paid out to the upper plate 8 from the upper plate discharge port 8a (FIG. 1) via the passage unit 36.

At the opening 30a of the back mechanism plate 30, a back cover 37 mounted on the back side of the game board 5 and prize means 17 to
A prize ball discharge gutter (not shown) for discharging the game ball that has won the prize 19 is fitted respectively. A main control board 39 is disposed inside a case 38 attached to the back cover 37,
A symbol control board 40 is provided on the front side (FIG. 2). Below the main control board 39, a lamp control board 42 is provided inside a case 41a attached to the back cover 37, and a sound control board 43 is provided inside a case 41b adjacent to the case 41a.

A power supply board 45 and a payout control board 46 are provided inside the case 44 mounted on the back mechanism plate 30 below these cases 41a and 41b. As shown in FIG. 3, a power switch 8
0 and an initialization switch 85 are arranged. The case 44 is cut off at the portions corresponding to the switches 80 and 85, and each of the switches 80 and 85 can be simultaneously operated by a finger.

A firing control board 48 is provided inside a case 47 mounted on the rear side of the firing means 10. These control boards 39-40, 42-43, 45-4
6, 48 are independent boards, and control boards 39, 40, 42, 43, excluding the power supply board 45 and the emission control board 48.
A computer circuit including a one-chip microcomputer is mounted on the main control board 39 and other control boards 4.
0, 42, 43, and 46 are electrically connected to each other through connectors using a plurality of signal lines.

As shown in FIG. 5, the main control board 39 and the other control boards 40, 42, 43, 46 are electrically connected via a plurality of signal lines via connectors. A control command for executing a predetermined game operation can be transmitted to each of the control boards 40, 42, 43, 46 by one-way communication. By adopting the one-way communication of the control command, it is possible to surely prevent impropriety and to use the main control board 3
9 can be significantly reduced, and transmission control can be simplified.

The main control board 39 is provided with an ordinary winning port 19 via a relay board (not shown) (circuit board for relaying signals).
And game board information such as a start winning port 17 and a switch signal from the gate 20 are supplied. On the other hand, the payout control board 46
Are supplied via a relay board 50 with signals of a ball lending counting switch, a prize ball counting switch, a lower tray switch, and a replenishment detection switch. Among them, the signal of the prize ball counting switch is also supplied to the main control board 39 via the relay board 50. Note that the payout control board 46 drives the payout motor M of the game ball via the relay board 50.

FIG. 6 shows a payout cassette C for paying out game balls.
FIG. 5 is an exploded perspective view of A, specifically illustrating the payout means 35 shown in FIG. 4. As shown in the figure, the payout cassette CA (payout means 35) includes a payout motor M, a payout rotating body 51 rotated by the payout motor M, and a switching blade 52 that is switched according to whether the ball is in the ball lending state or the winning ball state.
And left and right ball lending counting switches 53a and 53b, left and right prize ball counting switches 54a and 54b, and the like. The game balls that have moved on the left and right guide paths 55a and 55b are captured by the left and right holding portions H of the payout rotating body 51, and are led out to the upper plate 8 according to the rotation of the payout rotating body 51.

FIG. 7 shows a state in which the switching blade 52 is positioned on the prize ball side. The number of prize balls is counted by the prize ball counting switch 54. In addition, the taxiway 5 on the left and right
The game balls 5a and 55b are derived in accordance with the rotation of the payout rotator 51, and the counting switch 5 is normally operated within 100 ms.
Pass position 4. The passing of the game balls is counted by the left and right counting switches 54a and 54b, respectively, and thereafter, when the prize ball operation is completed, the state of FIG.
The state shifts to the state of (b). The ball lending operation is the same, and the ball lending count switch 53 counts the number of lending balls in a state where the switching blade 52 is located on the lending side as shown in FIG. The game balls on the left and right taxiways 55a and 55b are respectively set to the left and right counting switches 53a and 53b.
Counted by. Thereafter, when the ball lending operation is completed, the state shifts from the state of FIG. 8A to the state of FIG. 8B.

The control boards 39, 40, 42, 5 shown in FIG.
Since all of the circuits 3 and 46 have substantially the same circuit configuration, the main control board 39 will be representatively described. FIG. 9 is a block diagram showing a circuit configuration of the main control board 39. As shown in the figure, the main control board 39 is a C
A PU circuit 60, a system clock generator 61 for generating a clock signal having a frequency that is an integral multiple of the system clock CK supplied to the CPU, and a decode circuit 62 for generating a chip select signal for each unit based on an address signal from the CPU. An output port circuit 63 for outputting data from the CPU, an input port circuit 64 for taking in external data by the CPU, an output drive circuit 65 for outputting commands and the like to each control board, Switch input circuit 66 for inputting ON / OFF state of switches
And it is mainly composed.

The one-chip microcomputer 60 is, specifically,
CPU equivalent to Z80 (Zilog) and ROM (Read Onl)
y Memory), a RAM (Random Access Memory), a counter section, and the like. FIG. 10 (a)
5 illustrates a specific configuration of the counter unit built in the one-chip microcomputer 60. As shown in FIG. 10A, the counter unit of the one-chip microcomputer 60 receives the clock pulse Φ having the pulse period τ and decrements (−
1) Down counter 70 that operates and down counter 7
An initial value register 71 holding a preset value N of 0,
When the count value DW (8-bit length) of the down counter reaches zero, an interrupt control unit 72 that outputs an interrupt signal INT to the CPU, an interface unit 73 that is a relay unit with the CPU, and the like are provided.

In this embodiment, the preset value N is 12
5 and the pulse period τ of the clock pulse Φ is 16
μS is set. Therefore, the down counter 70
T = τ × N = 16 × 125 μS = 2 mS from the start of operation
After elapse, the counter value DW of the down counter 70 becomes zero, and a timer interrupt is applied to the CPU inside the one-chip microcomputer. In this embodiment, the game control operation is executed intermittently every T (= 2 mS) using the interrupt signal INT (Maskable Interrupt). After the value of the down counter 70 becomes zero, the preset value N (= 125) is reset and the countdown operation is continued.

As shown, the down counter 70 and the CPU
Is connected via the interface unit 73, so that the CPU can read the count value DW of the down counter 70 by an IN instruction or an LD instruction as necessary. Therefore, even after the CPU is in the interrupt disabled state, the CPU can manage the time by grasping the value of the down counter 70. That is, since the pulse period τ of the clock pulse Φ is 16 μS, it is possible to grasp that the time of M × τ has elapsed from the transition amount (decrease number M) of the count value DW of the down counter 70 read by the CPU. The time can be managed without providing a hardware timer.

For example, when it is desired to repeat the processing of the processing time P (indicated by a shaded square in FIG. 10) at regular time intervals (T), the CPU constantly monitors the counter value DW of the down counter 70, What is necessary is just to wait for the count value DW to reach the specific value n1, and start the process when the counter value DW reaches n1. FIG. 10B illustrates this state. Even when the interrupt signal reception is prohibited,
The CPU starts the processing for the processing time P at the timing when the count value DW becomes n1, so that the certain time T (= 2
mS) can be executed. n1
Is an arbitrary integer equal to or less than N, but when n1 = 1,
The processing can be started at substantially the same timing as the interrupt processing by the interrupt signal INT. Note that N × τ = T
, But the processing time P of the processing repeated at a constant interval T
Must satisfy the relationship of (N−n1) × τ> P−n1 × τ, and specifically, P <N × τ.

FIG. 11 exemplifies the contents of an interrupt processing program executed by the main control board 39 in response to an NMI interrupt, and is executed when the power supply voltage drops due to a power failure or the like. Note that a detection circuit for detecting a power supply abnormality is provided on the power supply board 45,
The MI signal is transmitted to the CPU of each control board. The interrupt of NMI (Non Maskable Interrupt)
Since this is the highest priority interrupt, CPU (INT
kable Interrupt), the process of FIG. 11 is started, and the CPU thereafter executes INT (Maskable Interrupt).
(Interrupt) signal is not accepted.

In the interrupt processing of the NMI, first, the contents of each register (AF, I, BC, DE, HL) are pushed to the stack area (ST20). However, since the value of the I register cannot be directly PUSHed to the stack area, after the instruction of LDA, I is executed, the PUSH is executed.
Executing the AF instruction performs the operation.

Next, PUSH in step ST20
The value of the stack pointer SP after execution of the instruction is the SP of the RAM.
It is stored in the storage area (ST21). In a predetermined area of the RAM including the SP storage area, data is retained even after the power supply is stopped by supplying a backup power supply such as a battery. While the game is in progress, various data are temporarily stored in a work area (work area) of the RAM.
Those data are also held by the backup power supply.

Subsequently, the CPU substitutes 105 for a variable NT (ST22). This process is for repeatedly detecting the state of the prize ball counting switch for a certain period of time (specifically, 210 mS) since the occasion of the NMI interruption happens to be during the payout of the prize ball. When the initialization of the variable NT is completed, the CPU obtains the count value DW of the down counter 70 from the counter unit inside the one-chip microcomputer (ST23). Then, it waits until the count value DW reaches a predetermined value (1 in this example) (ST24, ST2).
3).

As described above, the down counter 70
Is 125 → 124 →... Every pulse period τ = 16 μS.
→ 1 → (0 → 125) →... In this embodiment, in order to start the switch input processing (ST25) at the timing of the counter value DW = 1, step ST25 is performed.
23 and ST24 are provided. Thereafter, when the counter value DW becomes 1, the CPU acquires the signals of the right and left prize ball switches 54a and 54b, and stores necessary data in a corresponding area of the RAM based on the grasped number of prize balls (ST25). . It goes without saying that this stored data is backed up even during a power failure.

Thereafter, the variable NT is decremented (ST
26) Until NT = 0, steps ST23 to ST23
27 is repeated. As described above, the process of step ST25 is performed by counting the counter value D of the down counter 70.
The timing starts when W reaches 1 and the timing when the counter value DW reaches 1 is a fixed time T (= 2 m
S) (see FIG. 10B). for that reason,
Although the CPU is in the interrupt disabled state, the switch input process can be executed at the same interval T (= 2 mS) as the interrupt process (FIG. 13) described later.

The switch input process (ST25) is 1
The processing is repeated 05 times, and the processing shifts to the next processing after 105 × 2 mS = 210 mS. However, since the game balls passing at 100 mS are monitored over 210 mS, the missed reading of the number of award balls is prevented. This point will be specifically described with reference to FIGS. The NMI interrupt causes the main control board 39
Then, the processing of FIG. 11 is started, and the same processing is started in the payout control board 46, so that the payout rotating body 51 stops operating.

For example, the payout rotating body 51 stops in the state of FIG. 7 (a), and the sent game balls are in a state of FIG. 7 (b) after a predetermined time has passed from the state of FIG. 7 (a). Move to When the NMI process is started, the switch process synchronized with the INT interrupt cannot be performed.
In the present embodiment, the switch input process is repeated for a predetermined time (= 210 ms) in synchronization with the value DW of the down counter, so that there is no possibility that several prize balls shown in FIG.

After the number of prize balls being paid out is accurately grasped as described above, the flag value 5AH is stored in the RAM area of the backup flag BFL (ST28).
The access to the AM is inhibited and the CPU waits for the power supply voltage to drop and the CPU to become inactive (ST29). After that, CP
U goes into a non-operating state, but since backup power is supplied to the RAM, the backed up data is kept stored as it is.

The NMI interrupt processing program in the main control board 39 has been described above. In the case of the payout control board 46, the value of the ball lending counting switch is also managed in addition to the prize ball coefficient switch. The processing content in response to the NMI interrupt is the same as that of FIG. 11, and the movement of the game ball is monitored for a time of 210 mS. Therefore, even if a power failure occurs during lending of a ball or a prize ball, counting of the game ball is performed. There is no mistake.

FIG. 12 is a flowchart showing a main routine of a game control program executed by the main control board 39. In the main routine, first, the CPU sets itself to the interrupt disabled state (DI) and initializes each part of the one-chip microcomputer 60 including the CPU (ST).
1). When the power is turned on, there are two patterns. One is when the power is turned on when the initialization switch 85 is turned off, and the other is when the pachinko hall is opened. Thus, the power may be turned on when the initialization switch 85 is turned on.

Thereafter, the CPU determines the value of the RAM clear signal (ST2). The RAM clear signal is a signal indicating whether or not the RAM area is to be initialized, and has a value corresponding to the ON / OFF state of the initialization switch 85. Now, assuming that the pachinko hall is opened and the power is turned on with the initialization switch 85 turned on,
The determination in step ST2 becomes Yes, the work area of the RAM is initialized, and the other RAM areas are cleared to zero (ST4). Then, the CPU is set to the interrupt permission state (EI) (ST4), and thereafter, the random number generation processing is performed in an infinite loop (ST5). Note that the process of step ST5 is a process for determining what kind of off-game to produce when the game is in a missed state due to a determination such as a big hit determination process described later.

On the other hand, when the initialization switch 85 is in the OFF state as in the case of recovery from the power failure state, the backup flag BFL follows the determination in step ST2.
Is determined (ST3). Backup flag B
FL is data indicating whether the backup data at the time of the interruption operation saved in the NMI process is restored to the original state, and in this embodiment, the backup flag BFL is set to 5AH in the process of step ST28. And is cleared to zero in the process of step ST10.

Now, assuming a time of recovery from a power failure state,
The content of the backup flag BFL is 5AH. Therefore, the processing of the CPU is performed from step ST3 to step S3.
The process proceeds to T6, where the 16-bit data read from the SP storage area of the RAM is written to the stack pointer SP of the CPU (ST6).

Next, the data held by the backup power supply is read, and processing for restoring the interrupted command is performed (ST7). Here, the command is a command transmitted from the main control board to each control board, and is used to excite the game by an image or sound or to pay out a prize ball. To create the required commands. Next, the CPU executes a POP instruction to execute each register (BC, D) excluding the AF register from the stack area.
E, HL) is restored (ST8). When this process is completed, the data in the SP storage area is cleared to zero (ST9).

As a result of the above processing, the recovery processing from the time of the power failure is temporarily completed, so that the backup flag BFL is cleared to zero to indicate that (ST10). In this embodiment, although the return of the AF register is not completed, the SP
The data in the storage area is cleared to zero and the backup flag BFL is cleared to zero in ST9 and ST10.
This is because the A register must be used in the processing of (1), and if the processing of ST9 or ST10 is postponed, the data of the A register that has been restored will be destroyed.

Therefore, in this embodiment, the I flag and the AF register are restored after the backup flag BFL is cleared to zero. Specifically, first, P
The OPAF instruction is executed to restore the contents of the I register to the F register (ST11). In the NMI interrupt processing program, after loading the value of the I register into the A register, the value of the A register is pushed, so that the P / V flag of the F register is
The value of the interrupt permission flip-flop IFF inside the PU is stored.

Here, when the P / V flag is 1, NM
The CPU at the time of the I processing is in the interrupt enabled state. Conversely, when the P / V flag is 0, the CPU at the time of the NMI processing is in the interrupt disabled state. Therefore,
If the P / V flag is 0, the POP instruction is executed again to restore the value of the AF register, and the RET instruction is executed in the interrupt disabled state (ST13, ST14). On the other hand, if the P / V flag is 1, the POP instruction is executed again to restore the value of the AF register, the state is changed to the interrupt enabled state, and the RET instruction is executed (ST15 to ST17). Whatever it is,
By executing the RET instruction, the value of the PC (program counter) at the time of the interruption that has been subjected to the PUSH processing in the stack area is restored, and the processing that has been interrupted due to a power failure or the like is resumed.

FIG. 13 is a flowchart showing the contents of an interrupt processing program of a timer interrupt INT (maskable interrupt prohibition interrupt) generated every 2 ms during the infinite loop processing (ST5) of the main routine (FIG. 12). When a timer interrupt occurs, the contents of each register are saved in the stack area, and random number creation processing, switch input management processing, error management processing, and the like are performed (ST30). The switch input management process is for determining whether or not a game ball has passed through a gate, an electric tulip, or the like, and the error management process is for determining whether or not an abnormality has occurred inside the device.
Further, the random number generation process means a process of acquiring a hit random number value or a jackpot random number value updated in hardware.

Thereafter, the value of the processing division counter is determined, and the corresponding processing of ST32 to ST36 is performed. The above-described error management and switch management should be repeated at short time intervals, while processing related to the production of pachinko games is complicated and sophisticated according to the needs of the player, and requires a certain amount of processing time. Will be. Therefore, in this embodiment, all the game control operations are set to 1
Instead of being completed in one interrupt process, the process is divided into five types of processes, and each of the divided processes is shared and executed for each interrupt. Therefore, a processing division counter that circulates in the range of 0 to 4 is provided, and processing according to the value of the processing division counter is performed.

More specifically, when the processing division counter is 0, processing relating to the opening of the special winning opening is performed (ST32), and when the processing division counter is 1, the hit state (opening of the electric tulip) is determined. Ordinary symbol processing regarding whether or not the processing is performed (ST33), and when the processing division counter is 2, processing regarding whether or not the state is a big hit state is performed (ST33).
34). If the processing division counter is 3, a timer management process related to the opening / closing timing of the electric tulip and the winning port, and a command creation process transmitted from the main control board to each control board are performed (ST35). If the processing division counter is 4, information output and error display command creation processing are performed (ST36).

When any one of steps ST32 to ST36 is completed, the value of the processing division counter is updated (ST37), and the generated command is transmitted to each control board (ST38). Further, the value of each register is restored, and at the same time, the state is changed to the interrupt enabled state, and the process returns from the interrupt processing routine to the main routine (ST39).

Although the embodiment of the present invention has been described above, the specific technical contents do not particularly limit the present invention. That is, in the embodiment, the CPU is Z80CPU
Although a specific description has been given on the premise that it is a substantial product, it is obvious that other CPUs may be used. Also, the specific configuration of the counter section is not particularly limited to the present invention, and it goes without saying that an up counter may be used instead of the down counter.

[0056]

As described above, according to the present invention,
Even without adding another circuit element, even if the CPU is in the interrupt disabled state, it is possible to realize a gaming machine capable of managing the same timing as before.

[Brief description of the drawings]

FIG. 1 is a perspective view of a pachinko machine according to an embodiment.

FIG. 2 is a side view of the pachinko machine of FIG.

FIG. 3 is a front view of the pachinko machine of FIG.

FIG. 4 is a rear view of the pachinko machine shown in FIG. 1;

FIG. 5 is a circuit block diagram of the pachinko machine of FIG. 1;

FIG. 6 shows a specific example of a payout cassette CA (payout means).

FIG. 7 illustrates a prize ball operation.

FIG. 8 illustrates a ball lending operation.

FIG. 9 is a block diagram illustrating a circuit configuration of a main control board.

FIG. 10 is a block diagram showing a circuit configuration of a timer unit in the one-chip microcomputer.

FIG. 11 is a flowchart of an NMI interrupt processing program executed at the time of a power failure or the like.

FIG. 12 is a flowchart of a main routine of a game control program according to the embodiment.

FIG. 13 is a flowchart of an INT interrupt processing program for a timer interrupt.

FIG. 14 is a flowchart illustrating the operation of the conventional device.

[Explanation of symbols]

 2 Ball game machine (pachinko machine) 46 Payout control board 39 Main control board 70 Counter (down counter) ST20-29 Backup means (NMI processing) DW counter count value CA Payout device (payout cassette)

Claims (9)

[Claims] 1. A payout control board that controls a payout device that pays out game balls to a player, a main control board that mainly controls a game operation, and a power supply voltage supplied to the payout control board and the main control board. Power supply monitoring means for monitoring the power supply monitoring means, and backup means for storing information necessary for resuming the game operation by interrupting the game operation on condition that the power supply monitoring means detects an abnormal state, the main control board And / or the payout control board includes a memory storing a game control program, a CPU operating based on the control program,
The main control board and / or the dispensing control board acquire a count value of the counter when the backup means operates, and based on the acquired value. A ball game machine characterized by performing a detection operation of passing a game ball. 2. In the main control board and / or the payout control board, during game operation, detection of passage of a game ball in response to an interrupt signal generated from the counter each time the count value reaches a predetermined value. The ball game machine according to claim 1, wherein the ball game machine performs an operation. 3. In the main control board and / or the payout control board, when the backup means operates, the value reaches a predetermined value while acquiring the count value before or after the detecting operation of the passing of the game ball. The ball game machine according to claim 1 or 2, wherein a process of waiting for a game is executed. 4. The power supply monitoring means is provided on a separately provided power supply board, and the main control board and / or the dispensing control board is provided with the backup means. The ball-and-ball game machine described in 1. 5. When the power supply monitoring unit detects an abnormal state, the power supply monitoring unit detects a CP of the main control board and / or the payout control board.
The ball game machine according to any one of claims 1 to 4, wherein a highest priority interrupt signal is supplied to U. 6. The system according to claim 1, wherein the main control board determines the number of winning balls based on game ball passage detected when the backup unit operates. Ball game machine. 7. The payout control board according to claim 1, wherein the number of winning balls and / or the number of balls lent is determined based on the passing of the game balls detected when the backup means operates. The ball game machine according to any one of the above. 8. The ball game machine according to claim 1, wherein the memory, the CPU, and the counter are integrated with a single electronic component. 9. The ball game machine according to claim 1, wherein the backup means completes the operation after detecting a predetermined number of times of passage of the game ball. .