JP2002224400A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an improved game machine regenerating an original game, if there are fluctuations in a power voltage and other electric troubles, in restarting the interrupted game actions. SOLUTION: This pachinko machine is so constituted that, while realizing the game action according to a control program stored in the device inside, when it is not processed normally according to the control program, a watch dog timer WDT functions to forcedly return the game action to the initial state. This machine is also provided with a clear processing ST 37 obstructing the functioning of the watch dog timer WDT by outputting the clear signals at intervals within a prescribed time and a system reset circuit 52 outputting an initial signal PS in inputting a power supply and delaying the timing of functioning of the watch dog timer WDT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko machine, an arrangement ball machine, a sparrow ball game machine, a spinning-type game machine and the like. Relates to a gaming machine improved so that the original gaming operation can be normally resumed.

[0002]

2. Description of the Related Art A gaming machine with a built-in personal computer, such as a pachinko machine, cannot continue normal operation when a power supply voltage falls below a predetermined value. Therefore, a gaming machine with a built-in personal computer needs to be devised so as not to be affected by a power failure caused by a lightning strike or the like.

[0003] Here, there can be a countermeasure such as providing each pachinko hall with an in-house power generation device. However, since the power consumption of the pachinko machines is not small and the number of pachinko machines is large, such countermeasures are cost-effective. It is not realistic in space.

[0004] Therefore, as a general countermeasure against power failure, necessary data is stored in a RAM area by NMI processing, backup power is supplied to the RAM area to maintain the contents, and backup is performed when commercial power is restored. The read data is read to reproduce the game operation before the power failure.

[0005]

However, since troubles such as a power failure occur suddenly, for example, if the pachinko machine was in a big hit state before the power failure, there is no problem after the power is restored. The big hit game needs to be reproduced, otherwise an unnecessary trouble occurs with the player. Also, even if it is not a power failure state, unexpected abnormalities may occur in the power line,
For example, even if the power supply line fluctuates in an unstable state, it is desired to perform an appropriate operation.

The present invention has been made on the basis of such a request. When the interrupted game operation is restarted, the power supply voltage may fluctuate and other electric troubles may be minimized even if there is any problem. It is another object of the present invention to provide a gaming machine improved so that an original game is reproduced.

[0007]

In order to solve the above-mentioned problems, the present invention realizes a game operation in accordance with a control program stored in the device, while preventing normal processing in accordance with the control program. If
A gaming machine in which reset means WDT functions to forcibly return a game operation to an initial state, and outputs a clear signal within an interval of a predetermined time, thereby preventing the reset means WDT from functioning. Clear processing,
A clear circuit 5 which outputs an initial signal PS at power-on and delays the timing at which the reset means functions.
2 is provided. Here, the control program typically includes a main control board that mainly controls game operations, and / or
Alternatively, it is provided on a payout control board that pays out game media based on a command from the main control board.

In the present invention, since the clear circuit is provided in addition to the clear processing, when the interrupted game operation is restarted, even if there is a fluctuation in the power supply voltage or other electrical trouble, There is no trouble that the reset means WDT functions and the game operation is initialized. In addition,
In the embodiment, the system reset circuit corresponds to the clear circuit of the present invention.

Typically, even when the power supply voltage at the time of power-on changes, the clear circuit 52 repeatedly outputs the initial signal PS in response to the change. Further, the initial signal PS is generated based on a power reset signal SYSRST. Here, the power supply reset signal means a pulse signal generated in response to the power supply voltage rising to a normal value.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described based on a card-type ball game machine which is one embodiment of the present invention. FIG. 1 is a perspective view showing the pachinko machine 2 of the present embodiment, and FIG. 2 is a side view of the pachinko machine 2.

A pachinko machine 2 shown in FIG. 1 includes a rectangular wooden frame 3 detachably mounted on an island structure, and an outer frame 3.
And a front frame 4 that is pivotally attached to be openable and closable via a hinge H fixed to the front frame 4. In addition, this pachinko machine 2
A plurality of pachinko parlors are arranged in the length direction of the island structure while being electrically connected to the card-type ball lending machine 1.

A game board 5 is detachably mounted on the front frame 4 pivotally attached to the outer frame 3 via the hinge H from the back side, and a glass door having a window corresponding to the front side of the game board 5. The front panel 6 and the front panel 7 are pivotally connected to each other so as to be freely opened and closed. An upper plate 8 for storing game balls for firing is attached to the front plate 7, and a front frame 4 is provided.
The lower part 9 is provided with a lower plate 9 for storing game balls overflowing or withdrawn from the upper plate 8 and a firing handle 11 of a firing means 10.

The firing means 10 includes a firing handle 11 that can be rotated and a firing motor that fires a game ball with a hitting hammer 12 (FIG. 4) with a hitting force corresponding to the turning angle of the firing handle 11. Have. On the right side of the upper plate 8,
An operation panel 13 for ball lending operation for the card-type ball lending machine 1 is provided. The operation panel 13 has a card balance display section 13a for displaying the card balance with three digits, and a game ball for a predetermined amount. Ball lending switch 1 for ball lending
3b and a return switch 13c for instructing a return of the card at the end of the game.

As shown in FIG. 3, the game board 5 is provided with a substantially annular guide rail 15 composed of metal outer rails and inner rails. Color liquid crystal display 16, symbol starting means (symbol starting and winning means) 17, opening and closing winning means (large winning means) 18, a plurality of normal winning means 19 (open and closed winning means 18 in addition to the normal winning means 19 in the upper stage) 6) normal winning means 19) on the left and right sides of the two gates 20
(Passing ports) are respectively provided at predetermined positions.

The liquid crystal display 16 functions as first symbol display means 22 for displaying a variable symbol and displaying a background image, moving images of various characters, and the like. The first symbol display means 22 displays a background image and a character in an animated manner, and displays three (left,
(Medium, right) symbol display sections 22a to 22c, and on the condition that a game ball wins in the symbol starting means 17, the display symbols of the symbol display sections 22a to 22c fluctuate for a predetermined time (scroll display). Then, the game stops in the stop symbol pattern determined based on the lottery result according to the timing of winning the game ball to the symbol starting means 17.

Immediately above the liquid crystal display 16, ordinary winning means 19 and second symbol display means 23 are provided. The second symbol display means 23 has an ordinary symbol display unit for displaying one ordinary symbol, and when a game ball passing through the gate 20 is detected, the symbol displayed on the ordinary symbol display unit fluctuates for a predetermined time, When the game ball passes through the gate 20, a stop symbol determined by the random number for the lottery selected by the lottery is displayed and stopped. The symbol starting means 17 is an electric tulip having a pair of left and right opening and closing claws 17a that can be freely opened and closed. It is opened only for a predetermined time and it becomes easy to win a prize.

The open / close prize means 18 has an open / close plate 18a which can be opened forward, and when the stop symbol after the change of the first symbol display means 22 is a hit symbol such as "777", a "big hit" is reached.
Is started, and the open / close plate 18a is opened to the front side. The specific area 1 is provided inside the opening / closing prize means 18.
8b, and when the winning ball passes through the specific area 18b, the special game is continued. Here, the special game state corresponds to a state advantageous to the player.

After the opening / closing plate 18a of the opening / closing type winning means 18 is opened, a predetermined time elapses or a predetermined number (for example, 10
) Game balls win and the open / close plate 18a closes,
If the game ball does not pass through the specific area 18b, the special game is terminated, but if the game ball passes through the specific area 18b, the special game is continued up to, for example, 16 times at maximum, and is controlled in a state advantageous to the player. Is done.

As shown in FIG. 4, on the back side of the front frame 4, a back mechanism plate 30 for holding the game board 5 from the back side is detachably mounted. The back mechanism plate 30 has an opening 30a formed therein. A prize ball tank 33 and a tank rail 34 extending from the prize ball tank 33 are provided on the upper side thereof. Dispensing means 35 connected to the tank rail 34 is provided on a side portion of the back mechanism plate 30, and is provided below the back mechanism plate 30. Is provided with a passage unit 36 connected to the dispensing means 35. Dispensing means 35
Are paid out to the upper plate 8 from the upper plate discharge port 8a (FIG. 1) via the passage unit 36.

In the opening 30a of the back mechanism plate 30, a back cover 37 mounted on the back side of the game board 5 and prize means 17 to
A prize ball discharge gutter (not shown) for discharging the game ball that has won the prize 19 is fitted respectively. A main control board 39 is disposed inside a case 38 attached to the back cover 37,
A symbol control board 40 is provided on the front side (FIG. 2). Below the main control board 39, a lamp control board 42 is provided inside a case 41a attached to the back cover 37, and a sound control board 43 is provided inside a case 41b adjacent to the case 41a.

A power supply board 45 and a payout control board 46 are provided inside the case 44 mounted on the back mechanism plate 30 below the cases 41a and 41b. As shown in FIG. 3, a power switch 8
0 and an initialization switch 85 are arranged. The case 44 is cut off at the portions corresponding to the switches 80 and 85, and each of the switches 80 and 85 can be simultaneously operated by a finger.

A firing control board 48 is provided inside a case 47 mounted on the rear side of the firing means 10. These control boards 39-40, 42-43, 45-4
6, 48 are independent boards, and control boards 39, 40, 42, 43, excluding the power supply board 45 and the emission control board 48.
46 has a one-chip microcomputer LE2080A (LE
The main control board 39 and the other control boards 40, 42, 4
3 and 46 are electrically connected via a connector by a plurality of signal lines. The one-chip microcomputer LE2080A used in this embodiment is a Z80 (Zilog
And a built-in CPU, ROM, RAM and other ICs.

The main control board 39 and other control boards 40,
42, 43, and 46 are electrically connected to each other through a plurality of signal lines via connectors, and are used to cause the control boards 40, 42, 43, and 46 to execute predetermined game operations from the main control board 39. Control commands can be transmitted by one-way communication. By adopting the one-way communication of the control command, it is possible to reliably prevent the improper operation related to the symbol stop, to remarkably reduce the control load on the main control board 39, and to simplify the transmission control.

FIG. 5 shows the main control board 39 of the Z80C
FIG. 2 illustrates a circuit example of a reset signal generation unit for putting a PU into a reset state. From this circuit, a user reset signal URST and a system reset signal RST are output. For both signals, the value of the program counter PC is forced to 0000H by setting the reset terminal of the Z80 CPU to the L level for a predetermined time. To return the program processing to the initial state.

As shown in FIG. 5, the reset signal generating section includes a watchdog timer circuit 51 which operates in response to a timer clear signal from the CPU, and a ripple counter RB.
C (for example, TC74HC4020AF) and a system reset circuit 52 including a D-type flip-flop D-FF (for example, HD74HC74). The system reset circuit 52 is supplied with a reset signal SYSRST from a power supply reset circuit (not shown) and a system clock XTAL, and outputs a system reset signal RST and an initial signal PS.

Here, the reset signal SYSRST from the power reset circuit includes two Schmitt triggers G2, G
3, the pulse width is widened by the delay circuit DL including the capacitor and the resistor, and the CPU of the main circuit board 39 is reset slightly later than the CPUs of the other control boards 40, 42, 43, and 46. I have. This operation allows the control boards 40, 4 to operate in an operation such as when power is restored.
There is no risk of the commands 2, 43, 46 dropping commands from the main control board 39.

The watchdog timer circuit 51 has a dedicated I
C barrel watchdog timer WDT (TA8030S)
Is used. In a self-running state in which a pulse signal is not input to the clock terminal WD, the watchdog timer WDT changes the voltage of the TC terminal to 2 V and 4 V after turning on the power to the IC.
The charge / discharge is repeated between V and V, and a reset signal RS having an H level period _TWD of 1.1 × C1 × R1 (ms) and an L level period _TRST of 0.75 × C1 (ms) is output from the RST terminal.
T is output (hereinafter, T _WD + T _RST is referred to as a timer reset period T ₀ ). On the other hand, when a positive pulse is applied to the clock terminal WD, the charge is discharged even during charging toward 4V, and the charging operation is started again from 2V.

Therefore, in this pachinko machine, the RST terminal is constantly set at the H level by applying the timer clear signal to the clock terminal WD of the watchdog timer WDT by software every predetermined time T _CLR shorter than the timer reset period T _0. To be maintained. When the pachinko machine is operating normally, a timer clear signal is added to the watchdog timer circuit 51 every predetermined time T _CLR , so that the CPU is not reset. In this situation, the reset signal RST of the watchdog timer WDT automatically falls after a predetermined time, and the Z80 CPU receiving the user reset signal URST is forcibly reset. In other words, the game operation is forcibly returned to the initial state.

As shown in FIG. 5, the watchdog timer W
The initial signal PS from the system reset circuit 52 is supplied to the clock terminal WD of the DT via the OR gate G1.
(Inverted RST signal) is also added. However, the supply of the initial signal PS is for eliminating the influence of chattering or the like at the time of turning on the power. In the steady state, the H-level initial signal PS is applied to the OR gate G1. Does not affect the operation of. The operation at power-on is also one of the features of the present embodiment, and will be described in detail below.

FIG. 6 is a time chart for explaining the operation of the system reset circuit 52 shown in FIG. When the power is turned on (t1), a signal SYSRST from a power reset circuit (not shown) rises as shown in FIG. Then, correspondingly, the ripple counter RB
The clear terminal CLR of C goes high, and all outputs of the RBC, including Q8 and Q9, go low. The signal SY
Since the clear terminal CLR of the D-type flip-flop D-FF falls in response to the rise (t1) of SRST, the Q output of the D-FF goes to L level (FIG. 6 (d)).

Thereafter, at the timing of t2, the signal SYSRST from the power reset circuit falls as shown in FIG. Then, the clear terminal CLR of the ripple counter RBC also goes to the L level, and the ripple counter RBC starts counting the system clock XTAL. Further, the CLR terminal of the D-FF goes to the H level in response to the fall of the signal SYSRST (t2). Thereafter, when a signal is supplied to the clock terminal CK of the D-type flip-flop D-FF, the H level becomes high. A level D input will appear at the Q output terminal.

After a predetermined time, as a result of the counting operation of the ripple counter RBC, the Q8 output of the RBC becomes H level (t3). Then, correspondingly, system reset signal RST attains H level as shown in FIG. 6 (g).
Note that, from t2 to t3, which is determined by the number of count stages of the ripple counter RBC, the Z80 CPU can be properly reset by the L level of the system reset signal RST.

The operation after that will be described. The output Q8 of the ripple counter RBC eventually goes low, and the output Q9 of the RBC goes high accordingly (t)
4). Then, the Q output of the D-FF goes high in response to the rising edge of the Q9 output of the ripple counter RBC. Then, the clear terminal CL of the ripple counter RBC
When R becomes H level, all outputs of the ripple counter RBC thereafter are maintained at L level.

FIG. 7 is a time chart for explaining the relationship between the system reset signal RST generated as described above and the operation of the watchdog timer circuit 51.
FIG. 7A shows an exceptional case where the reset signal SYSRST from the power reset circuit fluctuates in a short time due to chattering or other reasons at the time of power restoration. The CPU issues a system reset signal RST
Is reset to the section τ where L is at the L level, but there is a possibility that the CPU is reset even during the unstable period before that. However, since the processing of the one-chip microcomputer is restarted from the beginning at timing t3, the waveform of the system reset signal RST during the unstable period is not shown in FIG.

In FIG. 7, a system reset signal RS
The fact that T changes as shown in the figure is as described above for the system reset circuit 52. Therefore, in FIG. 7, at time t1 'when the power of the pachinko machine is turned on.
Hereinafter, the operation of the watchdog timer circuit 51 will be described. FIG. 7 shows a reset signal SYSRST (not shown) from a power reset circuit (not shown).
(A)), the system reset signal RST applied to the one-chip microcomputer (FIG. 7 (b)), the operation of the CPU, FIG.
(D) is an initial signal PS applied to the OR gate G1.
(FIG. 7 (c)), a timer clear signal supplied from the CPU as software (FIG. 7 (e)), a differential capacitor C
2 (FIG. 7 (f)), WDT reset output R
ST1 (FIG. 7 (g)) and a user reset signal URST (FIG. 7 (h)) applied to the one-chip microcomputer.

In the operation contents of the CPU shown in FIG. 7C, the security check means that the CPU checks the contents of the memory including the program area when starting the game control operation, and the program is not illegally modified. It is a work to confirm. In a gaming machine, the security check operation is important because there is a possibility that the game machine may be tampered with after the shipment from the maker, and a considerable amount of processing time is required because all memory areas are checked. In addition, the return processing described in FIG.
If the game is interrupted due to a power failure or the like, this is a process for restarting the interrupted game, which is executed when the power is restored. When the pachinko hall is opened, the power supply is turned on, the security check time is passed, and the process shifts to the original process. In the case of a power failure, for example, the return process time is further required.

The watchdog timer circuit 51 will be described based on the above description. The watchdog timer WDT (TA8030S) of the embodiment receives the power supply voltage, resets the reset terminal RST after 0.5 × C1 × R1 (ms). Is set to the H level, and thereafter, if it is in a self-running state, it operates so that the voltage of the reset terminal RST falls after the time of _TWD . On the other hand, as described above, WD
When the terminal receives a positive pulse, the capacitor C1
Is discharged, the output of the reset terminal RST remains at the H level, and is maintained only for _TWD .

In this embodiment, the watchdog timer W
The WD terminal of DT is ORed through the differentiation capacitor C2.
Since the output of the gate G1 is also applied, a positive level differential pulse is applied to the voltage of the WD terminal at the timing of t2 as shown in FIG. 7 (f). Therefore, no matter how long the period from the power-on t1 'to t2 when the normal reset signal is supplied to the CPU (however the unstable period is long), the reset is performed from the time t2 until _TWD elapses. Terminal R
There is no possibility that ST falls to the L level. Therefore,
According to the present embodiment, regardless of the length of the unstable period, CP
There is no possibility that U is reset by the operation of the watchdog timer WDT.

FIG. 8 shows a comparative example of this embodiment. FIG. 8C shows a circuit of a related circuit for supplying only a timer clear signal to the watchdog timer WDT without providing the OR gate G1. FIGS. 8A and 8B are time charts for explaining the operation of this circuit. FIG.
As in (a), when there is no unstable period normal, earlier than the time T _WD until the fall of the reset signal RST of the watchdog timer WDT, there is no trouble because the timer clear signal from the CPU is output.

[0040] In other words, than the maximum time T _MAX from the CPU reset to the CPU outputs the timer clear signal, because the people of T _WD watchdog timer WDT is large (T
_MAX < _TWD ) No problem occurs. However, when there is an unstable period as shown in FIG. 8B, the output timing of the timer clear signal is delayed by the delay of the reset of the CPU. The reset signal RST falls, and the restoration process cannot be normally continued. On the other hand, in the circuit of this embodiment, as described above, before the CPU is reset, the charge of the capacitor C1 is discharged at the timing of t2 in FIG.
The trouble as shown in FIG. 8B does not occur.

FIG. 9 is a flowchart showing a main routine of a game control program executed by the main control board 39. When the power is turned on, the operation of the system reset circuit 52 shown in FIG.
A reset signal is applied to the CPU core (equivalent to Z80) of the E2080A, and the processing shown in FIG. 7 is started.

The main routine is executed only when the security check (ST1) is completed normally. First, the Z80 CPU sets itself to the interrupt disabled state (DI) and sets the one-chip microcomputer including the Z80 CPU core. Are initialized (ST2). When the power is turned on, there are two patterns. As in the case of recovery from a power failure, the initialization switch 85 is turned off.
There are cases where the power is turned on in the F state and cases where the power is turned on when the initialization switch 85 is on, such as when a pachinko hall is opened. In any case, the processing of step ST2 is executed. Is done.

Next, the CPU is set to the interrupt mode 2 (ST2). Note that the interrupt mode 2 is defined as Z80-3.
This is the most powerful interrupt mode among the two interrupt modes (modes 0, 1, and 2). One byte data stored in the I register inside the CPU and the interrupt vector (1 Byte) in combination with a maximum of 128 interrupt processing routines.

After the setting of the interrupt mode 2, the CPU
Determines the value of the RAM clear signal (ST3). RA
The M clear signal is a signal indicating whether or not to set an initial value in the RAM area.
It has a value corresponding to the state. Now, assuming that the pachinko hall is opened and the power is turned on with the initialization switch 85 turned on, the determination in step ST3 is Yes.
Then, the work area of the RAM is initialized, and the other RAM areas are cleared to zero (ST5). And
The CPU is set to the interrupt permission state (EI) (ST
5) Then, random number generation processing is performed in an infinite loop (ST6). Note that the process of step ST6 is a process for determining what kind of off-game to produce when the game is in a missed state due to a determination such as a big hit determination process described later.

On the other hand, when the initialization switch 85 is in the OFF state as in the case of recovery from the power failure state, the backup flag BFL follows the determination in step ST3.
Is determined (ST4). Backup flag B
The FL is data indicating whether the backup data at the time of the interruption operation saved in the NMI process is restored to the original state, and in this embodiment, the backup flag BFL is set to 5AH in the process of step ST25. And is cleared to zero in the process of step ST12.

Now, assuming a time of recovery from a power failure state,
The content of the backup flag BFL is 5AH. Therefore, the processing of the CPU is performed from step ST4 to step S4.
In T7, the 16-bit data read from the SP storage area of the RAM is written to the stack pointer SP of the CPU (ST7).

Next, each data saved in the NMI process at the time of the power failure is read, and a process of restoring the backed up command is performed (ST8). Here, the command is a command transmitted from the main control board to each control board, and is used to excite the game by an image or sound or to pay out a prize ball.
Creates necessary commands by reading saved data. Next, the CPU executes the POP instruction,
Each register except the AF register from the stack area (B
C, DE, and HL) are restored (ST9). When this process is completed, the data in the SP storage area is cleared to zero (ST11). This step ST1
The processing 1 is not necessarily technically essential, but is based on the guidance from a public organization and is always executed.

As a result of the above processing, the recovery processing from the time of the power failure is completed for the time being, so the backup flag BFL is cleared to zero to indicate that (ST12). As described above, in the present embodiment, the process of clearing the data in the SP storage area to zero (ST11) and the backup flag BFL
Is continuously performed, the data in the SP storage area is cleared to zero, but the user reset signal URST may be applied to the CPU in a state where the backup flag BFL is not cleared to zero. Is extremely small, and there is almost no possibility of occurrence of an abnormal situation.

That is, in a state where the data in the SP storage area has been cleared to zero but the backup flag BFL has not been cleared to zero, if the CPU is reset due to an unexpected malfunction of any circuit, the operation after the reset is reset. , After step ST4, step ST
7, the stack pointer SP contains 0
000H.

Then, the subsequent return processing (POP instruction)
In, data will be restored, and the game operation completely unrelated to before the interruption will be resumed,
Or, a situation may occur in which the program runs away.
However, in this embodiment, the process of clearing the data in the SP storage area to zero (ST11) and the backup flag B
Since the process of clearing the FL to zero (ST12) is performed continuously, such a possibility becomes practically zero. Moreover, in this embodiment, since the watchdog timer WDT is cleared at the timing of t2 in FIG. 7, such an abnormal situation can be reliably prevented.

As described above, in the present embodiment, step ST
11 and ST12 are executed consecutively, but the data in the SP storage area is cleared to zero and the backup flag BFL is cleared to zero even though the restoration of the AF register has not been completed. ST11 and ST12
This is because if the processing of (1) is postponed, the data of the A register that has been restored will be destroyed.

Therefore, in this embodiment, after the backup flag BFL is cleared to zero, the I register and the AF register are restored. Specifically, first, P
By executing the OPAF instruction, the contents of the I register are returned to the F register (ST13). In the NMI interrupt processing program, after loading the value of the I register into the A register, the value of the A register is PUSHed (FIG. 1).
0 (c)), the POP instruction causes the value of the interrupt enable flip-flop IFF inside the CPU to be stored in the P / V flag of the F register.

Here, when the P / V flag is 1, NM
The CPU at the time of the I processing is in the interrupt enabled state. Conversely, when the P / V flag is 0, the CPU at the time of the NMI processing is in the interrupt disabled state. Therefore,
If the P / V flag is 0, the POP instruction is executed again to restore the value of the AF register, and the RET instruction is executed in the interrupt disabled state (ST15, ST16). On the other hand, if the P / V flag is 1, the POP instruction is executed again to restore the value of the AF register, the state is changed to the interrupt enabled state, and the RET instruction is executed (ST17 to ST19). Whatever it is,
By executing the RET instruction, the value of the PC (program counter) at the time of the interruption that has been subjected to the PUSH processing in the stack area is restored, and the processing that has been interrupted due to a power failure or the like is resumed.

By the way, if the CPU reset signal URST is sometimes issued from the watchdog timer WDT after the processing of step ST12 is completed, the processing of the CPU after being reset again goes from step ST4 to step ST5. Since the transition is made, the interrupted game operation can no longer be resumed. However, with this pachinko machine,
Since the watchdog timer WDT is cleared before the CPU is reset (t2 in FIG. 7), the possibility that the CPU will be reset without meaning is extremely low.

In order to further eliminate the possibility that the CPU is reset, as indicated by the broken line in FIG. 9, prior to the processing (ST11, 12) indicating the completion of the return processing from the time of the power failure, the timing of step ST10 is set. , A timer clear signal may be output to the watchdog timer WDT.
In this case, the same processing in addition to the timing of t2 in FIG. 7 is executed, set a short H-level period T _WD reset output of the watchdog timer WDT in the free-running state (specifically Even if the time constant C1 × R1 is reduced), and the response at the time of program runaway is speeded up, no trouble is caused.

FIG. 10 is a flowchart showing the contents of an NMI interrupt processing program which is generated when the power supply voltage drops due to a power failure or the like. In this interrupt processing, first, the contents of each register (AF, I, BC, DE, HL) are pushed to the stack area (ST20). However, since the value of the I register cannot be directly pushed to the stack area, the execution of the instruction of LDA, I is followed by the execution of the instruction of PUSH AF.

Next, the contents of the storage area of the backup flag BFL shown in FIG.
The contents of the P storage area are checked (ST21). FIG.
As described with respect to steps ST11 and ST12, when the operation returns from the NMI interrupt to normal, the contents of the backup flag BFL and the SP storage area should be zero. Therefore, in the determination of step ST21, the case where the condition that both are zero is not satisfied means that the NMI interrupt has occurred again during the NMI interrupt return processing (ST1 to ST10).

In such a case, even if the processing shifts to the processing after step ST22, in step ST22, N
Since the value of the stack pointer SP at the time of the MI interrupt is destroyed, the state before the power failure cannot be restored. Therefore, in this embodiment, during the return processing of the NMI interrupt (ST
If the power supply voltage drops again and an NMI interrupt occurs again during the period from 1 to ST10), the process is shifted to the address 0000H. By responding in this manner, the processing of the main routine proceeds from step ST1 to step ST4, and further proceeds to step ST4.
By proceeding to 7, the process before the interruption can be restored.

On the other hand, in the normal case where the contents of the backup flag BFL and the SP storage area are both zero, the processing shifts from step ST21 to step ST22, and the value of the stack pointer SP after the execution of the PUSH instruction in step ST20 becomes It is stored in the SP storage area of the RAM (ST22). FIGS. 10B and 10C show the registers (AF, I, BC, DE, HL) and the stack pointer S.
P shows the save state of the program counter PC.

Subsequently, since the prize ball may be currently being paid out, the state of the prize ball counting switch is detected and stored (ST23). Note that waiting for a predetermined time (ST2
4), taking into account the time required for the prize balls being paid out to move. In addition, although not shown, after backing up necessary data, the flag value 5AH is stored in the RAM area of the backup flag BFL (ST25).
The access of the AM is prohibited, and the CPU waits for the power supply voltage to drop and the CPU to become inactive (ST26). After that, CP
U goes into a non-operating state, but since backup power is supplied to the RAM, the backed up data is kept stored as it is. That is, even after the power is completely shut off, the RAM area is maintained in the state shown in FIGS.

FIG. 11 is a flowchart showing the contents of an interrupt processing program of a timer interrupt INT (maskable interrupt prohibition interrupt) generated every 2 msec during the infinite loop processing (ST6) of the main routine (FIG. 9). When a timer interrupt occurs, the contents of each register are saved in the stack area, and random number creation processing, switch input management processing, error management processing, and the like are performed (ST30). The switch input management process is for determining whether or not a game ball has passed through a gate, an electric tulip, or the like, and the error management process is for determining whether or not an abnormality has occurred inside the device.
Further, the random number generation process means a process of acquiring a hit random number value or a jackpot random number value updated in hardware.

Thereafter, the value of the processing division counter is determined, and the corresponding processing of ST32 to ST36 is performed. The error management and switch management described above should be repeated at short time intervals, while the processing related to the performance of the pachinko game requires more than a certain amount of processing time because the processing becomes more sophisticated according to the needs of the player. Will be. Therefore, in this embodiment, all the game control operations are set to 1
Rather than being completed in one interrupt process, the process is divided into five types of processes, and each of the divided processes is shared and executed for each interrupt. Therefore, a processing division counter that circulates in the range of 0 to 4 is provided, and processing according to the value of the processing division counter is performed.

More specifically, when the processing division counter is 0, processing relating to opening of a special winning opening is performed (ST32), and when the processing division counter is 1, it is determined whether a hit state (opening of the electric tulip) has occurred. Ordinary symbol processing regarding whether or not the processing is performed (ST32), and when the processing division counter is 2, processing regarding whether or not the state is a big hit state is performed (ST32).
32). If the processing division counter is 3, a timer management process related to the opening / closing timing of the electric tulip and the winning port, and a command creation process transmitted from the main control board to each control board are performed (ST35). If the processing division counter is 4, information output and error display command creation processing are performed (ST36). Thereafter, a timer clear signal is output to the watchdog timer WDT (ST37).

Since the processing of step ST37 is executed in the fifth interrupt processing, the generation cycle of the timer clear signal in step ST37 is normally 2 msec ×
5 However, if the power is restored after an NMI interrupt has occurred, a further main routine (FIG. 9) is performed.
Is added, the timer clear signal is not generated for a time longer than 2 msec × 5. However, in the case of the present embodiment, the watchdog timer WDT is cleared at least when the power is turned on (timing t2 in FIG. 7), so that the CPU is reset and interrupted after recovery from a power failure or the like without meaning. There is no adverse effect that processing cannot be returned.

When any one of steps ST32 to ST36 is completed, the value of the processing division counter is updated (ST39), and the generated command is transmitted to each control board (ST40). Further, the value of each register is restored, and at the same time, the state is changed to the interrupt enabled state, and the process returns from the interrupt processing routine to the main routine (ST40). As shown by the broken line in FIG. 11, a timer clear signal may be output to the watchdog timer WDT for each interrupt (ST38). In this case, the charge / discharge capacitor C1
It is possible to set the time until the completion of the charging of the CPU shorter, detect the runaway of the program more quickly, and reset the CPU.

Although the embodiment of the present invention has been described above, the specific technical contents do not particularly limit the present invention. For example, it is preferable that the processing order of step ST11 and step ST12 shown in FIG. 9 be reversed. That is, in such an embodiment, in any case, the CPU is not reset in a state where the backup flag is not cleared to zero even though the SP storage area is cleared to zero. Although the SP storage area is not cleared to zero even though
Only the PU is reset. Then, even in the worst case, since the backup flag is cleared to zero, the process proceeds to step ST5 after the process of step ST4, and the reset process is correctly performed.

As shown by the broken line in FIG. 9, a clearing process of the watchdog timer WDT may be provided after step ST6 instead of or in addition to step ST37 (ST38). The output of the OR gate G1 is not limited to the case where the output is supplied to the watchdog timer WDT via a capacitor as in the embodiment, but may be supplied directly to the reset means WDT.

[0068]

As described above, according to the present invention,
When the interrupted game operation is restarted, the original game can be reproduced as much as possible even if there is a fluctuation in the power supply voltage or other electric trouble.

[Brief description of the drawings]

FIG. 1 is a perspective view of a pachinko machine according to an embodiment.

FIG. 2 is a side view of the pachinko machine of FIG.

FIG. 3 is a front view of the pachinko machine of FIG.

FIG. 4 is a rear view of the pachinko machine of FIG.

FIG. 5 is a circuit example of a watchdog timer circuit and a system reset circuit.

FIG. 6 is a time chart illustrating a circuit operation of a system reset circuit.

FIG. 7 is a time chart illustrating the operation of the watchdog timer circuit.

FIG. 8 is a time chart and a comparison circuit diagram for explaining the effect of the present embodiment.

FIG. 9 is a flowchart of a main routine of a game control program according to the embodiment.

FIG. 10 is a flowchart of an NMI interrupt processing program executed at the time of a power failure or the like.

FIG. 11 is a flowchart of an INT interrupt processing program in a timer interrupt.

[Explanation of symbols]

 WDT Watchdog timer 2 Gaming machine (Pachinko machine) ST37 Clear processing 52 Clear circuit (System reset circuit)

Claims (8)

[Claims] 1. While realizing a game operation according to a control program stored in the device, when a normal process according to the control program is not performed,
A gaming machine in which a reset means WDT functions to forcibly return a game operation to an initial state, and outputs a clear signal at predetermined time intervals to prevent the reset means WDT from functioning. And a clear circuit 52 for outputting an initial signal PS at power-on and delaying the timing at which the reset means WDT functions. 2. The game according to claim 1, wherein the clear circuit 52 is configured to repeatedly output the initial signal PS in response to a change in the power supply voltage when the power is turned on. Machine. 3. The gaming machine according to claim 2, wherein the initial signal PS is generated based on a power reset signal SYSRST. 4. The gaming machine according to claim 3, wherein the initial signal PS is generated based on the wide-shaped signal after the power reset signal SYSRST is broadly shaped. 5. The gaming machine according to claim 1, wherein the clear circuit 52 generates a system reset signal RST for resetting a CPU in addition to the initial signal PS. 6. The gaming machine according to claim 5, wherein the initial signal PS is an inverted signal of the system reset signal RST. 7. The clear signal and the initial signal P
The gaming machine according to any one of claims 1 to 6, further comprising an OR gate receiving S, wherein an output of the OR gate is directly or indirectly supplied to the reset unit WDT. 8. The control program includes a first process started in response to power-on and usually ended in an infinite loop process, and a second process repeatedly executed at predetermined time intervals (T). The second process includes a common process executed every time the predetermined time (T) and a time (N
The gaming machine according to any one of claims 1 to 7, comprising: T) a total of N kinds of sorting processes executed at intervals; and wherein the clearing process is executed by any one of the sorting processes.