JP4431557B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, an arrangement ball machine, a sparrow ball game machine, and a revolving game machine, and in particular, even if a power failure occurs during a game operation, the original game operation is normally performed after power is restored. It relates to an improved gaming machine so that it can be resumed.

  A game machine with a built-in microcomputer, such as a pachinko machine, cannot continue normal operation when the power supply voltage falls below a predetermined value, and measures against power outages due to lightning strikes are necessary. In such a case, a countermeasure may be considered in which each game hall is provided with a private power generation device. However, the power consumption of the gaming machines is not small and the number of the gaming machines is large.

  Therefore, as a general countermeasure against a power failure, necessary data is saved in the RAM area by non-maskable interrupt processing (Non Maskable Interrupt) and other interrupt processing (Maskable Interrupt), and the stored contents are maintained by a backup power supply. When the commercial power is restored, the saved data is read to reproduce the gaming operation before the power failure.

  However, troubles such as power outages occur suddenly, so the above measures may not be sufficient. For example, it is divided into a main control board having main control means for centrally controlling game operations and a sub control board having sub control means for realizing control operations in accordance with control commands from the main control means. In the case of a game machine that is in use, if a power failure occurs during transmission of a control command, there is a possibility that the game operation cannot be resumed after the power is restored.

  FIG. 15 is a diagram for explaining the relationship. In the main control board, the OUT command is executed at the timing T1, the control command is written to the output port, and the dispensing control board is interrupted at the timing T2. Show. Thereafter, the payout control board executes the IN command at the timing of T3 and reads the control command from the input port. The shaded portion indicates the time required to execute each instruction.

  For example, when performing the control operation as described above, the period from T1 to T3 is an indeterminate period, and if the power supply voltage is interrupted during this period, the control command is lost. That is, when a power failure occurs during execution of the OUT command (shaded portion) on the main control board, the OUT command itself is executed, but the output port data (control command) is lost due to the power supply voltage being cut off. The same applies when a power failure occurs after the control command is acquired at the input port and before the IN command is executed on the payout control board, and the data of the input port is lost due to the interruption of the power supply voltage. .

  In such a case, if the lost control command is a control command related to paying out a prize ball, the player cannot obtain a predetermined prize ball, so there is no unnecessary trouble with the game hall. However, it is extremely important to accurately reproduce the game action through thorough countermeasures.

  The present invention has been made based on such a request, and is improved so that the game operation can be normally reproduced regardless of the interruption of the power supply voltage or other electrical trouble at any timing during the game operation. It is an object to provide an improved gaming machine.

In order to solve the above-mentioned problems, the invention according to claim 1 is directed to a main control means for centrally controlling a gaming operation, and a predetermined apparatus for a gaming machine based on a command signal having a predetermined bit length from the main control means. In the gaming machine divided into sub-control means for controlling the operation, the command signal is divided into a first signal and a second signal obtained by dividing the predetermined bit length and transmitted from the main control means to the sub-control means. In the main control means, the command signal being transmitted to the sub-control means is temporarily stored and then stored and erased, and the function signal is stored immediately after recovery from an abnormal situation. Re-transmission means for re-transmitting the command signal on condition that the command signal is not erased, and the sub-control means functions when the power supply voltage falls below a predetermined value, and the main control The command signal from the means is received and this A first means for determining whether the presence already command signal (S23), and function if it is determined not been stored by the first means, based on the value of the decision variable, received command signal is first The second means (S24) for determining whether the signal is the second signal or the second signal, and functioning when the second means determines that the signal is the second signal, returns the determination variable to the initial state and receives the received command signal Is determined as a second signal from the numerical range, and if it is determined as a second signal, third means (S25, S26) for shifting to a process of storing the received command signal in the memory; Whether the received command signal is valid as the first signal by functioning when the third means determines that it is not a valid second signal, or when the second means determines that the signal is a first signal. fourth means for determining from the numerical range ( And 29), when it is determined that the first signal valid in the fourth means is configured to change the determination variable to the value indicating that the fifth means for storing the received command signal to the memory ( S30) and backup means for maintaining the stored contents of the memory including the command signal and the determination variable even after the power supply voltage is cut off . The storage unit of the present invention may function only when a specific command signal is transmitted (or for a specific sub-control unit), or may function when all command signals are transmitted (or for all sub-control units). You can do it.

  According to the present invention, since the command signal is retransmitted immediately after recovery from the abnormal situation, no trouble occurs even if the command signal is lost. Since there is a possibility that the same command signal is transmitted in duplicate, it is preferable to provide the sub-control means with an exclusion means for prohibiting acquisition of the command signal when the command signal is duplicated.

  In the present invention, since an unacquired command signal is acquired in accordance with the occurrence of an abnormal situation, the loss of the command signal is prevented. Note that the backup means may be provided on all the sub-control boards or only on a specific sub-control board.

  As described above, according to the present invention, it is possible to realize a gaming machine that can reproduce the gaming operation normally regardless of the fluctuation of the power supply voltage and other electrical troubles at any timing during the gaming operation.

  Hereinafter, an embodiment of the present invention will be described based on a card-type ball game machine which is an embodiment of the present invention. FIG. 1 is a perspective view showing a pachinko machine 2 according to the present embodiment, and FIG. 2 is a side view of the pachinko machine 2.

  The pachinko machine 2 shown in FIG. 1 is a rectangular frame-shaped wooden outer frame 3 that is detachably mounted on the island structure and a hinge H that is fixed to the outer frame 3 before being pivotably mounted. It consists of a frame 4. A plurality of pachinko machines 2 are arranged in the length direction of the island structure of the pachinko hall while being electrically connected to the card-type ball lending machine 1.

  A game board 5 is detachably attached from the back side to the front frame 4 pivotally attached to the outer frame 3 via a hinge H. A glass door 6 having a window portion corresponding to the front side of the game board 5 and A front plate 7 is pivotally attached to each other so as to be freely opened and closed. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and launching means 10 at the lower part of the front frame 4. And a firing handle 11 are provided.

  The launching means 10 includes a launching handle 11 that can be rotated, and a launching motor that launches a game ball with a striking rod 12 (FIG. 4) with a striking force corresponding to the rotational angle of the launching handle 11. On the right side of the upper plate 8, there is provided an operation panel 13 for a ball lending operation for the card-type ball lending machine 1, and on this operation panel 13, a card remaining amount display portion 13a for displaying the remaining amount of the card with a 3-digit number. And a ball lending switch 13b for instructing lending of game balls for a predetermined amount, and a return switch 13c for instructing to return the card at the end of the game.

  As shown in FIG. 3, the game board 5 is provided with a guide rail 15 made of a metal outer rail and an inner rail in a substantially annular shape, and a color liquid crystal is provided in the game area 5 a inside the guide rail 15. A display 16, a symbol start opening (design start means / winning means) 17 having a detection switch, an open / close type winning means (large winning means) 18, a plurality of normal winning means 19 (in addition to the upper normal winning means 19, an open / close type winning prize) Six normal winning means 19) and two gates 20 (passage openings) are arranged at predetermined positions on the left and right sides of the means 18, respectively.

  The liquid crystal display 16 functions as a first symbol display means 22 that displays a changing symbol and also displays a background image, moving images of various characters, and the like. The first symbol display means 22 displays background images and characters in an animated manner, and has three (left, middle, and right) symbol display portions 22a to 22c arranged in the left-right direction. On the condition that the ball wins, the display symbols of the symbol display portions 22a to 22c are variably displayed (scrolled) for a predetermined time, and based on the lottery result corresponding to the winning timing of the game ball at the symbol start port 17. Stop at the determined stop symbol pattern.

  A normal winning means 19 and a second symbol display means 23 are provided immediately above the liquid crystal display 16. The second symbol display means 23 has a normal symbol display unit for displaying one normal symbol. When a game ball that has passed through the gate 20 is detected, the display symbol of the normal symbol display unit fluctuates for a predetermined time, A stop symbol determined by a random number for lottery drawn at the time the game ball passes through the gate 20 is displayed and stopped. The symbol starting port 17 is an electric tulip having a pair of left and right opening and closing claws 17a that can be opened and closed. When the stop symbol after the change of the second symbol display means 23 is hit and the symbol is displayed, the opening and closing claws 17a It is open for a predetermined time, making it easy to win.

  The open / close-type winning means 18 includes an opening / closing plate 18a that can be opened forward, and when the stop symbol after the fluctuation of the first symbol display means 22 is a winning symbol such as “777”, a special game called “big hit” is started. The opening / closing plate 18a is opened to the front side. The opening / closing operation of the open / close winning means is controlled by the main control means of the main control board. There is a specific area 18b inside the openable winning means 18, and when the winning ball passes through the specific area 18b, the special game is continued. Here, the special game state corresponds to a state advantageous to the player.

  After the opening / closing plate 18a of the open / close winning means 18 is opened, when a predetermined time elapses, or when a predetermined number (for example, 10) of gaming balls wins and the opening / closing plate 18a is closed, the gaming ball is in the specific area 18b. If it has not passed, the special game ends. However, if it has passed the specific area 18b, the special game is continued up to, for example, 16 times, and is controlled in a state advantageous to the player.

  As shown in FIG. 4, on the back side of the front frame 4, a back mechanism plate 30 that presses the game board 5 from the back side is detachably mounted. The back mechanism plate 30 has an opening 30a formed on the top side thereof. A prize ball tank 33 and a tank rail 34 extending from the prize ball tank 33 are provided. A payout device 35 connected to the tank rail 34 is provided on a side portion of the back mechanism plate 30. A passage unit 36 connected to 35 is provided. The game balls paid out from the payout device 35 are paid out to the upper plate 8 from the upper plate discharge port 8a (FIG. 1) via the passage unit 36.

  The opening 30a of the back mechanism plate 30 is fitted with a back cover 37 mounted on the back side of the game board 5 and a winning ball discharge basket (not shown) for discharging the winning game balls to the winning means 17-19. Are combined. A main control board 39 is disposed inside a case 38 attached to the back cover 37, and a symbol control board 40 is disposed on the front side thereof (FIG. 2). Below the main control board 39, a lamp control board 42 is provided in a case 41a attached to the back cover 37, and a sound control board 43 is provided in a case 41b adjacent to the case 41a.

  A power supply board 45 and a payout control board 46 are provided inside the case 44 mounted on the back mechanism plate 30 below the cases 41a and 41b. As shown in FIG. 4, a power switch 80 and an initialization switch 85 are disposed on the power board 45. Cases 44 are notched at portions corresponding to these switches 80 and 85, and each of the switches 80 and 85 can be operated simultaneously with a finger.

  A launch control board 48 is provided inside the case 47 attached to the rear side of the launch means 10. These control boards 39 to 40, 42 to 43, 45 to 46, and 48 are independent boards, and the control boards 39, 40, 42, 43, and 46 excluding the power supply board 45 and the launch control board 48 have one chip. A computer circuit including a microcomputer is mounted, and the main control board 39 and the other control boards 40, 42, 43, 46 are electrically connected via a connector with a plurality of signal lines. The one-chip microcomputer used in this embodiment is configured by incorporating a CPU, ROM, RAM, and other ICs equivalent to Z80 (Zilog).

  As shown in FIG. 5, the main control board 39 and the other control boards 40, 42, 43, 46 are electrically connected via a connector with a plurality of signal lines, and each control board is connected to the main control board 39. Various control commands for executing predetermined game operations can be transmitted to one of the 40, 42, 43, and 46 by one-way communication. By adopting one-way communication of the control command, the control load on the main control board 39 can be remarkably reduced, and transmission control can be simplified.

  FIG. 6 is a block diagram showing a circuit configuration of the main control board 39. As shown in the figure, the main control board 39 includes a CPU circuit 50 composed of the above-described one-chip microcomputer, a system clock generator 51 that generates a clock signal Φ0 that is an integer multiple of the CPU operating clock CLK, and an address from the CPU. A decode circuit 52 that generates a chip select signal CS for each part based on the signal, an output port circuit 53 for outputting data from the CPU, an input port circuit 54 for the CPU to take in external data, and each control board An output drive circuit 55 that outputs control commands and the like, and a switch input circuit 56 that inputs ON / OFF states of switches of each part of the game board are mainly configured. The main control means includes the functions realized by this configuration. The same applies to the sub-control means.

  FIG. 7 is a block diagram illustrating a specific configuration of the output port circuit 53 and the output drive circuit 55. In detail, the output port circuit 53 includes a prize ball port 53a, an audio port 53b, a lamp port 53c, a symbol port 53d, and a strobe port 53e, and bus transceivers 57 and 58 (74245 equivalent in the embodiment). ) To the CPU data bus.

  The prize ball port 53a, the voice port 53b, the lamp port 53c, and the symbol port 53d correspond to the payout control board 46, the voice control board 43, the lamp control board 42, and the symbol control board 40, respectively. A control command is output to each control board through a corresponding bus buffer (74244 equivalent product in the embodiment).

  Specifically, the output ports 53a to 53e are configured by D-type flip-flops (74273 equivalent product in the embodiment), and control commands and strobe signals are synchronized with the chip select signals CS0 to CS4 from the decoder circuit 52. The STB is acquired. Note that after the power is turned on to the main control board 39, the outputs of the output ports 53a to 53e are all cleared to zero.

  Outputs P0 to P3 of the strobe port 53e are supplied as strobe signals STB to the control boards 46, 43, 42, and 40. When the strobe signal STB becomes H level, the CPUs of the control boards 46, 43, 42, and 40 ( An interrupt (Maskable interrupt) is applied to the Z80 equivalent product, and a control command from the main control board 39 is acquired by each interrupt processing program of each control board 46, 43, 42, 40.

  8 and 9 are flowcharts showing a control program for the main control board 39. The control program for the main control board 39 is an initial processing program (FIG. 8) that is executed after power-on and normally ends with an infinite loop processing (ST6), and a timer interrupt processing (Maskable Interrupt disableable interrupt) program that is started every 2 ms. (FIG. 9) and an NMI processing program (not shown) that is driven by an NMI (Non Maskable interrupt) signal to back up the register value of the CPU when the power supply voltage falls below a predetermined value.

  Hereinafter, the timer interrupt process will be described with reference to FIG. When a timer interrupt occurs, the contents of each register are saved in the stack area, and random number generation processing, switch input management processing, error management processing, and the like are performed (ST30). The switch input management process is a determination as to whether or not a game ball has passed through a gate or an electric tulip, and the error management process is a determination as to whether an abnormality has occurred inside the device. The random number generation process means a process for acquiring a hit random number value or a jackpot random value that is updated in hardware.

  Thereafter, the value of the process division counter is determined, and the corresponding process from ST32 to ST36 is performed (ST31). The above error management and switch management should be repeated at short time intervals. On the other hand, the processing related to the pachinko game production is complicated and sophisticated according to the player's needs, and therefore requires a certain amount of processing time. It will be. Therefore, in this embodiment, not all the game control operations are completed by one interrupt process, but are divided into five types of processes, and each divided process is divided and executed for each interrupt. Yes. Therefore, a processing division counter that circulates in the range of 0 to 4 is provided to perform processing according to the value of the processing division counter.

  More specifically, when the processing division counter is 0, processing relating to the opening of the big prize opening is performed (ST32), and when the processing division counter is 1, whether the winning state (electric tulip is open) or not. Normal symbol processing is performed (ST33), and when the processing division counter is 2, processing relating to whether or not a big hit state is performed (ST34). If the processing division counter is 3, timer management processing related to the opening / closing timing of the electric tulip and the big prize opening and command creation processing transmitted from the main control board to each control board are performed (ST35). If the process division counter is 4, information output and error display command creation processing is performed (ST36).

  When any one of steps ST32 to ST36 is completed, the value of the process division counter is updated (ST37), and the generated command is output to each control board (ST38). Further, the value of each register is restored and changed to the interrupt enabled state, and the routine returns from the interrupt processing routine to the main routine (ST39).

  FIG. 10 is a flowchart showing the above-described command output process (ST38) in more detail. As described with reference to FIG. 7, there are control commands for the payout control board, the voice control board, the lamp control board, and the symbol control board, and all of them are basically output with the same algorithm. Hereinafter, the control commands output to the payout control board 46 will be mainly described.

  In this embodiment, all control commands have a 2-byte structure. Therefore, in order to separately output the upper 8 bits of MODE data indicating the operation type and the lower 8 bits of EVENT data indicating the operation content, 2 is first stored in the variable LOOP (ST41). The control command for the payout control board specifies the payout operation (70H) by the MODE data and the stop or restart (80H) of the payout operation, and the number of prize balls to be paid out by the EVENT data (1 to 16). In addition, either stop or restart is specified. Specifically, 70nnH means a payout command for nn game balls, 8011H means a payout operation stop command, and 8012H means a payout operation restart command.

  After the processing of step ST41, whether or not the data to be output is MODE data (first byte) directed to the payout control board 46 (ST42), and EVENT data (second byte) directed to the payout control board 46 Is determined (ST43). There are control command data to be output for symbol control boards, lamp control boards, and voice control boards. Whether or not the command is a control command for the payout control board depending on the address value of the command buffer area of the RAM. Is determined (see FIG. 10B).

  If the control command is directed to the payout control board 46, the control command data to be output is first stored in the SAFBAK address (ST44). As described above, in this embodiment, among the control commands for the payout control board, the voice control board, the lamp control board, and the symbol control board, only the control command for the payout control board is stored in the RAM area. However, this corresponds to the fact that the data backup process is performed only by the payout control board 46 in addition to the main control board 39 when the power supply voltage drops.

  When the above processing is completed, control command data is output to the corresponding port (ST45). Specifically, one of the chip select signals CS0 to CS3 is output from the decode circuit 52, and the control command data is written to the D-type flip-flop 53. Thereafter, after another process requiring 49 states or more is executed (ST46), the corresponding bit of the strobe port 53e is set to the H level (ST47).

  If a control command is output to the payout control board 46, (P3, P2, P1, P0) = (H, L, L,) via the bus transceiver 58 from the CPU to the strobe port 53e. L) data is output, and the chip select signal CS4 is output from the decode circuit 52, and the strobe signal STB directed to the payout control board 46 becomes H level. By this operation, the CPU of the payout control board 46 is interrupted (Maskable Interrupt), and the input process of the control command is performed (this point will be further described later).

  Thereafter, after a sufficient time has been consumed to complete the data acquisition process on the control board that has received the control command (ST48), the data at the SAFBAK address is cleared to zero (ST49). Therefore, it is possible to determine whether or not a control command for the payout control board 46 has been acquired by the payout control board 46 only by checking the data of the SAFBAK address.

  When the zero clear of the SAFBAK address is completed, the corresponding bit Pi of the strobe port 53e is returned to the L level, and the strobe signal STB directed to the corresponding control board is set to the L level. However, the operation order of steps ST49 and ST50 may be reversed. Next, the variable LOOP is decremented (ST51), and the processes of steps ST42 to ST51 are repeated until the value becomes 0. Specifically, the processing of ST42 to ST51 is executed twice for the control board to which the control command is to be output, and MODE data and EVENT data are continuously output. Note that this processing is not limited to the payout control board 46 as long as there is a control command to be output to the corresponding control board (that is, as long as there is data in the command buffer area as shown in FIG. 10B). The sound control board 43, the lamp control board 42, and the symbol control board 40 are also performed.

  FIGS. 11A to 11D are timing charts showing the output process of the control command data to the payout control board 46 described above. The control command is saved at the timing t1 (ST44), the control data is output at the timing t2 (ST45), the strobe signal becomes H level at the timing t3 (ST47), and the SAFBAK address is cleared at the timing t4. (SY49), the strobe signal is set to L level (ST50).

  By the way, this gaming machine is configured such that an NMI (Non Maskable interrupt) interrupt is applied to the CPU of the main control board 39 and the payout control board 46 when the power supply voltage falls below a predetermined value during operation. When an NMI interrupt is applied, all the registers of the CPU are stored in the RAM area, and the voltage of the work area of the RAM including the RAM is maintained by a backup power source. On the other hand, after the power is restored, the saved register value is restored to the state before the game interruption, and the interrupted game is resumed normally. Hereinafter, based on this point, the operation content after power-on will be described based on the flowchart of FIG.

  When the power is turned on, after the CPU is set to the interrupt disabled state, the CPU registers are initialized (ST1), and the CPU is set to the interrupt mode 2 (ST2). Thereafter, the RAM clear signal and the backup flag are checked (ST3, ST4). The RAM clear signal corresponds to the initialization switch 85, and the power switch 80 is turned on while pressing the initialization switch 85 with the front frame 4 of the pachinko machine 2 opened forward as at the start of business. When switched to the ON side, the RAM clear signal is in the ON state.

  If the RAM clear signal is ON (ST3: yes), after all the game information stored in the RAM is erased, the CPU sets an initial symbol to be displayed on the first symbol display means 22. In addition, after performing initial processing such as setting an interrupt cycle for periodically executing interrupt processing during the execution of this game control, the EI command is executed to set itself in an interrupt enabled state (ST5). Thereafter, random number processing (ST6) for the off symbol repeated in an infinite loop is performed. Note that the random symbol processing for the off symbol defines a off symbol pattern to be drawn on the liquid crystal display 16 when the special symbol lottery is interrupted in the interrupt processing described later.

  On the other hand, when the RAM clear signal is OFF when the power is turned on (ST3: no), after confirming that the backup flag is not zero (ST4), a backup data restoration process is performed (S7). The backup data restoration process is a process for restoring the data backed up by the NMI process in the event of a power failure or the like, and this processing is performed when the power is turned on without pressing the initialization switch 85 after the power failure is restored. The backup flag indicates whether or not the backup process has been completed, and is meaningful when the power failure occurs again before the process up to step ST16 is completed.

  If the power is restored from the power failure state, the content of the backup flag BFL is 5AH. Therefore, the processing of the CPU shifts from step ST4 to step ST7, and 16-bit data read from the SP storage area of the RAM is written into the stack pointer SP of the CPU (ST7).

  Subsequently, the data at the SAFBAK address is copied to the BSAFBK address (ST8). As described above, after the main control board 39 prepares the control command to the payout control board 48 until the payout control board 48 reliably acquires the control command (t1 to t4), A control command is stored at the SAFBAK address, and the data at the SAFBAK address is zero during other periods. Therefore, if the content of the SAFBAK address at the time of power failure recovery is other than zero, it means that a power failure has occurred during the transmission of the control command to the payout control board 48. Therefore, a process of step ST8 is provided in order to perform a control command retransmission process according to the contents of the SAFBAK address.

  Next, the RAM area data stored in the NMI process at the time of a power failure is read to create a backup return command (ST9 to ST11). Here, the backup return command creation process (ST9) for the payout control board means a preparatory operation for rechecking the error signal and outputting a control command according to the current state of the gaming machine to the payout control board 46. . For example, if the upper plate is full before the power failure, the error state is saved by the backup data, but the player is likely to collect the game balls due to the power failure. The current situation is being confirmed.

  In addition, the backup return command creation processing (ST10, ST11) for the symbol control board and the lamp control board is a so-called probability change state in which the gaming machine before the power failure is in a big hit state or the winning probability is increased. In such a case, the background color of the liquid crystal display unit is set in accordance with the operation state, and a sound effect can be generated.

  Next, the CPU reads the contents of the BSAFBK address saved in the process of step ST8 to the ACC (accumulator) and outputs it to the prize ball port 53a (ST12). When the output data is not zero (that is, when a control command is output), the bit P3 of the strobe port is set to the H level (ST14). By this process, the CPU of the payout control board 46 is interrupted, and the input process of the control command output to the prize ball port 53a is started. This kind of operation is provided in consideration of the possibility of a power failure at delicate timing (t1 to t4 in FIG. 11C) whether or not the payout control board 46 acquires a control command. In order to eliminate control command acquisition errors, the control command is retransmitted when the power is restored.

  Since the strobe signal STB rising to the H level is returned to the L level by the subsequent timer interrupt processing (FIG. 9, FIG. 10) (ST38, ST50), the H level period becomes longer than the original period. There is also. Therefore, even after the processing of the interrupt processing program on the payout control board 46 is completed and the CPU enters the EI (interrupt permission) state, the strobe signal STB may be at the H level, and the payout control board 46 overlaps with the payout control board 46. There is a risk of interruption. However, the occurrence of harmful effects is prevented by the processing shown in FIG.

  In any case, after the processing of step ST13 or ST14, the CPU executes the POP instruction to restore the values of the registers (BC, DE, HL) excluding the AF register from the stack area (ST15). As a result of this process, the recovery process from the power failure is completed, so the backup flag BFL is cleared to zero (ST16). Finally, it is checked whether or not the interrupt is prohibited before the power failure (ST17 and ST18), and after the AF register is returned from the stack area (ST19 and ST21), the process is terminated while the interrupt is disabled (ST19 and ST21). (ST20) Or, the process is finished after returning to the interrupt enabled state (ST22, ST23).

  Next, the operation content of the payout control board 46 will be described with reference to FIGS. The control operation of the payout control board 46 includes a command interrupt process (FIG. 12A) activated based on a strobe signal STB from the main control board 39, and a main process executed after power-on (FIG. 12B). And NMI interrupt processing (FIG. 13) that occurs when the power supply voltage drops. In the command interrupt process, a control command from the main control board 39 is input (S13, S17), and the input control command is interpreted and executed in the main process (S5). Further, since the data backed up by the NMI interrupt process is restored in the main process after the power is restored (S3), the process after the interruption is resumed (S4).

  The command interrupt process will be further described with reference to FIG. 12A. In the interrupt process that starts upon receiving the strobe signal STB from the main control board 39, the CPU first checks the value of the command counter COMCNT (S10). If the value of the command counter COMCNT is 1, it is normally command data (EVENT value) of the second byte, so the command counter COMCNT is rewritten to zero (S11), and whether the input data is within a valid numerical range. Confirm (S12).

  If the data exceeds the numerical range, the process proceeds to step S15. If not, the input data is stored in the area indicated by the pointer PNT (S13). Thereafter, the pointer is incremented (S14), the CPU is set in an interrupt enabled state (S18), and the process is terminated. On the other hand, if it is determined in step S10 that the command counter COMCNT is zero, it is checked whether the input data is within a valid numerical range as the first byte of command data (MODE value) (S15). As a result, if the data exceeds the numerical range, the process proceeds to step S18. If not, the input data is stored in the area indicated by the pointer PNT (S16). Then, after rewriting the value of the command counter COMCNT to 1 (S17), the process proceeds to step S18.

  As apparent from the above description, the value of the command counter COMCNT is cyclically changed from 0 → 1 → 0 → 1 → 0, so that the input data is originally the first byte data (COMCNT = 0). This indicates whether the data is originally the second byte data (COMCNT = 1). However, as described above, the main control board 39 may retransmit the command data after the power is restored (ST12, ST14). The possibility that the first byte data is continuous or the second byte data is continuous. There is. Therefore, in this embodiment, when the first byte of MODE data is continuous, the second byte of MODE data is overwritten in the same place through the path of steps S11 → S12 → S16 → S17. ing. On the other hand, when the second byte of EVENT data continues, the second EVENT data is ignored through the path from step S16 to S15.

  FIG. 14 specifically illustrates the operation contents of the command input process shown in FIG. As shown in FIG. 14A, when data is received in a normal procedure, only EVENT data is stored, and MODE data of the first byte is continuous (FIG. 14B), 2 Even if the EVENT data of the byte is continuous (FIG. 14 (c)), it shows that it operates normally.

  FIG. 13 is a flowchart showing the operation of the payout control board 46 in an NMI interrupt that occurs when the power supply voltage falls below a predetermined value. In the NMI interrupt program, first, registers are saved in the stack area (S20), and the value of the stack pointer SP is saved in the RAM storage area (S21). Next, input port data (control command data) is input (S22), and it is determined whether this is the same as the latest stored data (S23). If the data does not match the latest data, the operations in steps S24 to S31 are executed, and the control command data is stored in the RAM area by the same algorithm as in FIG.

  The case where the data acquired in the process of step S22 does not match the latest stored data is an NMI interrupt (non-maskable) while the control command data is being input by the interrupt process of FIG. ). Therefore, in this embodiment, control command data that has not been acquired is acquired in the backup process just in case. Since the same control command is transmitted again from the main control board 39 after the power supply voltage is restored (S12, S14), the same control command data may be reacquired in some cases, but the MODE data is Since it is either redundantly acquired or EVENT data is redundantly acquired, no problem occurs (see S24 to S31 and S10 to S17).

  In any case, after acquiring the missed control command data, the CPU waits for the power supply voltage to further drop to zero while performing an infinite loop process through other necessary processes (S32).

  As mentioned above, although the Example of this invention was described, it has only illustrated the specific example and does not specifically limit this invention. For example, in the embodiment, command data (1 byte) reacquisition processing (S24 to S31) at the time of data backup of the NMI interrupt in the payout control board 46, and command data (1 byte) retransmission processing in the main control board 39 ( ST12 to ST14) are provided, but only one of them may be provided. Such command data re-acquisition processing and / or command data re-transmission processing may be provided for other than the payout control board.

  Further, in the embodiment, the command data re-transmission processing in the main control board 39 is performed when the backup data is restored after the power supply is restored (the condition that the backup flag ≠ 0), but may be performed at other timings. good. For example, it is also preferable to execute the program when the program runs away and the CPU is reset by the operation of the watchdog timer. Also, unlike the case of the above embodiment, the main control board control program is composed of the main control process and the subsequent infinite loop process, and the CPU of the main control board is reset at regular intervals. The invention is preferred. In other words, even if the main control process is abnormally prolonged for some reason and the CPU is reset before the control command to the payout control board is normally transmitted, it is abnormal if a command data retransmission process is provided. The occurrence of the situation can be prevented.

  The present invention is applicable not only to the first type ball ball machine, the second type ball ball machine, and the third type ball ball machine, but also to a ball game machine having a winning opening but not a big winning hole. Of course you can. Further, the control circuit is not limited to the equipment configuration divided into the main control board, the symbol control board, the lamp control board, the voice control board, and the payout control board, and further, a so-called “production movable object”. It may be provided with an animal control board that controls a “display unit” that is called and used for notifying the internal winning state based on a control command. Further, as in the arrangement ball machine, it may be divided into a main control board, a symbol control board, a lamp control board, a voice control board, a payout control board, and a launch control board.

  In the case of an arrange ball machine, it is preferable to apply the present invention to a launch control board, and a control program similar to the payout control board described in the embodiment is provided on the launch control board, and the main control board has a control program for the payout control board. It is preferable to execute control command output processing and re-output processing in the same procedure as in the case. In this case, the launch control board acquires unacquired command data at the time of backup operation, and when a command is duplicated, the exclusion means functions to prohibit duplicate acquisition of command data.

  In the arrange ball machine, the number of game balls per unit game is determined, and the main control means manages the number of game balls per unit game using a launch ball detection switch, a return ball detection switch, a entrance switch, and the like. ing. Further, based on the fact that all of the determined number of game balls per unit game have entered the entrance, the main control means controls the launch control means for controlling the launch means for projecting and launching the game balls to the game area. In response to this, a “stop firing” command is transmitted by one-way communication. Further, the main control means transmits a “start firing” command to the firing control means by one-way communication at the start of the unit game.

  If a power failure occurs during transmission of this “stop firing” command and the launching means has not received the “stop firing” command, all the number of game balls per unit game entered the entrance. Nevertheless, after power is restored, the launch control means controls to launch the game ball in response to the player's launch operation. However, by applying the present invention to the arrange ball machine, the above-mentioned problems can be solved and the operation before the reliable interruption can be resumed. That is, the firing stop command is re-output from the main control board, and since the same control program as the payout control board is stored in the launch control board, the unacquired command can be reliably acquired during the backup operation. .

It is a perspective view of the pachinko machine concerning an example. It is a side view of the pachinko machine of FIG. It is a front view of the pachinko machine of FIG. It is a rear view of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram which shows the circuit structure of a main control board. The output port part of the main control board is illustrated in detail. It is a flowchart which shows the outline | summary of the system reset process in a main control board. It is a flowchart which shows the outline | summary of the timer interruption process in a main control board. It is a flowchart which shows the outline | summary of the control command output process in a main control board. It is a time chart explaining the control command output process in a main control board. It is a flowchart which shows the outline | summary of the main process and command input process in a payout control board. It is a flowchart which shows the outline | summary of the backup process at the time of the power supply cutoff in a payout control board. It is drawing explaining the command input process in a payout control board. It is drawing explaining the problem of a prior art.

Explanation of symbols

2 Pachislot machines (pachinko machines)
39 Main control board 40 Sub control board (design control board)
42 Sub-control board (lamp control board)
43 Sub control board (voice control board)
46 Sub control board (dispensing control board)
ST42 to ST45, ST49 Storage means ST12 to ST14 Retransmission means

Claims (3)

In a gaming machine divided into main control means for centrally controlling gaming operations and sub-control means for controlling the operation of a predetermined device of the gaming machine based on a command signal of a predetermined bit length from the main control means, The command signal is configured to be divided into a first signal and a second signal obtained by dividing the predetermined bit length and transmitted from the main control unit to the sub control unit,
The main control means includes
A storage means for erasing the command signal being transmitted to the sub-control means after temporarily storing;
Re-transmission means that functions immediately after recovery from an abnormal situation and re-sends it on condition that the stored command signal is not erased,
In the sub-control means,
A first means (S23) that functions when a power supply voltage falls below a predetermined value, receives a command signal from the main control means, and determines whether this is a stored command signal;
A second means (S24) that functions when the first means determines that the received instruction signal has not been saved, and determines whether the received command signal is the first signal or the second signal based on the value of the determination variable ;
It functions when the second means determines that the signal is the second signal , returns the determination variable to the initial state, and determines whether the received command signal is valid as the second signal from the numerical range. If it is determined that, the third means (S25, S26) for shifting to the process of storing the received command signal in the memory,
Whether the received command signal is valid as the first signal by functioning when the third means determines that it is not a valid second signal, or when the second means determines that the signal is a first signal. A fourth means (S29) for judging from the numerical range;
When the fourth means determines that the signal is a legitimate first signal, the fifth variable (S30) stores the received command signal in the memory while changing the determination variable to a value indicating that;
After that, the gaming machine is provided with backup means for maintaining the stored contents of the memory including the command signal and the determination variable even after the power supply voltage is cut off .   The gaming machine according to claim 1, wherein the predetermined device includes a payout device that pays out game media to a player.   The gaming machine according to claim 1 or 2, wherein the predetermined device includes a game ball launching device for projecting and launching a game ball into a game area.

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