JP4372122B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more particularly to an improved gaming machine so that the original gaming operation can be resumed normally after power is restored even if a power failure occurs during the gaming operation.

  A game machine with a built-in microcomputer such as a pachinko machine cannot continue normal operation when the power supply voltage falls below a predetermined value. Therefore, it is necessary to devise a device that will not be affected by a power failure caused by a lightning strike in a pachinko machine.

  Here, there may be a measure that includes a self-power generation device in each pachinko hall, but the power consumption of the pachinko machine is not small, and the number of pachinko machines is also large. Is not realistic.

  Therefore, as a general measure against power failure, the necessary data is saved in the RAM area by NMI processing, the backup power is supplied only to the RAM area, the contents are maintained, and if the commercial power is restored, the data is backed up. The data is read to reproduce the game operation before the power failure.

  However, troubles such as power outages occur suddenly. For example, if the pachinko machine before the power outage was in a big hit state, after the power is restored, the big hit game needs to be reproduced in any case. Otherwise, useless trouble will occur with the player. Moreover, even if it is not a power failure state, an unexpected abnormality may occur in the power supply line. For example, even if the power supply line fluctuates in an unstable state, an appropriate operation is desired.

  The present invention has been made on the basis of such a request, and when the interrupted game operation is resumed, even if there are fluctuations in the power supply voltage or other electrical troubles, It is an object to provide an improved gaming machine so that a game can be reproduced.

In order to solve the above problems, the invention according to claim 1 includes a CPU that controls a game operation based on a control program, and has a first state that is advantageous to the player and a second state that is disadvantageous to the player. A gaming machine that can be alternatively selected, and when the normal processing is not performed according to the control program, the reset means functions to forcibly return the gaming operation to the initial state, The control program is started in response to power-on, and includes a first process configured to include an infinite loop process , and a first process that is started by interrupting the first process every predetermined time, and controls a game operation repeatedly. second processing and the power supply voltage is started to force the falls below a predetermined level, and a third process of performing data saving process to save area, in the third process, after the data save processing, the stack pointer Identify value The predetermined flag with Save to憶area is set to a second state, wherein in the first process, on condition that said predetermined flag is in the second state, the stack based on the storage contents of said specified storage area After setting the pointer value, the data restoration process of the data saved in the save area is started, and then the saved contents of the specific storage area are rewritten together with the reset process for setting the predetermined flag to the first state. The clear process is executed, the reset process and the clear process are executed continuously, and the save destination of the save area in the data save process and the return source of the save area in the data return process are It is specified by the stack pointer.

The invention according to claim 2 has a Z80 CPU for controlling the game operation based on the control program, and selectively selects a first state advantageous to the player and a second state disadvantageous to the player. A possible gaming machine, configured so that when normal processing according to the control program is not performed, the reset means functions to forcibly return the gaming operation to the initial state , initiated in response to power-on, a first process is configured to include an endless loop, is started by interrupting said first processing for each predetermined time, and a second process of controlling the repetition game operation, power supply A third process for forcibly starting when the voltage falls below a predetermined level and performing a data save process to the save area. In the third process, after the data save process, the value of the stack pointer is Keep And the predetermined flag is set to the second state, and the first process sets the value of the stack pointer based on the stored contents of the specific storage area on the condition that the predetermined flag is in the second state. After the setting, the data restoration process of the data saved in the save area is started, and then the reset process for setting the flag to the first state is executed, and the save area is saved in the data save process. The return source of the save area in the data return process is specified by the stack pointer. In the data save process, the first process for saving the AF register value of the Z80 CPU and the value of the I register of the Z80 CPU are used. After the transfer to the A register of the AF register, the second processing for saving the value of the AF register is executed in this order. On the other hand, in the data restoration process, the data is restored in the reverse order of the save process, thereby specifying whether or not the Z80 CPU is in an interrupt enabled state, and the value of the AF register saved in the first process is set. I am trying to recover .

  As described above, according to the present invention, when the interrupted game operation is resumed, the original game is reproduced as much as possible even if there is a fluctuation in power supply voltage or other electrical trouble. It becomes possible.

  Hereinafter, an embodiment of the present invention will be described based on a card-type ball game machine which is an embodiment of the present invention. FIG. 1 is a perspective view showing a pachinko machine 2 according to the present embodiment, and FIG. 2 is a side view of the pachinko machine 2.

  The pachinko machine 2 shown in FIG. 1 is a rectangular frame-shaped wooden outer frame 3 that is detachably mounted on the island structure and a hinge H that is fixed to the outer frame 3 before being pivotably mounted. It consists of a frame 4. A plurality of pachinko machines 2 are arranged in the length direction of the island structure of the pachinko hall while being electrically connected to the card-type ball lending machine 1.

  A game board 5 is detachably attached from the back side to the front frame 4 pivotally attached to the outer frame 3 via a hinge H, and a glass door 6 having a window portion and a front side corresponding to the front side of the game board 5. A face plate 7 is pivotally attached to each other so as to be freely opened and closed. The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and launching means 10 at the lower part of the front frame 4. And a firing handle 11 are provided.

  The launching means 10 includes a launching handle 11 that can be rotated, and a launching motor that launches a game ball with a striking rod 12 (FIG. 4) with a striking force corresponding to the pivoting angle of the launching handle 11. . On the right side of the upper plate 8, there is provided an operation panel 13 for a ball lending operation for the card-type ball lending machine 1, and on this operation panel 13, a card remaining amount display portion 13a for displaying the remaining amount of the card with a three-digit number. And a ball lending switch 13b for instructing lending of game balls for a predetermined amount, and a return switch 13c for instructing to return the card at the end of the game.

  As shown in FIG. 3, the game board 5 is provided with a guide rail 15 made of a metal outer rail and an inner rail in a substantially annular shape, and a color liquid crystal is provided in the game area 5 a inside the guide rail 15. Display 16, symbol starting means (symbol starting and winning means) 17, open / close type winning means (large winning means) 18, a plurality of normal winning means 19 (in addition to the upper normal winning means 19, both the left and right sides of the opening / closing type winning means 18 Six normal winning means 19) and two gates 20 (passage openings) are arranged at predetermined positions.

  The liquid crystal display 16 functions as a first symbol display means 22 that displays a changing symbol and also displays a background image, moving images of various characters, and the like. The first symbol display means 22 displays background images and characters in an animated manner, and has three (left, middle, and right) symbol display portions 22a to 22c arranged in the left-right direction. On the condition that the ball wins, the display symbols of the symbol display units 22a to 22c are variably displayed (scrolled) for a predetermined time, and based on the lottery result corresponding to the winning timing of the game ball to the symbol starting means 17. Stop at the determined stop symbol pattern.

  A normal winning means 19 and a second symbol display means 23 are provided immediately above the liquid crystal display 16. The second symbol display means 23 has a normal symbol display unit for displaying one normal symbol. When a game ball that has passed through the gate 20 is detected, the display symbol of the normal symbol display unit fluctuates for a predetermined time, A stop symbol determined by a random number for lottery drawn at the time the game ball passes through the gate 20 is displayed and stopped. The symbol starting means 17 is an electric tulip having a pair of left and right opening and closing claws 17a that can be freely opened and closed. It is easy to win a prize by opening for a predetermined time.

  The open / close-type winning means 18 includes an opening / closing plate 18a that can be opened forward, and when the stop symbol after the fluctuation of the first symbol display means 22 is a winning symbol such as “777”, a special game called “big hit” is started. The opening / closing plate 18a is opened to the front side. There is a specific area 18b inside the openable winning means 18, and when the winning ball passes through the specific area 18b, the special game is continued. Here, the special game state corresponds to a state advantageous to the player.

  After the opening / closing plate 18a of the open / close winning means 18 is opened, when a predetermined time elapses, or when a predetermined number (for example, 10) of gaming balls wins and the opening / closing plate 18a is closed, the gaming ball is in the specific area 18b. If it has not passed, the special game ends. However, if it has passed the specific area 18b, the special game is continued up to, for example, 16 times, and is controlled in a state advantageous to the player.

  As shown in FIG. 4, on the back side of the front frame 4, a back mechanism plate 30 that presses the game board 5 from the back side is detachably mounted. The back mechanism plate 30 has an opening 30a formed on the top side thereof. A prize ball tank 33 and a tank rail 34 extending from the prize ball tank 33 are provided. Dispensing means 35 connected to the tank rail 34 is provided on the side of the back mechanism plate 30. A passage unit 36 connected to 35 is provided. The game balls paid out from the payout means 35 are paid out to the upper plate 8 from the upper plate discharge port 8a (FIG. 1) via the passage unit 36.

  The opening 30a of the back mechanism plate 30 is fitted with a back cover 37 mounted on the back side of the game board 5 and a winning ball discharge basket (not shown) for discharging the winning game balls to the winning means 17-19. Are combined. A main control board 39 is disposed inside a case 38 attached to the back cover 37, and a symbol control board 40 is disposed on the front side thereof (FIG. 2). Below the main control board 39, a lamp control board 42 is provided in a case 41a attached to the back cover 37, and a sound control board 43 is provided in a case 41b adjacent to the case 41a.

  A power supply board 45 and a payout control board 46 are provided inside the case 44 mounted on the back mechanism plate 30 below the cases 41a and 41b. As shown in FIG. 3, a power switch 80 and an initialization switch 85 are arranged on the power board 45. Cases 44 are notched at portions corresponding to these switches 80 and 85, and each of the switches 80 and 85 can be operated simultaneously with a finger.

  A launch control board 48 is provided inside the case 47 attached to the rear side of the launch means 10. These control boards 39 to 40, 42 to 43, 45 to 46, and 48 are independent boards, and the control boards 39, 40, 42, 43, and 46 excluding the power supply board 45 and the launch control board 48 have one chip. A computer circuit equipped with a microcomputer LE2080A (made by LE / Tech) is mounted, and the main control board 39 and the other control boards 40, 42, 43, 46 are electrically connected via a connector with a plurality of signal lines. It is connected to the. The one-chip microcomputer LE2080A used in this embodiment is constructed by incorporating a CPU, ROM, RAM, and other ICs equivalent to Z80 (Zilog).

  The main control board 39 and the other control boards 40, 42, 43, 46 are electrically connected via a connector with a plurality of signal lines, and each control board 40, 42, 43, 46 is connected from the main control board 39. In addition, various control commands for executing a predetermined game operation can be transmitted by one-way communication. By adopting the one-way communication of the control command, it is possible to reliably prevent fraud related to the symbol stop, to remarkably reduce the control load on the main control board 39, and to simplify the transmission control.

  FIG. 5 illustrates a circuit example of a reset signal generation unit for setting the Z80 CPU in the reset state in the main control board 39. A user reset signal URST and a system reset signal RST are output from this circuit. In either case, the value of the program counter PC is forcibly set to 0000H by setting the reset terminal of the Z80 CPU to the L level for a predetermined time. The program processing is returned to the initial state.

  As shown in FIG. 5, the reset signal generator includes a watchdog timer circuit 51 that operates in response to a timer clear signal from the CPU, a ripple counter RBC (for example, TC74HC4020AF), and a D-type flip-flop D-FF (for example, HD74HC74). And a system reset circuit 52 comprising: The system reset circuit 52 is supplied with a reset signal SYSRST from a power reset circuit (not shown) and a system clock XTAL.

The watchdog timer circuit 51 uses TA8030S (Toshiba) as the watchdog timer WDT. In this watchdog timer WDT, in a self-running state where no pulse signal is input to the clock terminal WD, the voltage of the TC terminal is repeatedly charged and discharged between 2V and 4V after the power is supplied to the IC. The reset signal RST having an H level period _TWD of 1.1 × C1 × R1 (ms) and an L level period _TRST of 0.75 × C1 (ms) is output. On the other hand, when a positive pulse is applied to the clock terminal WD, the charge is discharged even during charging toward 4V, and the charging operation starts again from 2V.

Therefore, in this pachinko machine, the RST terminal is always maintained at the H level by applying a timer clear signal to the clock terminal WD of the watchdog timer WDT at a predetermined time τ less than _TWD by software. Yes. In such a watchdog timer circuit 51, when the pachinko machine is operating normally, a timer clear signal is applied every predetermined time τ, so that the CPU is not reset, but due to a program runaway or the like In a situation where the timer clear signal from the CPU is interrupted, the reset signal RST of the watchdog timer WDT automatically falls after a certain time, and the Z80 CPU that has received the user reset signal URST is forcibly reset.

  FIG. 6 is a time chart for explaining the operation content of the system reset circuit 52 shown in FIG. When the power is turned on, a signal SYSRST from a power reset circuit (not shown) rises as shown in FIG. 6A (t1). Then, correspondingly, the clear terminal CLR of the ripple counter RBC becomes H level, and all the outputs of the RBC including Q5 and Q6 become L level. In response to the rising edge (t1) of the signal SYSRST, the clear terminal CLR of the D-type flip-flop D-FF falls, so that the Q output of the D-FF becomes L level.

  Thereafter, the signal SYSRST from the power reset circuit falls as shown in FIG. 6A (t2). Then, since the clear terminal CLR of the ripple counter RBC is also at the L level, the RBC starts counting the system clock XTAL. In response to the fall of the signal SYSRST (t2), the CLR terminal of the D-FF goes to the H level. Thereafter, when a signal is supplied to the clock terminal CK of the D flip-flop D-FF, The level D input will appear at the Q output terminal.

  After a certain time, as a result of the count operation of the ripple counter RBC, the Q5 output of the RBC becomes H level (t3). Then, in response to this, the system reset signal RST becomes H level as shown in FIG. Note that the system reset signal RST is at the L level during the period from t2 to t3 determined by the number of count stages of the ripple carry binary counter RBC, so that the Z80 CPU can be correctly reset.

  The subsequent operation will also be explained. The Q5 output of the ripple counter RBC eventually becomes L level, and the Q6 output of the RBC becomes H level in accordance with this (t4). Then, the Q output of the D-FF becomes H level corresponding to the rise of the Q6 output of the ripple counter RBC. When the clear terminal CLR of the ripple counter RBC becomes H level, all the outputs of the ripple counter RBC thereafter are maintained at L level.

  FIG. 7 is a flowchart showing a main routine of the game control program executed on the main control board 39. When the power is turned on, a reset signal is applied to the CPU core (Z80 equivalent product) of the one-chip microcomputer LE2080A by the operation of the system reset circuit 52 shown in FIG. 5, and the processing shown in FIG. 7 is started.

  In the main routine, first, the Z80 CPU sets itself to an interrupt disabled state (DI), and initializes each part of the one-chip microcomputer including the Z80 CPU core (ST1). There are two patterns when the power is turned on, such as when the initialization switch 85 is turned off and the power is turned on, such as when recovering from a power failure, and when the pachinko hall is opened. As described above, there are cases where the initialization switch 85 is in the ON state and the power supply is in the ON state. In either case, the process of step ST1 is executed.

  When the process of step ST1 is completed, the CPU next outputs a timer clear signal to the watchdog timer WDT (ST2). Therefore, the charging / discharging capacitor C1 of the watchdog timer WDT is always discharged at this timing, and there is no possibility that the CPU reset signal URST is output from the watchdog timer WDT at an unexpectedly early timing.

  Next, the CPU is set to interrupt mode 2 (ST2). Interrupt mode 2 is the most powerful interrupt mode among the three interrupt modes of Z80 (modes 0, 1, and 2). One-byte data stored in the I register in the CPU and This means an interrupt mode in which the CPU can branch to a maximum of 128 interrupt processing routines in combination with an interrupt vector (1 byte) acquired from the data bus by the CPU.

  After setting the interrupt mode 2, the CPU determines the value of the RAM clear signal (ST3). The RAM clear signal is a signal indicating whether or not the RAM area is set to an initial value, and has a value corresponding to the ON / OFF state of the initialization switch 85. Assuming that the pachinko hall is opened and the initialization switch 85 is turned on and the power is turned on, the determination in step ST3 is Yes, the RAM work area is initialized, and the other RAM areas are cleared to zero. (ST5). Then, the CPU is set to an interrupt permission state (EI) (ST5), and thereafter, random number generation processing is performed in an infinite loop (ST6). Note that the process of step ST6 is a process for determining what kind of out-of-game is to be produced when a disengaged state is obtained by a determination such as a jackpot determination process described later.

  On the other hand, when the initialization switch 85 is in the OFF state as in the recovery from the power failure state, the content of the backup flag BFL is determined following the determination in step ST3 (ST4). The backup flag BFL is data indicating whether or not the backup data at the time of the interruption operation saved in the NMI process is restored to the original state. In this embodiment, the backup flag BFL is processed in the process of step ST25. Is set to 5AH, and is cleared to zero in the process of step ST12.

  Assuming a recovery from a power failure state, the content of the backup flag BFL is 5AH. Therefore, the processing of the CPU shifts from step ST4 to step ST7, and 16-bit data read from the SP storage area of the RAM is written into the stack pointer SP of the CPU (ST7).

  Next, each data saved in the NMI process at the time of a power failure is read, and a process for restoring the backed up command is performed (ST8). Here, the command is a command transmitted from the main control board to each control board, and is used for exciting the game or paying out a prize ball by an image or sound. Create necessary commands by reading. Next, the CPU executes a POP instruction to restore the value of each register (BC, DE, HL) excluding the AF register from the stack area (ST9). When this process ends, the data in the SP storage area is cleared to zero (ST11). Note that the process of step ST11 is not necessarily essential technically, but is based on instruction from a public institution and is always executed.

  As a result of the above processing, the return processing from the power failure is completed for the time being, so the backup flag BFL is cleared to zero to indicate that (ST12). As described above, in this embodiment, the process of clearing the SP storage area data to zero (ST11) and the process of clearing the backup flag BFL to zero (ST12) are continuously executed. Although it has been cleared to zero, the possibility that the user reset signal URST is applied to the CPU in a state where the backup flag BFL has not been cleared to zero becomes extremely small, and there is almost no possibility of occurrence of an abnormal situation.

  That is, if the CPU is reset due to an unexpected malfunction of any circuit in the state where the data in the SP storage area is cleared to zero but the backup flag BFL is not cleared to zero, in the operation after reset, in step ST4 Next, since the process of step ST7 is performed, the stack pointer SP is set to 0000H.

  Then, in the subsequent return processing (POP instruction), frank data will be restored, and a game operation completely unrelated to that before the interruption is resumed, or the program runs out of control. End up. However, in the present embodiment, the process of clearing data in the SP storage area to zero (ST11) and the process of clearing the backup flag BFL to zero (ST12) are executed continuously, so that such a possibility is virtually zero. Become. Note that the clearing of the watchdog timer WDT at the timing of step ST2 also greatly contributes to the prevention of the above-described abnormal situation.

  As described above, this embodiment is characterized in that steps ST11 and ST12 are continuously executed. However, the data in the SP storage area is cleared to zero and the backup flag is returned even though the restoration of the AF register is not completed. BFL is cleared to zero because the processing of ST11 and ST12 can only use the A register, and if the processing of ST11 or ST12 is postponed, the data of the A register that has been restored is broken.

  Therefore, in this embodiment, the restoration processing of the I register and AF register is performed after the backup flag BFL is cleared to zero. Specifically, first, a POPAF instruction is executed to restore the contents of the I register to the F register (ST13). In the NMI interrupt processing program, the value of the A register is pushed after the value of the I register is loaded into the A register (see FIG. 8C), so that the POP instruction causes the P / V flag of the F register to be set. Stores the value of the interrupt permission flip-flop IFF in the CPU.

  Here, when the P / V flag is 1, the CPU at the time of NMI processing is in an interrupt enabled state. Conversely, when the P / V flag is 0, the CPU at the time of NMI processing is prohibited from interrupting. It was in a state. Therefore, if the P / V flag is 0, the POP instruction is executed again to restore the value of the AF register, and the RET instruction is executed with the interrupt disabled state (ST15, ST16). On the other hand, if the P / V flag is 1, the POP instruction is executed again to restore the value of the AF register, and the RET instruction is executed after changing to the interrupt enabled state (ST17 to ST19). In any case, when the RET instruction is executed, the value of the PC (program counter) at the time of the PUSH processing being restored in the stack area is restored, and the processing suspended due to a power failure or the like is resumed. Become.

  By the way, if the CPU reset signal URST is issued from the watchdog timer WDT after the process of step ST12 is completed, the process of the CPU after the reset is shifted from step ST4 to step ST5. The game operation that was interrupted can no longer be resumed. However, in this pachinko machine, since the watchdog timer WDT is cleared immediately after the CPU is reset (ST2), there is very little possibility that the CPU is reset unnecessarily.

In order to further eliminate the possibility that the CPU will be reset, as shown by the broken line in FIG. 7, the watchdog at the timing of step ST10 prior to the process (ST11, 12) indicating the completion of the recovery process from the power failure. A timer clear signal may be output to the timer WDT. In this case, since the same processing is performed instead of (or in addition to) the timing of step ST2, even if the interrupt disabled state is prolonged even after execution of the RET instruction, the watchdog timer WDT The reset signal URST is not applied to the CPU. Also, (to reduce the constant C1 × R1 when specifically) watchdog timer to set a short H-level period T _WD reset output the WDT in the free-running state, even if faster response when program runaway, Troubles associated with it do not occur.

  FIG. 8 is a flowchart showing the contents of an NMI interrupt processing program that occurs when the power supply voltage drops due to a power failure or the like. In this interrupt processing, first, the contents of each register (AF, I, BC, DE, HL) are pushed to the stack area (ST20). However, since the value of the I register cannot be pushed directly to the stack area, it is substituted by executing the instruction of PUSH AF after executing the instruction of LDA, I.

  Next, the contents of the storage area of the backup flag BFL shown in FIG. 8B are checked, and the contents of the SP storage area are checked (ST21). As described with reference to steps ST11 and ST12 in FIG. 7, when the NMI interrupt returns normally, the contents of the backup flag BFL and the SP storage area should be zero. Therefore, in the determination of step ST21, the case where the condition that both are zero is not satisfied means that an NMI interrupt has occurred again during the NMI interrupt recovery process (ST1 to ST10).

  In such a case, even if the process proceeds to the processing after step ST22, the value before the power failure cannot be restored because the value of the stack pointer SP at the time of the NMI interruption is destroyed in step ST22. Therefore, in this embodiment, when the power supply voltage drops again and an NMI interrupt occurs again during the NMI interrupt recovery process (ST1 to ST10), the process is shifted to address 0000H. I have to. By responding in this way, the process of the main routine proceeds from step ST1 to step ST4, and further proceeds to step ST7, whereby the process before the interruption can be restored.

  By the way, when the contents of the backup flag BFL and the SP storage area are both zero, the process moves from step ST21 to step ST22, and the value of the stack pointer SP after execution of the PUSH instruction in step ST20 is the SP of the RAM. It is stored in the storage area (ST22). FIGS. 8B and 8C illustrate the saving state of each register (AF, I, BC, DE, HL), stack pointer SP, and program counter PC.

  Subsequently, since there is a case where a prize ball is currently being paid out, the state of the prize ball counting switch is detected and stored (ST23). Note that waiting for a predetermined time (ST24) takes into account the time for which the prize ball being paid out moves. Although not shown, after the necessary data is backed up, the flag value 5AH is stored in the RAM area of the backup flag BFL (ST25). Thereafter, the access to the RAM is prohibited and the power supply voltage drops and the CPU Waiting for a non-operation state (ST26). After that, the CPU becomes non-operating, but since the backup power is supplied to the RAM, the backed up data continues to be stored as it is. That is, even after the power supply is completely shut down, the RAM area is maintained as shown in FIGS.

  FIG. 9 is a flowchart showing the contents of an interrupt processing program of a timer interrupt INT (Maskable Interrupt disableable interrupt) that occurs every 2 msec during the infinite loop processing (ST6) of the main routine (FIG. 7). When a timer interrupt occurs, the contents of each register are saved in the stack area, and random number generation processing, switch input management processing, error management processing, and the like are performed (ST30). The switch input management process is a determination as to whether or not a game ball has passed through a gate or an electric tulip, and the error management process is a determination as to whether an abnormality has occurred inside the device. The random number generation process means a process for acquiring a hit random number value or a jackpot random value that is updated in hardware.

  Thereafter, the value of the process division counter is determined, and the corresponding process from ST32 to ST36 is performed. The above error management and switch management should be repeated at short time intervals. On the other hand, the processing related to the pachinko game production is complicated and sophisticated according to the player's needs, and therefore requires a certain amount of processing time. It will be. Therefore, in this embodiment, not all the game control operations are completed by one interrupt process, but are divided into five types of processes, and each divided process is divided and executed for each interrupt. Yes. Therefore, a processing division counter that circulates in the range of 0 to 4 is provided to perform processing according to the value of the processing division counter.

  More specifically, when the processing division counter is 0, processing relating to the opening of the big prize opening is performed (ST32), and when the processing division counter is 1, whether the winning state (electric tulip is open) or not. Normal symbol processing is performed (ST32), and when the processing division counter is 2, processing relating to whether or not a big hit state is performed (ST32). If the processing division counter is 3, timer management processing related to the opening / closing timing of the electric tulip and the big prize opening and command creation processing transmitted from the main control board to each control board are performed (ST35). If the process division counter is 4, information output and error display command creation processing is performed (ST36). Thereafter, a timer clear signal is output to the watchdog timer WDT (ST37).

  Since the process of step ST37 is executed in the fifth interrupt process, the timer clear signal generation cycle in step ST37 is normally 2 msec × 5. However, when the power supply is restored after an NMI interrupt occurs, the processing of the main routine (FIG. 7) is further added, so that a timer clear signal longer than 2 msec × 5 is not generated. However, in this embodiment, since the timer clear signal is output to the watchdog timer WDT at least once during the processing of steps ST1 to ST19, the CPU is reset without meaning after recovery from a power failure or the like. There is no negative effect that the process cannot be resumed.

  When any one of steps ST32 to ST36 is completed, the value of the process division counter is updated (ST39), and the generated command is transmitted to each control board (ST40). Further, the value of each register is restored and changed to the interrupt enabled state, and the routine returns from the interrupt processing routine to the main routine (ST40). As indicated by the broken line in FIG. 9, a timer clear signal may be output to the watchdog timer WDT for each interrupt (ST38). In this case, the time until the charge / discharge capacitor C1 is completely charged is further increased. By setting it short, it becomes possible to detect a program runaway more quickly and to reset the CPU.

  Although one embodiment of the present invention has been described above, the specific technical contents do not particularly limit the present invention. For example, it is also preferable to reverse the processing order of step ST11 and step ST12 described in FIG. That is, in such an embodiment, in any case, the CPU is not reset in a state where the backup flag is not cleared to zero even though the SP storage area is cleared to zero. At worst, the CPU is reset in a state where the SP storage area is not cleared to zero even though the backup flag is cleared to zero. Even in this worst case, since the backup flag is cleared to zero, after the process of step ST4, the process proceeds to the process of step ST5 and the reset process is correctly performed.

It is a perspective view of the pachinko machine concerning an example. It is a side view of the pachinko machine of FIG. It is a front view of the pachinko machine of FIG. It is a rear view of the pachinko machine of FIG. It is a circuit example of a watchdog timer circuit and a system reset circuit. It is a time chart explaining circuit operation of a system reset circuit. It is a flowchart of the main routine of the game control program which concerns on an Example. It is a flowchart of the NMI interruption processing program implemented at the time of a power failure. It is a flowchart of the INT interruption processing program in the timer interruption.

Explanation of symbols

WDT reset means (watchdog timer)
2 Pachislot machines (pachinko machines)
ST6 Infinite loop processing ST1 to ST19 First processing ST30 to ST41 Second processing ST20 to ST26 Third processing ST11 SP storage area clear processing ST12 Backup flag reset processing ST22 Processing to save SP value in SP storage area ST25 Backup flag Process to set

Claims (2)

A gaming machine having a CPU for controlling a gaming operation based on a control program and capable of selectively selecting a first state advantageous to a player and a second state disadvantageous to the player, wherein the control program When normal processing is not performed according to the above, the reset means functions to forcibly return the game operation to the initial state,
The control program is started in response to power-on, and includes a first process configured to include an infinite loop process , and a first process that is started by interrupting the first process every predetermined time, and controls a game operation repeatedly. second processing and the power supply voltage is started to force the falls below a predetermined level, and a third process of performing data saving process to save area,
In the third process, after the data saving process, the value of the stack pointer is saved in the specific storage area and the predetermined flag is set to the second state,
In the first process, on the condition that the predetermined flag is in the second state, the value of the stack pointer is set based on the saved contents of the specific storage area, and then the data saved in the save area is stored. A data restoration process is started, and then a clear process for rewriting the saved contents of the specific storage area is performed together with a reset process for setting the predetermined flag to the first state,
The reset process and the clear process are executed successively, and the save destination of the save area in the data save process and the return source of the save area in the data return process are specified by the stack pointer.
A gaming machine that has become . It has a Z80 CPU for controlling the gaming operation based on the control program, and a second state disadvantageous to a preferred first state and the player to the player a alternatively selectable gaming machine, the control When normal processing is not performed according to the program, the reset means functions to force the game operation to return to the initial state,
The control program is started in response to power-on, and includes a first process configured to include an infinite loop process , and a first process that is started by interrupting the first process every predetermined time, and controls a game operation repeatedly. second processing and the power supply voltage is started to force the falls below a predetermined level, and a third process of performing data saving process to save area,
In the third process, after the data saving process, the value of the stack pointer is saved in the specific storage area and the predetermined flag is set to the second state,
In the first process, on the condition that the predetermined flag is in the second state, the value of the stack pointer is set based on the saved contents of the specific storage area, and then the data saved in the save area is stored. A data recovery process is started, and then a reset process is executed to set the flag to the first state,
The save destination of the save area in the data save process and the return source of the save area in the data return process are specified by the stack pointer,
In the data saving process, a first process for saving the value of the AF register of the Z80 CPU, and a second process for saving the value of the AF register after transferring the value of the I register of the Z80 CPU to the A register of the AF register. And in this order,
In the data restoration process, the data is restored in the reverse order of the save process, thereby specifying whether or not the Z80 CPU is in an interrupt enabled state and restoring the value of the AF register saved in the first process. A gaming machine characterized by doing so .

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