JP4206098B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more particularly to a gaming machine in which a CPU is not reset meaninglessly even though a program is normally executed.

  In a game machine with a built-in microcomputer such as a pachinko machine, Z80 (ZILOG) or its equivalent is preferably used as the CPU. Further, such a gaming machine is provided with a watch dog timer WDT, and is configured so that the CPU automatically returns to the reset state when the program runs away.

FIG. 8 is a circuit example when TA8030S (Toshiba) is used as the watchdog timer WDT. In a self-running state in which no pulse signal is input to the clock terminal WD of the watchdog timer WDT, the voltage at the TC terminal is repeatedly charged and discharged between 2V and 4V after the power is supplied to the IC. A reset signal RST having an H level period _TWD of 1.1 × C1 × R1 (ms) and an L level period _TRST of 0.75 × C1 (ms) is output. On the other hand, when a positive pulse is applied to the clock terminal WD, the charge is discharged even during charging toward 4V, and the charging operation starts again from 2V.

Therefore, in the pachinko machine, the RST terminal is constantly maintained at the H level by applying a timer clear signal to the clock terminal WD of the watchdog timer WDT at a predetermined time τ less than _TWD by software. . In such a circuit, when the pachinko machine is operating normally, a timer clear signal is applied every predetermined time τ, so that the CPU is not reset, but from the CPU side due to a program runaway or the like. In a situation where the timer clear signal is interrupted, the reset signal RST of the watchdog timer WDT automatically falls after a certain time, and the CPU that has received the CPU reset signal URST is forcibly reset.

  However, with such a pachinko machine, the CPU may be in a reset state even though the program is executed normally.

  Specifically, when the power supply voltage drops due to a power failure or the like, an NMI (Non Maskable Interrupt) is added to the CPU, and when a data backup (backup) process is performed in the subsequent interrupt processing program, for example, If the power supply voltage is recovered immediately thereafter, the operation of the watchdog timer WDT is started while the capacitor C1 shown in FIG. 8 is charged. Note that the charged state of the capacitor C1 may also occur when the power supply voltage is interrupted and turned on instantaneously.

  In such a case, since the operation of the watchdog timer WDT is started while the capacitor C1 is charged, the CPU reset signal URST is output within a short time after the operation of the watchdog timer WDT is started. . For this reason, after the power is restored, a flag indicating that the backup data restoration processing has been completed is set after completing the temporary processing, but the CPU forcibly cancels the program processing in a state where it has not completely returned to the processing before the interruption. There was a risk of being reset. In particular, if the pachinko machine before the power outage was in a big hit state, if the power is restored and the big hit game is not reproduced normally and the CPU is reset, then the big hit state will disappear, so the player It will also cause unnecessary troubles.

  Note that such trouble is caused even when the capacitor C1 is in a discharged state at the start of the operation of the watchdog timer WDT, and after the power supply is restored, the CPU is in an interrupt enabled state after the predetermined processing is completed, and then the timer clear signal is generated. Can also occur if the time is longer than usual.

  The present invention has been made in view of these problems, and it is an object of the present invention to provide a gaming machine that prevents a CPU that normally executes a program from entering a reset state without meaning. .

In order to solve the above-described problems, the present invention has a program storage means that stores a control program for a game operation, and a CPU that controls the game operation based on the control program. Game control means that can alternatively select a first state that is advantageous to the player and a second state that is disadvantageous to the player, and when normal processing is not performed according to the control program, a predetermined time A game machine in which the reset means functions by the time counting of the game machine so as to forcibly return the game operation to the initial state, and the control program is started in response to power-on and normally ends in an infinite loop process. 1 process, a second process that is repeatedly executed every predetermined time (T), and a third process that is forcibly started when the power supply voltage falls below a normal level. The first process includes the reset means Contains clear process of returning the operation to the initial state, the third process, prior to interrupt the game operation, saves the data needed to resume the interrupted game operation, then the flag in the memory of the first data When the power supply voltage is restored to a normal level, a restoration process for restoring the saved data is executed in the first process on condition that the first data is stored in the flag. Thereafter, the flag is changed to the second data, and the clear process is executed prior to the change to the second data.

  In the present invention, since the operation of the reset means is returned to the initial state in the first process that is started in response to power-on, the process interrupted due to a power failure or the like regardless of the operation state of the circuit element. Even during resumption, it is extremely difficult to cause a trouble that the game operation is forcibly returned to the initial state.

  As described above, according to the present invention, it is possible to realize a gaming machine that prevents a CPU that normally executes a program from entering a reset state without meaning.

  Hereinafter, an embodiment of the present invention will be described based on a card-type ball game machine which is an embodiment of the present invention. FIG. 1 is a perspective view showing a pachinko machine 2 according to the present embodiment, and FIG. 2 is a side view of the pachinko machine 2.

  The pachinko machine 2 shown in FIG. 1 is a rectangular frame-shaped wooden outer frame 3 that is detachably mounted on the island structure and a hinge H that is fixed to the outer frame 3 before being pivotably mounted. It consists of a frame 4. A plurality of pachinko machines 2 are arranged in the length direction of the island structure of the pachinko hall while being electrically connected to the card-type ball lending machine 1.

  A game board 5 is detachably attached from the back side to the front frame 4 pivotally attached to the outer frame 3 via a hinge H, and a glass door 6 having a window portion and a front side corresponding to the front side of the game board 5. A face plate 7 is pivotally attached to each other so as to be freely opened and closed. The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and launching means 10 at the lower part of the front frame 4. And a firing handle 11 are provided.

  The launching means 10 includes a launching handle 11 that can be rotated, and a launching motor that launches a game ball with a striking rod 12 (FIG. 4) with a striking force corresponding to the pivoting angle of the launching handle 11. . On the right side of the upper plate 8, there is provided an operation panel 13 for a ball lending operation for the card-type ball lending machine 1, and on this operation panel 13, a card remaining amount display portion 13a for displaying the remaining amount of the card with a three-digit number. And a ball lending switch 13b for instructing lending of game balls for a predetermined amount, and a return switch 13c for instructing to return the card at the end of the game.

  As shown in FIG. 3, the game board 5 is provided with a guide rail 15 made of a metal outer rail and an inner rail in a substantially annular shape, and a color liquid crystal is provided in the game area 5 a inside the guide rail 15. Display 16, symbol starting means (symbol starting and winning means) 17, open / close type winning means (large winning means) 18, a plurality of normal winning means 19 (in addition to the upper normal winning means 19, both the left and right sides of the opening / closing type winning means 18 Six normal winning means 19) and two gates 20 (passage openings) are arranged at predetermined positions.

  The liquid crystal display 16 functions as a first symbol display means 22 that displays a changing symbol and also displays a background image, moving images of various characters, and the like. The first symbol display means 22 displays background images and characters in an animated manner, and has three (left, middle, and right) symbol display portions 22a to 22c arranged in the left-right direction. On the condition that the ball wins, the display symbols of the symbol display units 22a to 22c are variably displayed (scrolled) for a predetermined time, and based on the lottery result corresponding to the winning timing of the game ball to the symbol starting means 17. Stop at the determined stop symbol pattern.

  A normal winning means 19 and a second symbol display means 23 are provided immediately above the liquid crystal display 16. The second symbol display means 23 has a normal symbol display unit for displaying one normal symbol. When a game ball that has passed through the gate 20 is detected, the display symbol of the normal symbol display unit fluctuates for a predetermined time, A stop symbol determined by a random number for lottery drawn at the time the game ball passes through the gate 20 is displayed and stopped. The symbol starting means 17 is an electric tulip having a pair of left and right opening and closing claws 17a that can be freely opened and closed. It is easy to win a prize by opening for a predetermined time.

  The open / close-type winning means 18 includes an opening / closing plate 18a that can be opened forward, and when the stop symbol after the fluctuation of the first symbol display means 22 is a winning symbol such as “777”, a special game called “big hit” is started. The opening / closing plate 18a is opened to the front side. There is a specific area 18b inside the openable winning means 18, and when the winning ball passes through the specific area 18b, the special game is continued. Here, the special game state corresponds to a state advantageous to the player.

  After the opening / closing plate 18a of the open / close winning means 18 is opened, when a predetermined time elapses, or when a predetermined number (for example, 10) of gaming balls wins and the opening / closing plate 18a is closed, the gaming ball is in the specific area 18b. If it has not passed, the special game ends. However, if it has passed the specific area 18b, the special game is continued up to, for example, 16 times, and is controlled in a state advantageous to the player.

  As shown in FIG. 4, on the back side of the front frame 4, a back mechanism plate 30 that presses the game board 5 from the back side is detachably mounted. The back mechanism plate 30 has an opening 30a formed on the top side thereof. A prize ball tank 33 and a tank rail 34 extending from the prize ball tank 33 are provided. Dispensing means 35 connected to the tank rail 34 is provided on the side of the back mechanism plate 30. A passage unit 36 connected to 35 is provided. The game balls paid out from the payout means 35 are paid out to the upper plate 8 from the upper plate discharge port 8a (FIG. 1) via the passage unit 36.

  The opening 30a of the back mechanism plate 30 is fitted with a back cover 37 mounted on the back side of the game board 5 and a winning ball discharge basket (not shown) for discharging the winning game balls to the winning means 17-19. Are combined. A main control board 39 is disposed inside a case 38 attached to the back cover 37, and a symbol control board 40 is disposed on the front side thereof (FIG. 2). Below the main control board 39, a lamp control board 42 is provided in a case 41a attached to the back cover 37, and a sound control board 43 is provided in a case 41b adjacent to the case 41a.

  A power supply board 45 and a payout control board 46 are provided inside the case 44 mounted on the back mechanism plate 30 below the cases 41a and 41b. As shown in FIG. 3, a power switch 80 and an initialization switch 85 are arranged on the power board 45. Cases 44 are notched at portions corresponding to these switches 80 and 85, and each of the switches 80 and 85 can be operated simultaneously with a finger.

  A launch control board 48 is provided inside the case 47 attached to the rear side of the launch means 10. These control boards 39 to 40, 42 to 43, 45 to 46, and 48 are independent boards, and the control boards 39, 40, 42, 43, and 46 excluding the power supply board 45 and the launch control board 48 have one chip. A computer circuit equipped with a microcomputer LE2080A (made by LE / Tech) is mounted, and the main control board 39 and the other control boards 40, 42, 43, 46 are electrically connected via a connector with a plurality of signal lines. It is connected to the. The one-chip microcomputer LE2080A used in this embodiment is constructed by incorporating a CPU, ROM, RAM, and other ICs equivalent to Z80 (Zilog).

  The main control board 39 and the other control boards 40, 42, 43, 46 are electrically connected via a connector with a plurality of signal lines, and each control board 40, 42, 43, 46 is connected from the main control board 39. In addition, various control commands for executing a predetermined game operation can be transmitted by one-way communication. By adopting the one-way communication of the control command, it is possible to reliably prevent fraud related to the symbol stop, to remarkably reduce the control load on the main control board 39, and to simplify the transmission control.

  FIG. 5 is a flowchart showing a main routine of the game control program executed on the main control board 39. When the power is turned on, a reset signal is applied to the CPU core (Z80 equivalent) of the one-chip microcomputer LE2080A by the operation of a power reset circuit (not shown), and the processing shown in FIG. 5 is started.

  In the main routine, first, the Z80 CPU sets itself to an interrupt disabled state (DI), and initializes each part of the one-chip microcomputer including the Z80 CPU core (ST1). There are two patterns when the power is turned on, such as when the initialization switch 85 is turned off and the power is turned on, such as when recovering from a power failure, and when the pachinko hall is opened. As described above, there are cases where the initialization switch 85 is in the ON state and the power supply is in the ON state. In either case, the process of step ST1 is executed.

  When the process of step ST1 is completed, the CPU next outputs a timer clear signal to the watchdog timer WDT (ST2). Therefore, the charging / discharging capacitor C1 of the watchdog timer WDT is always discharged at this timing, and there is no possibility that the CPU reset signal URST is output from the watchdog timer WDT at an unexpectedly early timing.

  Next, the CPU is set to interrupt mode 2 (ST2). Interrupt mode 2 is the most powerful interrupt mode among the three interrupt modes of Z80 (modes 0, 1, and 2). One-byte data stored in the I register in the CPU and This means an interrupt mode in which the CPU can branch to a maximum of 128 interrupt processing routines in combination with an interrupt vector (1 byte) acquired from the data bus by the CPU.

  After setting the interrupt mode 2, the CPU determines the value of the RAM clear signal (ST3). The RAM clear signal is a signal indicating whether or not the RAM area is set to an initial value, and has a value corresponding to the ON / OFF state of the initialization switch 85. Assuming that the pachinko hall is opened and the initialization switch 85 is turned on and the power is turned on, the determination in step ST3 is Yes, the RAM work area is initialized, and the other RAM areas are cleared to zero. (ST5). Then, the CPU is set to an interrupt permission state (EI) (ST5), and thereafter, random number generation processing is performed in an infinite loop (ST6). Note that the process of step ST6 is a process for determining what kind of out-of-game is to be produced when a disengaged state is obtained by a determination such as a jackpot determination process described later.

  On the other hand, when the initialization switch 85 is in the OFF state as in the recovery from the power failure state, the content of the backup flag BFL is determined following the determination in step ST3 (ST4). The backup flag BFL is data indicating whether or not the backup data at the time of the interruption operation saved in the NMI process is restored to the original state. In this embodiment, the backup flag BFL is processed in the process of step ST23. Is set to 5AH, and is cleared to zero in the process of step ST12.

  Assuming a recovery from a power failure state, the content of the backup flag BFL is 5AH. Therefore, the processing of the CPU shifts from step ST4 to step ST7, and 16-bit data read from the SP storage area of the RAM is written into the stack pointer SP of the CPU (ST7).

  Next, each data saved in the NMI process at the time of a power failure is read, and a process for restoring the backed up command is performed (ST8). Here, the command is a command transmitted from the main control board to each control board, and is used for exciting the game or paying out a prize ball by an image or sound. The CPU creates necessary commands by reading the saved data. Next, the CPU executes a POP instruction to restore the value of each register (BC, DE, HL) excluding the AF register from the stack area (ST9). When this process ends, the data in the SP storage area is cleared to zero (ST11). The process of step ST11 is not technically essential, but is based on instruction from a public institution and is always executed.

  As a result of the above processing, the return processing from the power failure is completed for the time being, so the backup flag BFL is cleared to zero to indicate that (ST12). Note that the process of ST11 and ST12 only uses the A register to clear the data in the SP storage area to zero and clear the backup flag BFL to zero even though the restoration of the AF register has not been completed. This is because if the processing of ST12 is postponed, the data of the A register that has been restored is broken.

  As described above, in this embodiment, after the backup flag BFL is cleared to zero, the restoration process of the I register and the AF register is performed. Specifically, first, a POPAF instruction is executed to restore the contents of the I register to the F register (ST13). Since the NMI interrupt processing program loads the value of the I register into the A register and pushes the value of the A register (see FIG. 2C), the POP instruction causes the P / V flag of the F register to be set. Stores the value of the interrupt permission flip-flop IFF in the CPU.

  Here, when the P / V flag is 1, the CPU at the time of NMI processing is in an interrupt enabled state. Conversely, when the P / V flag is 0, the CPU at the time of NMI processing is prohibited from interrupting. It was in a state. Therefore, if the P / V flag is 0, the POP instruction is executed again to restore the value of the AF register, and the RET instruction is executed with the interrupt disabled state (ST15, ST16). On the other hand, if the P / V flag is 1, the POP instruction is executed again to restore the value of the AF register, and the RET instruction is executed after changing to the interrupt enabled state (ST17 to ST19). In any case, when the RET instruction is executed, the value of the PC (program counter) at the time of the PUSH processing being restored in the stack area is restored, and the processing suspended due to a power failure or the like is resumed. Become.

  By the way, if the CPU reset signal URST is issued from the watchdog timer WDT after the process of step ST12 is completed, the process of the CPU after the reset is shifted from step ST4 to step ST5. The game operation that was interrupted can no longer be resumed. However, in this pachinko machine, since the watchdog timer WDT is cleared immediately after the CPU is reset (ST2), there is very little possibility that the CPU is reset unnecessarily.

In order to further eliminate the possibility of the CPU being reset, as shown by a broken line in FIG. 1, the watchdog is detected at the timing of step ST10 prior to the process (ST11, 12) indicating the completion of the recovery process from the power failure. A timer clear signal may be output to the timer WDT. In this case, since the same processing is performed instead of (or in addition to) the timing of step ST2, even if the interrupt disabled state is prolonged even after execution of the RET instruction, the watchdog timer WDT The reset signal URST is not applied to the CPU. Also, (to reduce the constant C1 × R1 when specifically) watchdog timer to set a short H-level period T _WD reset output the WDT in the free-running state, even if faster response when program runaway, Troubles associated with it do not occur.

  FIG. 6 is a flowchart showing the contents of an NMI interrupt processing program that occurs when the power supply voltage drops due to a power failure or the like. In this interrupt processing, first, the contents of each register (AF, I, BC, DE, HL) are pushed to the stack area (ST20). However, since the value of the I register cannot be pushed directly to the stack area, it is substituted by executing the instruction of PUSH AF after executing the instruction of LDA, I. Next, the value of the stack pointer SP after the execution of the PUSH instruction is stored in the SP storage area of the RAM. FIGS. 6B and 6C show the saving state of each register (AF, I, BC, DE, HL), stack pointer SP, and program counter PC.

  Subsequently, since there is a case where a prize ball is currently being paid out, the state of the prize ball counting switch is detected and stored (ST21). Note that waiting for a time of 210 msec (ST22) takes into account the time during which the prize ball being paid out moves. Although not shown, after the necessary data is backed up, the flag value 5AH is stored in the RAM area of the backup flag BFL (ST23). Thereafter, the access to the RAM is prohibited and the power supply voltage drops and the CPU Waiting for a non-operation state (ST24). After that, the CPU becomes non-operating, but since the backup power is supplied to the RAM, the backed up data continues to be stored as it is. That is, even after the power supply is completely shut down, the RAM area is maintained as shown in FIGS.

  FIG. 7 is a flowchart showing the contents of the interrupt processing program of the timer interrupt INT (Maskable Interrupt disabled interrupt) that occurs every 2 msec during the infinite loop processing (ST6) of the main routine (FIG. 5). When a timer interrupt occurs, the contents of each register are saved in the stack area, and random number generation processing, switch input management processing, error management processing, and the like are performed (ST30). The switch input management process is a determination as to whether or not a game ball has passed through a gate or an electric tulip, and the error management process is a determination as to whether an abnormality has occurred inside the device. The random number generation process means a process for acquiring a hit random number value or a jackpot random value that is updated in hardware.

  Thereafter, the value of the process division counter is determined, and the corresponding process from ST32 to ST36 is performed. The above error management and switch management should be repeated at short time intervals. On the other hand, the processing related to the pachinko game production is complicated and sophisticated according to the player's needs, and therefore requires a certain amount of processing time. It will be. Therefore, in this embodiment, not all the game control operations are completed by one interrupt process, but are divided into five types of processes, and each divided process is divided and executed for each interrupt. Yes. Therefore, a processing division counter that circulates in the range of 0 to 4 is provided to perform processing according to the value of the processing division counter.

  More specifically, when the processing division counter is 0, processing relating to the opening of the big prize opening is performed (ST32), and when the processing division counter is 1, whether the winning state (electric tulip is open) or not. Normal symbol processing is performed (ST32), and when the processing division counter is 2, processing relating to whether or not a big hit state is performed (ST32). If the processing division counter is 3, timer management processing related to the opening / closing timing of the electric tulip and the big prize opening and command creation processing transmitted from the main control board to each control board are performed (ST35). If the process division counter is 4, information output and error display command creation processing is performed (ST36). Thereafter, a timer clear signal is output to the watchdog timer WDT (ST37).

  Since the process of step ST37 is executed in the fifth interrupt process, the timer clear signal generation cycle in step ST37 is normally 2 msec × 5. However, when the power supply is restored after an NMI interruption occurs, the processing of the main routine (FIG. 5) is further added, so that a timer clear signal longer than 2 msec × 5 is not generated. However, in this embodiment, since the timer clear signal is output to the watchdog timer WDT at least once during the processing of steps ST1 to ST19, the CPU is reset without meaning after recovery from a power failure or the like. There is no negative effect that the process cannot be resumed.

  When any one of steps ST32 to ST36 is completed, the value of the process division counter is updated (ST39), and the generated command is transmitted to each control board (ST40). Further, the value of each register is restored and changed to the interrupt enabled state, and the routine returns from the interrupt processing routine to the main routine (ST40). As indicated by the broken line in FIG. 7, a timer clear signal may be output to the watchdog timer WDT for each interrupt (ST38). In this case, the time until the charging / discharging capacitor C1 is completely charged is further increased. By setting it short, it becomes possible to detect a program runaway more quickly and to reset the CPU.

It is a perspective view of the pachinko machine concerning an example. It is a side view of the pachinko machine of FIG. It is a front view of the pachinko machine of FIG. It is a rear view of the pachinko machine of FIG. It is a flowchart of the main routine of the game control program which concerns on an Example. It is a flowchart of the NMI interruption processing program implemented at the time of a power failure. It is a flowchart of the INT interruption processing program in the timer interruption. It is an example of a circuit of the reset means using a watchdog timer.

Explanation of symbols

WDT reset means (watchdog timer)
2 Pachislot machines (pachinko machines)
ST6 Infinite loop processing ST1 to ST19 First processing ST30 to ST41 Second processing

Claims (6)

It has a program storage means for storing a control program for a game operation and a CPU for controlling the game operation based on this control program, and is disadvantageous to the player in the first state advantageous to the player in relation to the game. A game control means capable of selectively selecting the second state, and when the normal processing is not performed according to the control program, the reset means functions according to a predetermined time to perform the game operation. A gaming machine that is forced to return to its initial state,
The control program starts when the power is turned on and normally ends with an infinite loop process . When the power supply voltage falls below the normal level, the second process is repeatedly executed every predetermined time (T). A third process forcibly started , and the first process includes a clear process for returning the operation of the reset means to an initial state.
In the third process, prior to interrupting the gaming operation, data necessary for resuming the interrupted gaming operation is saved, and then the first data is stored in the flag.
When the power supply voltage is restored to a normal level, a restoration process for restoring the saved data is executed in the first process on condition that the first data is stored in the flag. , The flag is changed to the second data,
The gaming machine , wherein the clearing process is executed prior to the change to the second data . 2. The gaming machine according to claim 1, wherein the resetting unit determines whether or not a normal gaming operation is realized depending on whether or not the control program executes a clear process within a predetermined time. . The clear processing, the gaming machine according to claim 1 or 2 is performed quickly in response to power-on. The second process includes a common process executed every time the predetermined time (T), and a total of N types of division processes executed at a time (NT) interval N times the predetermined time, The gaming machine according to any one of claims 1 to 3, wherein a series of processing is completed after NT. The gaming machine according to claim 4 , wherein the clear process for returning the operation of the reset means to the initial state is executed in any one of the sorting processes. The gaming machine according to claim 4 , wherein the clear process for returning the operation of the reset means to the initial state is also executed in the common process.

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