JP2006166430A5 - - Google Patents

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Publication number
JP2006166430A5
JP2006166430A5 JP2005336979A JP2005336979A JP2006166430A5 JP 2006166430 A5 JP2006166430 A5 JP 2006166430A5 JP 2005336979 A JP2005336979 A JP 2005336979A JP 2005336979 A JP2005336979 A JP 2005336979A JP 2006166430 A5 JP2006166430 A5 JP 2006166430A5
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Japan
Prior art keywords
block
programmable logic
integrated circuit
power
reset
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JP2005336979A
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Japanese (ja)
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JP4249745B2 (ja
JP2006166430A (ja
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Priority claimed from US11/003,586 external-priority patent/US7242218B2/en
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Publication of JP2006166430A5 publication Critical patent/JP2006166430A5/ja
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Publication of JP4249745B2 publication Critical patent/JP4249745B2/ja
Anticipated expiration legal-status Critical
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JP2005336979A 2004-12-02 2005-11-22 集積回路上で揮発性と不揮発性プログラム可能ロジックを結合させるための技術 Expired - Fee Related JP4249745B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/003,586 US7242218B2 (en) 2004-12-02 2004-12-02 Techniques for combining volatile and non-volatile programmable logic on an integrated circuit

Publications (3)

Publication Number Publication Date
JP2006166430A JP2006166430A (ja) 2006-06-22
JP2006166430A5 true JP2006166430A5 (cg-RX-API-DMAC7.html) 2008-12-11
JP4249745B2 JP4249745B2 (ja) 2009-04-08

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JP2005336979A Expired - Fee Related JP4249745B2 (ja) 2004-12-02 2005-11-22 集積回路上で揮発性と不揮発性プログラム可能ロジックを結合させるための技術

Country Status (4)

Country Link
US (1) US7242218B2 (cg-RX-API-DMAC7.html)
EP (1) EP1667327A3 (cg-RX-API-DMAC7.html)
JP (1) JP4249745B2 (cg-RX-API-DMAC7.html)
CN (1) CN1815628B (cg-RX-API-DMAC7.html)

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