JP2006130353A5 - - Google Patents

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Publication number
JP2006130353A5
JP2006130353A5 JP2006042832A JP2006042832A JP2006130353A5 JP 2006130353 A5 JP2006130353 A5 JP 2006130353A5 JP 2006042832 A JP2006042832 A JP 2006042832A JP 2006042832 A JP2006042832 A JP 2006042832A JP 2006130353 A5 JP2006130353 A5 JP 2006130353A5
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JP
Japan
Prior art keywords
processing
power
time
flag
nmi
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JP2006042832A
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Japanese (ja)
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JP2006130353A (en
JP4085145B2 (en
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Priority to JP2006042832A priority Critical patent/JP4085145B2/en
Priority claimed from JP2006042832A external-priority patent/JP4085145B2/en
Publication of JP2006130353A publication Critical patent/JP2006130353A/en
Publication of JP2006130353A5 publication Critical patent/JP2006130353A5/ja
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Publication of JP4085145B2 publication Critical patent/JP4085145B2/en
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Expired - Fee Related legal-status Critical Current

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停電時に、停電発生時の遊技状態から遊技を再開するためのデータを待避する停電時処理と、電源投入時に、RAMを初期化する初期化処理、前記待避したデータに従って設定処理を行うバックアップスタート設定処理のいずれかを行う電源投入時処理と、該電源投入時処理を実行後、複数のソレノイドをオン状態とする出力処理及び乱数更新処理を含む遊技の進行に係る処理を行う本処理と、該本処理の終了後に前記乱数の更新処理を行う残余処理と、を実行する手段を有する主制御基板と、
停電時に、現状の賞球払い出し状態及び球貸しの払い出し状態を示すデータを待避する停電時処理を行う払出制御基板と、を備えた遊技機であって、
前記主制御基板は、
前記電源投入時処理を終了した後、前記本処理及び前記残余処理から構成される通常時の処理を実行する通常時処理実行手段と、
強制割り込み端子に入力されるNMI制御信号が変化することで、NMIフラグを設定するバックアップ設定手段と、
時間の計時を行うタイマ手段と、
該タイマ手段により計時される前記本処理の開始からの経過時間が設定時間を経過したことを示すINTフラグを設定するタイムアップ判定手段と、
該タイムアップ判定手段によりINTフラグが設定されている場合に、前記残余処理を強制的に打ち切り、打ち切り後の処理を前記本処理の先頭へ回帰させる処理回帰手段と、
前記NMIフラグの有無を判断する処理を前記INTフラグの有無を判定する処理よりも先に実行することにより、前記NMIフラグが設定されている場合には前記INTフラグの有無に関わらず前記通常時の処理を強制的に停止させ、前記停電時処理に移行させる停電時処理移行手段と、
前記停電時処理では、前記RAMへのアクセスを禁止すると共に前記ソレノイドへの出力をオフ状態とし、前記電源投入時に前記本処理に移行する前に前記NMIフラグをオフ状態とし、前記残余処理を実行中に設定されたINTフラグを前記本処理においてオフ状態とするオフ状態設定手段と、を備え、更に、
前記払出制御基板は、前記主制御基板の強制割り込み端子に入力されるNMI制御信号が変化するときには、強制割り込み端子に入力させるNMI制御信号を変化させ前記停電時処理を行うことを特徴とする遊技機。
In the event of a power outage, a power outage process that saves data for resuming the game from the gaming state at the time of the power outage, an initialization process that initializes the RAM when the power is turned on, and a backup start setting that performs setting processing according to the saved data A power-on process for performing any one of the processes, a main process for performing a process related to the progress of the game, including an output process for turning on a plurality of solenoids and a random number update process after the power-on process is performed, A main control board having means for performing a residual process for performing the random number update process after the end of the process;
A game machine comprising a payout control board that performs processing during a power failure to save data indicating the current award ball payout state and ball lending payout state at the time of a power failure ,
The main control board is
Normal time processing execution means for executing normal processing composed of the main processing and the residual processing after finishing the power-on processing;
Backup setting means for setting the NMI flag by changing the NMI control signal input to the forced interrupt terminal;
Timer means for measuring time; and
A time-up determination means for setting an INT flag indicating that the elapsed time from the start of the main processing timed by the timer means has passed a set time;
A process regression means for forcibly aborting the residual process when the INT flag is set by the time-up determination means, and returning the process after the abort to the head of the main process ;
If the NMI flag is set by executing the process for determining the presence or absence of the NMI flag before the process for determining the presence or absence of the INT flag, the normal time is determined regardless of the presence or absence of the INT flag. Forcibly stopping the processing of the power failure, and shifting to the power failure processing, the power failure processing transition means,
In the power failure process, access to the RAM is prohibited, the output to the solenoid is turned off, the NMI flag is turned off before the main process is performed when the power is turned on, and the remaining process is executed. An OFF state setting means for setting the INT flag set in the OFF state in the main processing, and
The payout control board performs the power failure processing by changing the NMI control signal input to the forced interrupt terminal when the NMI control signal input to the forced interrupt terminal of the main control board changes. Machine.
JP2006042832A 2006-02-20 2006-02-20 Game machine Expired - Fee Related JP4085145B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006042832A JP4085145B2 (en) 2006-02-20 2006-02-20 Game machine

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006042832A JP4085145B2 (en) 2006-02-20 2006-02-20 Game machine

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2004309328A Division JP3817639B2 (en) 2004-10-25 2004-10-25 Game machine

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2006256899A Division JP4048250B2 (en) 2006-09-22 2006-09-22 Game machine
JP2007293034A Division JP4632375B2 (en) 2007-11-12 2007-11-12 Game machine

Publications (3)

Publication Number Publication Date
JP2006130353A JP2006130353A (en) 2006-05-25
JP2006130353A5 true JP2006130353A5 (en) 2006-11-09
JP4085145B2 JP4085145B2 (en) 2008-05-14

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006042832A Expired - Fee Related JP4085145B2 (en) 2006-02-20 2006-02-20 Game machine

Country Status (1)

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JP (1) JP4085145B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4632375B2 (en) * 2007-11-12 2011-02-16 株式会社高尾 Game machine

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3547775B2 (en) * 1993-08-18 2004-07-28 株式会社三共 Gaming machine
JPH1085421A (en) * 1996-09-17 1998-04-07 Sankyo Kk Game machine
JP2000286614A (en) * 1999-03-31 2000-10-13 Kokusai Electric Co Ltd Connecting structure for microstrip line

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