JP2006098495A - 表示装置 - Google Patents
表示装置 Download PDFInfo
- Publication number
- JP2006098495A JP2006098495A JP2004281666A JP2004281666A JP2006098495A JP 2006098495 A JP2006098495 A JP 2006098495A JP 2004281666 A JP2004281666 A JP 2004281666A JP 2004281666 A JP2004281666 A JP 2004281666A JP 2006098495 A JP2006098495 A JP 2006098495A
- Authority
- JP
- Japan
- Prior art keywords
- driving
- wiring
- substrate
- wiring conductor
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
【解決手段】
表示画素を形成する表示電極が形成された一対の基板1、2と、一方の基板2上に形成され且つ表示電極に接続する配線導体と、前記駆動用ICの実装領域内で配線導体に接続し且つ表示画素の選択を制御する駆動用ICとを有するとともに、前記配線導体と前記駆動用IC7とをバンプ71及び異方性導電樹脂部材9を介して接続してなる表示装置である。そして、前記駆動用IC実装領域内に配置された配線導体85と、前記駆動用ICの実装面の配線パターン71との間は、その電界強度が1M(メガ)V/m以下となるように、配線導体85と配線パターン71との間隔を広げた。
【選択図】 図6
Description
2・・・第2の基板
3・・・表示部材層(液晶層)
4・・・シール部材
7・・・駆動用IC
72・・配線パターン
81〜85・・・配線導体
9・・・異方性導電樹脂部材
2・・・保護樹脂
Claims (2)
- 表示画素を形成する表示電極が形成された一対の基板と、該一対の基板間に介在された表示部材層と、一方の基板上に実装される駆動用ICと、一方の基板上に形成されるとともに、前記駆動用ICに入力電源を供給する配線導体とを有するとともに、前記配線導体と前記駆動用ICとをバンプ及び異方性導電樹脂部材を介して接続してなる表示装置であって、
前記駆動用ICの実装領域内に形成された入力電源を供給する配線導体と、前記駆動用ICに形成された配線パターンとの間は、その電界強度が1M(メガ)V/m以下となるように、前記配線導体と前記配線パターンとを離間したことを特徴とする表示装置。 - 前記駆動用ICの実装領域内に形成された入力電源を供給する配線導体と、前記駆動用ICの配線パターンとの間の電圧差の絶対値がN V(ボルト)であり、且つ該配線導体と前記駆動用ICの配線パターンとの平面方向の距離をN μm以上としたことを特徴とする請求項1に記載の表示装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004281666A JP2006098495A (ja) | 2004-09-28 | 2004-09-28 | 表示装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004281666A JP2006098495A (ja) | 2004-09-28 | 2004-09-28 | 表示装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006098495A true JP2006098495A (ja) | 2006-04-13 |
Family
ID=36238411
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004281666A Pending JP2006098495A (ja) | 2004-09-28 | 2004-09-28 | 表示装置 |
Country Status (1)
Country | Link |
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JP (1) | JP2006098495A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8299597B2 (en) | 2008-07-14 | 2012-10-30 | Samsung Electronics Co., Ltd. | Semiconductor chip, wiring substrate of a semiconductor package, semiconductor package having the semiconductor chip and display device having the semiconductor package |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0926593A (ja) * | 1995-07-11 | 1997-01-28 | Hitachi Ltd | 液晶表示装置 |
JPH11142871A (ja) * | 1997-11-12 | 1999-05-28 | Casio Comput Co Ltd | 配線基板 |
JP2002140042A (ja) * | 2000-10-31 | 2002-05-17 | Hitachi Ltd | 液晶表示装置 |
JP2003176473A (ja) * | 2001-12-11 | 2003-06-24 | Matsushita Electric Ind Co Ltd | 接合材料、接合材料の設計方法および接合構造体 |
JP2004184884A (ja) * | 2002-12-06 | 2004-07-02 | Casio Comput Co Ltd | 表示装置 |
-
2004
- 2004-09-28 JP JP2004281666A patent/JP2006098495A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0926593A (ja) * | 1995-07-11 | 1997-01-28 | Hitachi Ltd | 液晶表示装置 |
JPH11142871A (ja) * | 1997-11-12 | 1999-05-28 | Casio Comput Co Ltd | 配線基板 |
JP2002140042A (ja) * | 2000-10-31 | 2002-05-17 | Hitachi Ltd | 液晶表示装置 |
JP2003176473A (ja) * | 2001-12-11 | 2003-06-24 | Matsushita Electric Ind Co Ltd | 接合材料、接合材料の設計方法および接合構造体 |
JP2004184884A (ja) * | 2002-12-06 | 2004-07-02 | Casio Comput Co Ltd | 表示装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8299597B2 (en) | 2008-07-14 | 2012-10-30 | Samsung Electronics Co., Ltd. | Semiconductor chip, wiring substrate of a semiconductor package, semiconductor package having the semiconductor chip and display device having the semiconductor package |
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